ISSCC 2020
Session 29
RF & Wireless
A 660-to-676GHz 4×2 Oscillator-Radiator Array with Intrinsic Frequency-Filtering Feedback for Harmonic Power Boost Achieving 7.4dBm EIRP in 40nm CMOS
The THz region of the electromagnetic spectrum is gaining interest due to its unique spectroscopic properties that make it useful for gas detection, biological imaging, and accurate timekeeping. While several techniques
ISSCC 2020
Session 29
RF & Wireless
A 0.59THz Beam-Steerable Coherent Radiator Array with 1mW Radiated Power and 24.1dBm EIRP in 40nm CMOS
In THz imaging systems, signal sources are needed to provide illumination of objects. In several reported imaging systems working at 0.3THz, 0.62THz, and 0.81THz, an output power around 1mW is required to achieve an acce
ISSCC 2020
Session 24
RF & Wireless
A 15dBm 12.8%-PAE Compact D-Band Power Amplifier with Two-Way Power Combining in 16nm FinFET CMOS
The drive for higher data-rates has led to the allocation of the spectrum above 100GHz for D-band communication. A high level of integration in a nm-CMOS technology is necessary to keep the cost low and allow for efficie
ISSCC 2019
Session 20
Data Converters
A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step
Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs
ISSCC 2018
Session 26
RF & Wireless
A Coupled-RTWO-Based Subharmonic Receiver FrontEnd for 5G E-Band Backhaul Links in 28nm Bulk CMOS
A fully integrated receiver for high-capacity 5G E-Band Backhaul links (71 to 76GHz and 81 to 86GHz) needs a local-oscillator (LO) distribution network with >19% tuning range (TR) and accurate quadrature phases. Further,
ISSCC 2018
Session 21
Other
Mixed-Signal Programmable Non-Linear Interface for Resource-Efficient Multi-Sensor Analytics
many portable always-awake and multi-sensor systems, the power consumption is dominated by digital backend processing [1] for feature-computation and classification. Recent Analog-to-Information based innovations (see Fi
ISSCC 2017
Session 14
AI / ML
ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI
ConvNets, or Convolutional Neural Networks (CNN), are state-of-the-art classification algorithms, achieving near-human performance in visual recognition
ISSCC 2017
Session 10
Power Management
A 1.1W/mm2-Power-Density 82%-Efficiency Fully Integrated 3:1 Switched-Capacitor DC-DC Converter in Baseline 28nm CMOS Using Stage Outphasing and Multiphase Soft-Charging
Over the past years, delivering power to integrated circuits has become increasingly difficult. With the current intake of many modern-day applications growing each new process generation, the Power Delivery Network (PDN
ISSCC 2016
Session 20
RF & Wireless
A 68.1-to-96.4GHz Variable-Gain Low-Noise Amplifier in 28nm CMOS
To allow a maximum theoretical data-rate of 25Gb/s over a 1km distance using 64QAM, an E-Band system should feature a 20dBm-output-power TX and an RX with 10dB maximum noise figure (NF) over two bands of 5GHz from 71 to
ISSCC 2016
Session 12
Power Management
A 94.6%-Efficiency Fully Integrated SwitchedCapacitor DC-DC Converter in Baseline 40nm CMOS Using Scalable Parasitic Charge Redistribution
In recent years, there has been an ever-increasing interest in monolithic power supplies. Integrating the power supply with the application has many direct benefits, including a reduction of the bill of materials and red
ISSCC 2015
Session 24
Other
Context-Aware Hierarchical Information-Sensing in a 6µW 90nm CMOS Voice Activity Detector
The rise of always-listening sensors integrated in energy-scarce devices such as watches and remote-controls increases the need for intelligent scalable interfaces. Contemporary sensor interfaces digitize raw sensor data
ISSCC 2015
Session 24
Other
Circuit Challenges from Cryptography
similar to applications in other fields. We have to worry about comparable optimization goals: area, power, energy, throughput and/or latency. Moore’s law helps to attain these goals. However, it also gives the attackers
ISSCC 2015
Session 10
Wireline I/O
An FSK Plastic Waveguide Communication Link in 40nm CMOS
Technology scaling has enabled RF-CMOS circuits that operate in the millimeterwave frequency range (30 to 300GHz) where large bandwidths are available. These bandwidths can be exploited to increase data-rates of wireless
ISSCC 2014
Session 3
AI / ML
A Dual-Mode Transformer-Based Doherty LTE Power Amplifier in 40nm CMOS
Modern high-data-rate communication systems such as LTE use spectrally efficient modulation schemes with a high peak-to-average power ratio (PAPR), placing stringent linearity demands on the RF power amplifiers (PA). The
ISSCC 2014
Session 3
AI / ML
A Transformer-Coupled True-RMS Power Detector in 40nm CMOS
To optimize the power consumption and system performance of battery-supplied devices, it is required to monitor and adjust the transmitted RF power accurately and continuously. This is typically done by an external power
ISSCC 2014
Session 27
Digital Circuits
A 210mV 5MHz Variation-Resilient Near-Threshold JPEG Encoder in 40nm CMOS
Operating circuits in the near-threshold region enables large energy savings. However, such circuits also pose many challenges, such as increased delay, unwanted leakage paths and high sensitivity to variations. Working
ISSCC 2014
Session 14
mm-Wave
A Push-Pull mm-Wave Power Amplifier with <0.8° AM-PM Distortion in 40nm CMOS
Millimeter-Wave standards like IEEE 802.15.3c and the new 802.11ad have classifications of their PHY to support single-carrier mode and more complex OFDM mode (high-speed interface) with high peak-to-average ratio (PAPR)
ISSCC 2014
Session 14
mm-Wave
A 0.9V 20.9dBm 22.3%-PAE E-Band Power Amplifier with Broadband Parallel-Series Power Combiner in 40nm CMOS
The 71-to-76GHz and 81-to-86GHz bands (known as E-band) exhibit low atmospheric attenuation and are allocated by FCC and CEPT for long-haul transmission. They enable multi-Gb/s fixed-link services such as fiber extension
ISSCC 2012
Session 21
Analog Circuits
On-Chip Gain Reconfigurable 1.2V 24µW Chopping Instrumentation Amplifier with Automatic Resistor Matching in 0.13µm CMOS
Motivated by low-voltage, low-power and small-size requirements of biomedical and energy scavenging circuits, this work introduces a fully integrated instrumentation amplifier (IA) running at 1.2V with a power consumptio
ISSCC 2011
Session 27
Data Converters
A 1.7mW 11b 1-1-1 MASH ΔΣ Time-to-Digital Converter
SCK-CEN, Mol, Belgium 3 KH Kempen, Geel, Belgium The frequency of the relaxation oscillator can be expressed as IREF/(VREF·2C). By correlating VREF and IREF as VREF = IREF·R, its frequency becomes only dependant on passi
ISSCC 2011
Session 27
Data Converters
A 250mV 7.5µW 61dB SNDR CMOS SC ΔΣ Modulator Using a Near-Threshold-Voltage-Biased CMOS Inverter Technique
One of the most continuous trends in solid-state circuits is the decrease in power supply as a direct consequence of technology scaling. The fact that Vt does not scale linearly with supply voltage has encouraged several
ISSCC 2011
Session 16
mm-Wave
A 120GHz 10Gb/s Phase-Modulating Transmitter in 65nm LP CMOS
This paper presents a 120GHz fully integrated 65nm low power (LP) CMOS transmitter that achieves data rates above 10Gb/s. At these high frequencies an extremely high bandwidth is available. This allows multi-gigabit-per-