技术领域

AI / ML

231 篇相关论文 (2008–2026)

ISSCC 2018 Session 31 AI / ML
A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with Sub-16ns Multiply-andAccumulate for Binary DNN AI Edge Processors
Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li,
Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang National Tsing Hua University, Hsinc
ISSCC 2018 Session 31 AI / ML
Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study
Tony F. Wu1, Haitong Li1, Ping-Chen Huang2, Abbas Rahimi2,
Jan M. Rabaey2, H.-S. Philip Wong1, Max M. Shulaker3, Subhasish Mitra1 Stanford University, Stanford, CA University of California, Berkeley, Berkeley, CA 3 Massachusetts Institute of Technology, Cambridge, MA 1 2 We demo
ISSCC 2018 Session 31 AI / ML
A 42pJ/Decision 3.12TOPS/W Robust In-Memory Machine Learning Classifier with On-Chip Training
Sujan Kumar Gonugondla, Mingu Kang, Naresh Shanbhag
Embedded sensory systems (Fig. 31.2.1) continuously acquire and process data for inference and decision-making purposes under stringent energy constraints. These always-ON systems need to track changing data statistics a
ISSCC 2018 Session 31 AI / ML
Conv-RAM: An Energy-Efficient SRAM with Embedded Convolution Computation for Low-Power CNN-Based Machine Learning Applications
Avishek Biswas, Anantha P. Chandrakasan, charge-sharing is used to integrate the lower of the 2 voltage rails with a ref
local column that replicates the local bit-line capacitance. This process continues until the voltage of the rail being integrated exceeds the other one, at which point the SA output flips. This signals conversion comple
ISSCC 2018 Session 26 AI / ML
A Compact Dual-Band Digital Doherty Power Amplifier Using Parallel-Combining Transformer for Cellular NB-IoT Applications
Yun Yin, Liang Xiong, Yiting Zhu, Bowen Chen, Hao Min, Hongtao Xu
Narrowband Internet-of-Things (NB-IoT) is a newly developed 3GPP protocol optimized for low-power wide-area IoT applications and is evolving toward the future fifth-generation (5G) mobile communication. It specifies at l
ISSCC 2018 Session 26 AI / ML
A 28GHz 41%-PAE Linear CMOS Power Amplifier Using a Transformer-Based AM-PM DistortionCorrection Technique for 5G Phased Arrays
Sheikh Nijam Ali1, Pawan Agarwal2, Joe Baylon1, Srinivasan Gopal1,
high data-rates, the millimeter-wave (mmW) 5G communication standard will extensively use high-order complex-modulation schemes (e.g., QAM) with high peak-to-average power ratios (PAPRs) and large RF bandwidths. High-eff
ISSCC 2018 Session 21 AI / ML
A 1μW Voice Activity Detector Using Analog Feature Extraction and Digital Deep Neural Network
Minhao Yang, Chung-Heng Yeh, Yiyin Zhou, Joao P. Cerqueira,
Aurel A. Lazar, Mingoo Seok Columbia University, New York, NY Voice user interfaces (UIs) are highly compelling for wearable and mobile devices. They have the advantage of using compact and ultra-low-power (ULP) input de
ISSCC 2018 Session 15 AI / ML
An 82-to-108GHz -181dB-FOMT ADPLL Employing a DCO with Split-Transformer and Dual-Path SwitchedCapacitor Ladder and a Clock-Skew-Sampling DeltaSigma TDC
Zhiqiang Huang, Howard Cam Luong, HKUST, Hong Kong, China, Existing ADPLLs in [1] are limited to 60GHz and are not capab
the W-band. At 100GHz, DCOs become more sensitive to parasitics resulting in low frequency resolution. A high-resolution delta-sigma TDC is used to reduce quantization noise by noise-shaping in [2], but it suffers from l
ISSCC 2018 Session 13 AI / ML
A 232-to-1996KS/s Robust Compressive-Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring
Ting-Sheng Chen, Hung-Chi Kuo, An-Yeu Wu
Compressive sensing (CS) techniques enable new reduced-complexity designs for sensor nodes and help reduce overall transmission power in wireless sensor network [1-2]. Prior CS reconstruction chip designs have been descr
ISSCC 2018 Session 13 AI / ML
A 1.8Gb/s 70.6pJ/b 128×16 Link-Adaptive Near-Optimal Massive MIMO Detector in 28nm UTBB-FDSOI
Wei Tang1, Hemanth Prabhu2, Liang Liu2, Viktor Öwall2, Zhengya Zhang1
Lund University, Lund, Sweden data movements using holding buffers to maximize data reuse. The data reuse is especially advantageous in our design, as it requires a relatively long 28b data bit width to support a wide ra
ISSCC 2018 Session 13 AI / ML
An Always-On 3.8μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28nm CMOS
Daniel Bankman1, Lita Yang1, Bert Moons2, Marian Verhelst2, Boris Murmann1
latency, bandwidth, and privacy has created demand for low-energy deep convolutional neural networks (CNNs). The single-layer classifier in [1] achieves sub-nJ operation, but is limited to moderate accuracy on low-comple
ISSCC 2018 Session 13 AI / ML
A 9.02mW CNN-Stereo-Based Real-Time 3D Hand-Gesture Recognition Processor for Smart Mobile Devices
Sungpill Choi, Jinsu Lee, Kyuho Lee, Hoi-Jun Yoo
Recently, 3D hand-gesture recognition (HGR) has become an important feature in smart mobile devices, such as head-mounted displays (HMDs) or smartphones for AR/VR applications. A 3D HGR system in Fig. 13.4.1 enables user
ISSCC 2018 Session 13 AI / ML
UNPU: A 50.6TOPS/W Unified Deep Neural Network Accelerator with 1b-to-16b Fully-Variable Weight Bit-Precision
Jinmook Lee, Changhyeon Kim, Sanghoon Kang, Dongjoo Shin,
deep learning algorithms from face recognition to emotion recognition in mobile or embedded environments [3]. However, most works accelerate only the convolutional layers (CLs) or fully-connected layers (FCLs), and diffe
ISSCC 2018 Session 13 AI / ML
QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS
Kodai Ueyoshi1, Kota Ando1, Kazutoshi Hirose1,
Shinya Takamaeda-Yamazaki1, Junichiro Kadomoto2, Tomoki Miyata2, Mototsugu Hamada2, Tadahiro Kuroda2, Masato Motomura1 Hokkaido University, Sapporo, Japan Keio University, Yokohama, Japan 1 2 A key consideration for deep
ISSCC 2018 Session 10 AI / ML
A 0.3ppm Dual-Resonance Transformer-Based DriftCancelling Reference-Free Magnetic Sensor for Biosensing Applications
Constantine Sideris, Parham Porsandeh Khial, Bill Ling, Ali Hajimiri
Cost-efficient, point-of-use diagnostics are critical for early disease detection. Traditionally, the majority of lab-based analysis equipment utilizes fluorescent markers for biodetection assays. However, magnetic-based
ISSCC 2017 Session 14 AI / ML
ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI
Bert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst
ConvNets, or Convolutional Neural Networks (CNN), are state-of-the-art classification algorithms, achieving near-human performance in visual recognition
ISSCC 2017 Session 14 AI / ML
DNPU: An 8.1TOPS/W Reconfigurable CNN-RNN Processor for General-Purpose Deep Neural Networks
Dongjoo Shin, Jinmook Lee, Jinsu Lee, Hoi-Jun Yoo
Recently, deep learning with convolutional neural networks (CNNs) and recurrent neural networks (RNNs) has become universal in all-around applications. CNNs are used to support vision recognition and processing, and RNNs
ISSCC 2017 Session 14 AI / ML
A 2.9TOPS/W Deep Convolutional Neural Network SoC in FD-SOI 28nm for Intelligent Embedded Systems
Giuseppe Desoli1, Nitin Chawla2, Thomas Boesch3, Surinder-pal Singh2,
Elio Guidetti1, Fabio De Ambroggi4, Tommaso Majo1, Paolo Zambotti4, Manuj Ayodhyawasi2, Harvinder Singh2, Nalin Aggarwal2 STMicroelectronics, Cornaredo, Italy STMicroelectronics, Greater Noida, India 3 STMicroelectronics
ISSCC 2016 Session 14 AI / ML
A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems
Jaehyeong Sim, Jun-Seok Park, Minhye Kim, Dongmyung Bae,
Internet-ofEverything (IoE) devices to data center servers for intelligent recognition processes is impractical for energy reasons, requiring in-situ processing of such data. However, algorithms accelerated by previous r
ISSCC 2016 Session 14 AI / ML
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
Yu-Hsin Chen1, Tushar Krishna1, Joel Emer1,2, Vivienne Sze1
Nvidia, Westford, MA 1 2 Deep learning using convolutional neural networks (CNN) gives state-of-the-art accuracy on many computer vision tasks (e.g. object detection, recognition, segmentation). Convolutions account for
ISSCC 2016 Session 14 AI / ML
A 502GOPS and 0.984mW Dual-Mode ADAS SoC with RNN-FIS Engine for Intention Prediction in Automotive Black-Box System
Kyuho J. Lee, Kyeongryeol Bong, Changhyeon Kim, Jaeeun Jang,
forward-collision warning, advanced emergency braking, adaptive cruise control, and lane-keeping assistance. Recently, automotive black boxes are installed in cars for tracking accidents or theft. In this paper, a dual-m
ISSCC 2015 Session 4 AI / ML
A 1.93TOPS/W Scalable Deep Learning/Inference Processor with Tetra-Parallel MIMD Architecture for Big-Data Applications
Seongwook Park, Kyeongryeol Bong, Dongjoo Shin, Jinmook Lee,
analysis in image retrieval with high accuracy [1]. As Fig. 4.6.1 shows, various applications, such as text, 2D image and motion recognition use DL due to its best-in-class recognition accuracy. There are 2 types of DL:
ISSCC 2014 Session 7 AI / ML
A 1000fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array and Self-Organizing Map Neural Network
Cong Shi1,2, Jie Yang1, Ye Han1, Zhongxiang Cao1, Qi Qin1,
that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial aut
ISSCC 2014 Session 3 AI / ML
A Dual-Mode Transformer-Based Doherty LTE Power Amplifier in 40nm CMOS
Ercan Kaymaksut, Patrick Reynaert
Modern high-data-rate communication systems such as LTE use spectrally efficient modulation schemes with a high peak-to-average power ratio (PAPR), placing stringent linearity demands on the RF power amplifiers (PA). The
ISSCC 2014 Session 3 AI / ML
A Transformer-Coupled True-RMS Power Detector in 40nm CMOS
Brecht Francois, Patrick Reynaert
To optimize the power consumption and system performance of battery-supplied devices, it is required to monitor and adjust the transmitted RF power accurately and continuously. This is typically done by an external power
ISSCC 2014 Session 10 AI / ML
A 1.22TOPS and 1.52mW/MHz Augmented Reality Multi-Core Processor with Neural Network NoC for HMD Applications
Gyeonghoon Kim, Youchang Kim, Kyuho Lee, Seongwook Park,
augmentation of images in a real-world environment. Wearable systems, such as head-mounted display (HMD) systems, have attempted to support real-time AR as a next generation UI/UX [1-2], but have failed, due to their lim
ISSCC 2012 Session 5 AI / ML
A 40mV Transformer-Reuse Self-Startup Boost Converter with MPPT Control for Thermoelectric Energy Harvesting
Jong-Pil Im1, Se-Won Wang1, Kang-Ho Lee1, Young-Jin Woo2,
(µEHs) is increasing (for seamless energy source in applications such as wireless sensor node), two major problems still obstruct versatile use of them. The first problem is the self-startup capability. Because many wire
ISSCC 2011 Session 6 AI / ML
A ±1.5% Nonlinearity 0.1-to-100A Shunt Current Sensor Based on a 6kV Isolated Micro-Transformer for Electrical Vehicles and Home Automation
Frederic Rothan1, Helene Lhermet1, Brice Zongo1, Cyril Condemine1,
techniques has been developed to satisfy various electrical and electronics applications requirements [1,2]. In high-voltage applications, the main issue is the electrical isolation with accurate measurement at low signa
ISSCC 2011 Session 24 AI / ML
A Flip-Chip-Packaged 1.8V 28dBm Class-AB Power Amplifier with Shielded Concentric Transformers in 32nm SoC CMOS
Yulin Tan, Hongtao Xu, Mohammed A El-tanani, Stewart Taylor, Hasnain Lakdawala
Intel, Hillsboro, OR As CMOS technology continues to scale for SoC applications, significant challenges to implement a monolithic linear high-power amplifier have emerged. This results from the low breakdown voltage of t
ISSCC 2010 Session 18 AI / ML
A 345mW Heterogeneous Many-Core Processor with an Intelligent Inference Engine for Robust Object Recognition
Seungjin Lee, Jinwook Oh, Minsu Kim, Junyoung Park, Joonsoo Kwon, Hoi-Jun Yoo
challenges: (1) the large number of features to process requires high computational power, and (2) false matches from background clutter can degrade recognition accuracy. Previously, saliency based bottom-up visual atten
ISSCC 2008 Session 31 AI / ML
A 60GHz 1V +12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS
Debopriyo Chowdhury, Patrick Reynaert, Ali M. Niknejad
The opening up of the mm-wave band has created opportunities for high-data-rate communication, radar and medical imaging. The cost and size advantages of CMOS have motivated research on 60GHz CMOS front-end design [1]. H