ISSCC 2008
Session 23
Memory
A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm
Shouchang Tsao1, Tai-Yuan Tseng1, Khanh Nguyen1, Jason Li1, Jayson Hu1, Jong Park1, Cynthia Hsu1, Fanglin Zhang1, Teruhiko Kamei1, Hiroaki Nasu1, Phil Kliza1, Khin Htoo1, Jeffrey Lutze1, Yingda Dong1, Masaaki Higashitani
ISSCC 2008
Session 21
Memory
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices
Network security is in high demand because of increasing network attacks. As mobile devices have limited CPU power, dedicated hardware is required to provide sufficient virus detection performance with a small energy cos
ISSCC 2008
Session 21
Memory
A 32kb 10T Subthreshold SRAM Array with BitInterleaving and Differential Read Scheme in 90nm CMOS
J. Watson, Yorktown Heights, NY 2 For robust subthreshold SRAMs, 8T or 10T subthreshold SRAMs based on single-ended read sensing have been proposed [1-3]. While the schemes in [1-3] improve the read stability and writabi
ISSCC 2008
Session 21
Memory
A 100nm Double-Stacked 500MHz 72Mb SeparateI/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy
Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim Samsung Electronics, Hwasung, Korea As multi-core processors become mainstream, the demand for high-density cache
ISSCC 2008
Session 21
Memory
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS
Hitachi, Tokyo, Japan, 2Renesas Technology, Tokyo, Japan Increasing Vth variation is becoming a serious problem in SoCs. Especially in SRAM, Vth variation has a critical impact on operating margins. Self-repairing SRAM [
ISSCC 2008
Session 21
Memory
A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-β-ratio Memory Cell
A. Tohata2, T. Sasaki1, A. Katayama1, G. Fukano1, Y. Fujimura1, N. Otsuka1 1 Toshiba Semiconductor, Kawasaki, Japan Toshiba Microelectronics, Kawasaki, Japan 2 A single-power supply 64kB SRAM is fabricated in a 45nm bulk
ISSCC 2008
Session 21
Memory
A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing
High-density SRAMs are a primary contributor to the dramatic cost reductions and expanding features of ICs every technology node. Unfortunately, their small bit-cell devices have large variation, and the ensuing degradat
ISSCC 2008
Session 21
Memory
A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management
45nm SOI technology [1]. The macro is adapted for use as the principal growable embedded-SRAM block in a 45nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves
ISSCC 2008
Session 21
Memory
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-κ Metal-Gate CMOS Technology
drive the increase of on-die memory density to meet performance needs in various applications such as microprocessors. Meanwhile, the device variation and leakage are increasing as the miniaturization of the transistor c
ISSCC 2008
Session 14
Memory
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology
Ji Yeon Yang, Hyeng Ouk Lee, Dong Uk Lee, Sujeong Sim, Young Ju Kim, Won Jun Choi, Keun Soo Song, Sang Hoon Shin, Hyang Hwa Choi, Hyung Wook Moon, Seung Wook Kwack, Jung Woo Lee, Young Kyoung Choi, Nak Kyu Park, Kwan Weo
ISSCC 2008
Session 14
Memory
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface
Young Kyoung Choi, Jung Woo Lee, Seung Wook Kwack, Hyeong Ouk Lee, Won Joo Yun, Sang Hoon Shin, Kwan Weon Kim, Young Jung Choi, Ye Seok Yang Hynix Semiconductor, Icheon, Korea After the development of graphics DRAM inter
ISSCC 2008
Session 14
Memory
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
Dae-Hyun Chung, Jin-Gook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Ka
ISSCC 2008
Session 14
Memory
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications
Atsushi Suzuki1, Tomohisa Takai1, Naoko Itoga1, Takayuki Miyazaki1, Takayuki Iwai1, Hiroyuki Takenaka2, Takehiko Hojo1, Shinji Miyano1, Nobuaki Otsuka1 1 Toshiba, Kawasaki, Japan, 2Toshiba Microelectronics, Kawasaki, Jap
ISSCC 2008
Session 14
Memory
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process
Muhammad Khellah, Jason Howard, Greg Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi Intel, Hilsboro, OR As silicon technology scales, the possibility of fabricating dense memories [1-4] is of great inter
ISSCC 2008
Session 14
Memory
A 170GB/s 16Mb Embedded DRAM with Data-Bus Charge-Recycling
Mike Mound1, G.W. Jones1, Tim Egging1, Tomofumi Arakawa2, Katsuhiko Sasahara2, Kazuo Taniguchi2, Masayuki Miyabayashi2 United Memories, Colorado Springs, CO Sony Corporation, Tokyo, Japan driven to VCC and one of the GDR
ISSCC 2008
Session 14
Memory
A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS
Cormac O’Connelll, Sreedhar Natarajan1, Chris Huang2, Chuan-Yu Wu2, Min-Jer Wang2, C. J. Wang2, Paul Chen2, Rick Hsieh2 1 TSMC Design Technology Canada, Kanata, Canada TSMC, Hsinchu, Taiwan 2 From 90nm and below, SoC int
← 上一页 · 第 6/6 页 · 共 266 篇