ISSCC 2011
Session 11
Memory
A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability
Yu-Sheng Chen1,2, Pi-Feng Chiu1,2, Chia-Chen Kuo2, Yih-Shan Yang2, Pei-Chia Chiang1, Wen-Pin Lin1, Che-He Lin1, Heng-Yuan Lee1, Pei-Yi Gu1, Sum-Min Wang1, Frederick T. Chen1, Keng-Li Su1, Chen-Hsin Lien2, Kuo-Hsing Cheng
ISSCC 2011
Session 11
Memory
A 151mm2 64Gb MLC NAND Flash Memory in 24nm CMOS Technology
Junpei Sato1, Teruo Takagiwa1, Naoaki Kanagawa1, Hitoshi Shiga1, Naoya Tokiwa1, Yoshihiko Shindo1, Toshiaki Edahiro1, Takeshi Ogawa1, Makoto Iwai1, Osamu Nagao1, Junji Musha1, Takatoshi Minamoto1, Kosuke Yanagidaira1, Yu
ISSCC 2010
Session 24
Memory
A 32Gb MLC NAND-Flash Memory with Vth-EnduranceEnhancing Schemes in 32nm CMOS
Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, InSuk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jaekwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan Kim, Jeawon Choi
ISSCC 2010
Session 24
Memory
A 3bit/Cell 32Gb NAND Flash Memory at 34nm with 6MB/s Program Throughput and with Dynamic 2b/Cell Blocks Configuration Mode for a Program Throughput Increase up to 13MB/s
C. Lattaro1, C. Musilli1, D. Rivers2, E. Sirizotti1, F. Paolini1, G. Imondi1, G. Naso1, G. Santin1, L. Botticchio1, L. De Santis1, L. Pilolli1, M.L. Gallese1, M. Incarnati1, M. Tiburzi1, P. Conenna1, S. Perugini1, V. Mos
ISSCC 2010
Session 24
Memory
A 159mm2 32nm 32Gb MLC NAND-Flash Memory with 200MB/s Asynchronous DDR Interface
Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyun Cho, Juseok Lee, Jungho Song, Soowoong Lee, Hyukjun Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, Kyehyun Kyung, Yong-Ho Lim, Chilhee Chung
ISSCC 2010
Session 24
Memory
A 2Gb/s 1.8pJ/b/chip Inductive-Coupling ThroughChip Bus for 128-Die NAND-Flash Memory Stacking
NAND Flash memory chips and 1 controller chip are stacked in a single package for SSD applications (Fig. 24.5.1). The controller chip accesses a random memory chip by relayed transmission using inductive-coupling transce
ISSCC 2010
Session 24
Memory
A Bitline Sense Amplifier for Offset Compensation
DRAM chips [1]. To satisfy this need, it is desirable to use a low VCORE in the DRAM core, even though with such a low voltage it is difficult to sense the cell signal due to an insufficient sensing margin in high densit
ISSCC 2010
Session 24
Memory
An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR Inductive-Coupling Interface Between 65nm CMOS GPU and 0.1µm DRAM
This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating
ISSCC 2010
Session 24
Memory
Paper withdrawn by author • 2010 IEEE International Solid-State Circuits Conference 978-1-4244-6034-2/10/$26.00 ©2010 IEEE
ISSCC 2010
Session 24
Memory
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns Bank-to-Bank Active Time and No Bank-Group Restriction
Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang,
ISSCC 2010
Session 19
Memory
A 0.5V 100MHz PD-SOI SRAM with Enhanced Read Stability and Write Margin by Asymmetric MOSFET and Forward Body Bias
characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1-3]. However, it is still difficult to achieve low-voltage operation (less than
ISSCC 2010
Session 19
Memory
SRAM Stability Characterization Using Tunable Ring Oscillators in 45nm CMOS
J. Watson, Yorktown Heights, NY 2 It is desirable to observe the cell read current at lower cell supplies. Lowering the array supply voltage VCELL can magnify the effect of read disturbance that raises the internal node
ISSCC 2010
Session 19
Memory
PVT-and-Aging Adaptive Wordline Boosting for 8T SRAM Power Reduction
19.6.1) is commonly used in single-VCC microprocessor core for its performance critical low-level caches and multi-ported register-file arrays
ISSCC 2010
Session 19
Memory
A 512kb 8T SRAM Macro Operating Down to 0.57V with An AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45nm SOI CMOS
J. Watson, Yorktown Heights, NY There is a need for large embedded memory that operates over a wide range of supply voltage compatible with the limits of static CMOS logic that also minimizes standby power [1,2]. A 512kb
ISSCC 2010
Session 19
Memory
A Configurable SRAM with Constant-Negative-Level Write Buffer for Low-Voltage Operation with 0.149µm2 Cell in 32nm High-κ Metal-Gate CMOS
Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe Toshiba Semiconductor, Kawasaki, Japan This paper presents a configurable SRAM for low-voltage operation with co
ISSCC 2010
Session 19
Memory
A 32nm High-κ Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation
performance, and density requirements as Moore’s law continues to drive CMOS technology scaling. Due to process variation, SRAM bitcell design margin continues to shrink in scaled technologies and conventional SRAM is no
ISSCC 2010
Session 19
Memory
A 32kB 2R/1W L1 Data Cache in 45nm SOI Technology for the POWER7TM Processor
Wolfgang Penth1, Thomas Froehnel1, Stefan Buettner1, Otto Torreiter1, Martin Eckert1, Jose Paredes2, David Hrusecky2, David Ray2, Miles Canada3 1 IBM, Boeblingen, Germany IBM, Austin, TX 3 IBM, Burlington, VT 2 Increasin
ISSCC 2010
Session 19
Memory
A 45nm SOI Embedded DRAM Macro for POWER7TM 32MB On-Chip L3 Cache
Gregory Fredeman2, Michael Sperling2, Abraham Mathews3, William Reohr4, Kavita Nair2, Nianzheng Cao2 1 IBM, Essex Junction, VT IBM, Poughkeepsie, NY 3 IBM, Austin, TX 4 IBM T. J. Watson, Yorktown Heights, NY 2 Logic-base
ISSCC 2010
Session 14
Memory
A 45nm 1Gb 1.8V Phase-Change Memory
voltage depending on the device configuration. In the voltage-forcing approach, a cell-position-compensation system is implemented to reduce the parasitic effect. The WL compensation is based on adding a resistive path t
ISSCC 2010
Session 14
Memory
A 90nm 4Mb Embedded Phase-Change Memory with 1.2V 12ns Read Access Time and 1MB/s Write Throughput
Marco Pasotti1, Massimo Borghi1, Paolo Mattavelli1, Paola Zuliani1, Luca Scotti1, Gianfranco Mastracchio1, Ferdinando Bedeschi2, Roberto Gastaldi2, Roberto Bez2 1 STMicroelectronics, Agrate Brianza, Italy Numonyx, Agrate
ISSCC 2010
Session 14
Memory
A 0.29V Embedded NAND-ROM in 90nm CMOS for Ultra-Low-Voltage Applications
Hsinchu, Taiwan 3 Fukuoka Institute of Technology, Fukuoka, Japan 2 Many low-voltage chips such as sensor networks and biomedical applications need large-capacity low-VDDmin-delay-product embedded ROM for storing fixed p
ISSCC 2010
Session 14
Memory
A 2.5Gb/s/ch 4PAM Inductive-Coupling Transceiver for Non-Contact Memory Card
An inductive-coupling link has been studied for inter-chip communications in System-in-a-Package [1]. Its communication distance extends millimeter ranges [2,3] and it can be used as a wireless interface for non-contact
ISSCC 2010
Session 14
Memory
A Scalable Shield-Bitline-Overdrive Technique for 1.3V Chain FeRAM
Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Sumiko Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Ta
ISSCC 2010
Session 14
Memory
A 0.13µm 64Mb Multi-Layered Conductive MetalOxide Memory
Sri Rama Namala, Misako Matsuoka, Bruce L Bateman, Darrell Rinerson Unity Semiconductor, Sunnyvale, CA A number of technologies have been proposed to replace NAND Flash as scaling becomes more difficult [1-2]. One promis
ISSCC 2010
Session 14
Memory
A 64Mb MRAM with Clamped-Reference and Adequate-Reference Schemes
Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe The voltage generators for t
ISSCC 2010
Session 14
Memory
Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13µm CMOS
random-access memory (MRAM) [1-3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access. However, t
ISSCC 2009
Session 7
Memory
Low-Vt Small-Offset Gated Preamplifier for Sub-1V Gigabit DRAM Arrays
achieves fast sensing, fast local I/O driving and low-leakage operation simultaneously even for low-voltage mid-point sensing. The features are verified with a 70nm 128Mb DRAM core that demonstrates 16.4ns row access (tR
ISSCC 2009
Session 7
Memory
A 1.6V 3.3Gb/s GDDR3 DRAM with Dual-Mode Phase- and Delay-Locked Loop Using Power-Noise Management with Unregulated Power Supply in 54nm CMOS
Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee,
ISSCC 2009
Session 7
Memory
A 6Gb/s/pin Pseudo-Differential Signaling Using Common-Mode Noise Rejection Techniques Without Reference Signal for DRAM Interfaces
parallel links as well as in high-speed serial links. However, differential signaling is not cost effective for DRAM interfaces because the I/O-pin count is a significant portion of the chip cost. Since differential sign
ISSCC 2009
Session 7
Memory
Single-Ended Transceiver Design Techniques for 5.33Gb/s Graphics Applications
Russell Homer1, Otto Schumacher2, Reinhold Unterricker2, Werner Kederer2 Qimonda, San Jose, CA Qimonda, Munich, Germany 1 2 Graphics processing is the driving force behind the demand for high-bandwidth DRAMs. Acceleratin
ISSCC 2009
Session 7
Memory
75nm 7Gb/s/pin 1Gb GDDR5 Graphics Memory Device with Bandwidth-Improvement Techniques
S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller, P. Petkov, M. Plan, M. Richter, I. Russell, K. Schiller, R. Schneider, K. Swaminathan, B. Weber, J. Weber, I. Bormann, F. Funfrock, M. Gjukic, W. Spirkl, H. Steffens, J. Wel
ISSCC 2009
Session 7
Memory
A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with Controllable Repeater and On-the-Fly Power-Cut Scheme for Low-Power and High-Speed Mobile Application
Lee, Duck Hwa Hong, Jae Hoon Kim, Eun Ryeong Lee, Min Chang Kim, Kyung Ha Lee, Sang Il Park, Jong Ho Son, Sang Kwon Lee, Seong Nyuh Yoo, Sung Mook Kim, Tae Woo Kwon, Jin Hong Ahn, Yong Tak Kim Hynix Semiconductor, Icheon
ISSCC 2009
Session 7
Memory
8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology
Hoon Lee, Soo-Ho Cha, Jaesung Ahn, DukMin Kwon, Jin Ho Kim, Jae-Wook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae
ISSCC 2009
Session 7
Memory
V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with Hybrid-I/O Sense Amplifier and Segmented SubArray Architecture
Seok-Hun Hyun, Byung-Chul Kim, In-Chul Jeong, Seong-Young Seo, Jun-Ho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kye-Hyun Kyung, Young-Hyun Jun, Kinam Kim Samsung Electronics, Hwasung, Korea As the workload and s
ISSCC 2009
Session 27
Memory
A 1.6GB/s DDR2 128Mb Chain FeRAM with Scalable Octal Bitline and Sensing Schemes
Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko Doumae, Shoichi Shimizu, Mitsumo Kawano
ISSCC 2009
Session 27
Memory
A 90nm 12ns 32Mb 2T1MTJ MRAM
Y. Kato1, K. Mori1, Y. Ozaki2, Y. Kobayashi2, N. Ohshima1, K. Kinoshita1, T. Suzuki1, K. Nagahara1, N. Ishiwata1, K. Suemitsu1, S. Fukami1, H. Hada1, T. Sugibayashi1, N. Kasai1 NEC, Sagamihara, Japan, 2NEC Electronics, S
ISSCC 2009
Session 27
Memory
A 2ns-Read-Latency 4Mb Embedded Floating-Body Memory Macro in 45nm SOI Technology
Philippe Bauser1, Paul de Champs1, Hamid Daghighian1, David Fisch1, Philippe Graber1, Michel Bron1 Innovative Silicon, Lausanne, Switzerland, 2AMD, Fort Collins, CO 1 To meet advancing market demands, microprocessor embe
ISSCC 2009
Session 27
Memory
A Process–Variation-Tolerant Dual-Power-Supply SRAM with 0.179µm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver
T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama, T. Yabe Toshiba Semiconductor, Kawasaki, Japan A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is
ISSCC 2009
Session 27
Memory
A 4.0 GHz 291Mb Voltage-Scalable SRAM Design in 32nm High-κ Metal-Gate CMOS with Integrated Power Management
Y. Zhang, K. Zhang, M. Bohr Intel, Hillsboro, OR CMOS technology has followed Moore’s law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for f
ISSCC 2009
Session 13
Memory
A 5.6MB/s 64Gb 4b/Cell NAND Flash Memory in 43nm CMOS
K. Isobe2, B. Le1, F. Moogat1, N. Mokhlesi1, K. Kozakai1, P. Hong1, T. Kamei1, K. Iwasa2, J. Nakai2, T. Shimizu2, M. Honma2, S. Sakai2, T. Kawaai2, S. Hoshi2, J. Yuh1, C. Hsu1, T. Tseng1, J. Li1, J. Hu1, M. Liu1, S. Khal
ISSCC 2009
Session 13
Memory
A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking
communication technique, which enables a controller chip to communicate with random access with a stack underneath it of 64 NAND Flash memory chips at a data rate of 2Gb/s using relayed transmission is developed (Fig. 13
ISSCC 2009
Session 13
Memory
A 113mm2 32Gb 3b/cell NAND Flash Memory
Shindo1, Toshiaki Edahiro1, Teruhiko Kamei2, Hiroaki Nasu2, Makoto Iwai1, Koji Kato1, Yasuyuki Fukuda1, Naoaki Kanagawa1, Naofumi Abiko1, Masahide Matsumoto2, Toshihiko Himeno1, Toshifumi Hashimoto1, Yi-Ching Liu2, Hardw
ISSCC 2009
Session 13
Memory
A 48nm 32Gb 8-Level NAND Flash Memory with 5.5MB/s Program Throughput
Jung-Chul Han, In-Soo Wang, kyu-hee Lim, Jung-Hwan Lee, Ji-Hwan Kim, Won-Kyung Kang, Tai-Kyu Kang, Hee-Su Byun, Yu-Jong Noh, Lee-Hyun Kwon, Bon-Kwang Koo, Myung Cho, Joong-Seob Yang, Yo-Hwan Koh Hynix Semiconductor, Iche
ISSCC 2009
Session 13
Memory
A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD
SSDs. A typical SSD consists of more than 16 NAND Flash memories, DRAMs and a NAND controller. Since the NAND write performance is 10MB/s [1,2], to raise the write speed of SSD to the level of HDD, 100MB/s, 8 or more NAN
ISSCC 2009
Session 13
Memory
A 172mm2 32Gb MLC NAND Flash Memory in 34nm CMOS
Matt Goldman1, Chris Haid1, Atif Huq1, Takaaki Ichikawa2, Joel Jorgensen1, Owen Jungroth1, Nishant Kajla1, Ravinder Kajley1, Koichi Kawai2, Jiro Kishimoto2, Ali Madraswala1, Tetsuji Manabe2, Vikram Mehta1, Midori Morooka
ISSCC 2008
Session 23
Memory
A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology
Koji Hosono1, Masahiro Yoshihara1, Toru Miwa2, Yosuke Kato2, Alex Mak3, Siu Lung Chan3, Frank Tsai3, Raul Cernea3, Binh Le3, Eiichi Makino1, Takashi Taira1, Hiroyuki Otake1, Norifumi Kajimura1, Susumu Fujimura1, Yoshiaki
ISSCC 2008
Session 23
Memory
A Multi-Level-Cell Bipolar-Selected Phase-Change Memory
Donze1, Meenatchi Jagasivamani2, Egidio Buda1, Fabio Pellizzer1, David Chow2, Alessandro Cabrini4, Giacomo Matteo Angelo Calvi4, Roberto Faravelli4, Andrea Fantini4, Guido Torelli4, Duane Mills2, Roberto Gastaldi1, Giuli
ISSCC 2008
Session 23
Memory
A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface
June Lee1, Erwin Yu1, Allahyar Vahidimowlavi1, Michael Abraham1, Sanjay Talreja2, Rajesh Sundaram2, Rod Rozman2, Luyen Vu1, Chih Liang Chen1, Uday Chandrasekhar1, Rupinder Bains2, Vimon Viajedor1, William Mak1, Munseork
ISSCC 2008
Session 23
Memory
A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed
Robert L. Melcher, Shahnam Khabiri, Nicholas T. Hendrickson, Andrew D. Proescholdt, David A. Ward, Mark A. Taylor Intel, Folsom, CA When transitioning to the 45nm process node, undesirable cell effects become many times
ISSCC 2008
Session 23
Memory
A 4b/Cell 8Gb NROM Data-Storage Memory with Enhanced Write Performance
Kobi Danon1, Yair Sofer1, Yoram Betser1, Amichai Givant1, Alexander Kushnarenko1, Yaal Horesh1, Ron Eliyahu1, Eduardo Maayan1, Boaz Eitan1, Wang Pei Jen2, Yan Feng2, Lin Ching Yao2, Kwon Yi Jin2, Kwon Sung Woo2, Cai En J