ISSCC 2013
Session 17
Memory
An Adaptive-Bandwidth PLL for Avoiding Noise Interference and DFE-Less Fast Precharge Sampling for over 10Gb/s/pin Graphics DRAM Interface
GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the sel
ISSCC 2013
Session 17
Memory
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s Thin-Oxide DDR Transmitter with 1.9-to-7.6V/ns Clock-Feathering Slew-Rate Control in 22nm CMOS impedance levels are controlled by the enable vectors (en_ffe_n/p[3:0] for FFE slices and en_n/p[7:0] for non-FFE slices). Typical impedance ranges are 24 to 40Ω in drive mode and 60 to 240Ω in ODT mode.
Matthias Brändli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf To save power in the predriver, the SST stages consist of thin-oxide devices, which require overvoltage protection implemented by transistors
ISSCC 2013
Session 17
Memory
A 27% Reduction in Transceiver Power for Single-Ended Point-to-Point DRAM Interface with the Termination Resistance of 4×Z0 at both TX and RX This integrator helps to reduce power and increase the robustness to highfrequency noise [1, 4-5].
in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2
ISSCC 2013
Session 17
Memory
A 6.4Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
Bill Stonecypher2, Wayne Dettloff2, Teva Stone2, Kashinath Prabhu3, Pravin Kumar Venkatesan3, Fred Heaton2, Ravi Kollipara1, Yi Lu1, Chris J. Madden1, John Eble2, Lei Luo2, Nhat Nguyen1 Rambus, Sunnyvale, CA, 2Rambus, Ch
ISSCC 2013
Session 12
Memory
Unified Solid-State-Storage Architecture with NAND Flash Memory and ReRAM that Tolerates 32× Higher BER for Big-Data Applications
Unified solid-state storage (USSS) provides high error tolerance with four techniques: reverse-mirroring (RM), error-reduction synthesis (ERS), page-RAID, and error-masking (EM). The acceptable raw bit-error rate (ABER)
ISSCC 2013
Session 12
Memory
Cycling Endurance Optimization Scheme for 1Mb STT-MRAM in 40nm Technology
Yu-Der Chih, Tong-Chern Ong, Jonathan Chang, Sreedhar Natarajan, Luan C. Tran TSMC, Hsinchu, Taiwan Spin-transfer-torque (STT) MRAM is considered as a good candidate for nextgeneration memory that can replace Flash, SRAM
ISSCC 2013
Session 12
Memory
A 45nm 6b/cell Charge-Trapping Flash Memory Using LDPC-Based ECC and Drift-Immune Soft-Sensing Engine
multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becom
ISSCC 2013
Session 12
Memory
Filament Scaling Forming Technique and Level-Verify-Write Scheme with Endurance Over 107 Cycles in ReRAM
Ryotaro Azuma1, Yuhei Yoshimoto1, Kouhei Tanabe2, Zhiqiang Wei1, Takeki Ninomiya1, Koji Katayama1, Ryutaro Yasuhara1, Shunsaku Muraoka1, Atsushi Himeno1, Naoki Yoshikawa1, Hideaki Murase1, Kazuhiko Shimakawa1, Takeshi Ta
ISSCC 2013
Session 12
Memory
A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology
P. Conenna1, A. D’Alessandro1, L. De Santis1, D. Di Cicco1, W. Di Francesco1, M.L. Gallese1, G. Gallo2, M. Incarnati1, C. Lattaro1, A. Macerola1, G. Marotta1, V. Moschiano1, D. Orlandi1, F. Paolini1, S. Perugini1, L. Pil
ISSCC 2013
Session 12
Memory
Time-Differential Sense Amplifier for Sub-80mV Bitline Voltage Embedded STT-MRAM in 40nm CMOS
Jan Otterstedt1, Othmane Bahlous1, Karl Hofmann1, Robert Allinger1, Stephan Kassenetter1, Doris Schmitt-Landsiedel2 Infineon Technologies, Neubiberg, Germany, Technical University Munich, Munich, Germany 1 2 Spin-torque-
ISSCC 2013
Session 12
Memory
A 6nW Inductive-Coupling Wake-Up Transceiver for Reducing Standby Power of Non-Contact Memory Card by 500×
Memory cards are widely used in electronic systems to expand internal storage area or are used as detachable media to carry data. Although cloud computing has recently drawn attention, data transfer consumes significant
ISSCC 2013
Session 12
Memory
40nm Embedded SG-MONOS Flash Macros for Automotive with 160MHz Random Access for Code and Endurance Over 10M Cycles for Data
markets of Flash MCUs, microcontrollers with embedded flash memory (eFlash), have been steadily growing since the middle of 1990s. Especially, in automotive, Flash MCUs have become essential to realize the complicated re
ISSCC 2013
Session 12
Memory
A 130.7mm2 2-Layer 32Gb ReRAM Memory Device in 24nm Technology
Jeffrey KoonYee Lee1, Gopinath Balakrishnan1, Gordon Yee1, Henry Zhang1, Alex Yap1, Jingwen Ouyang1, Takahiko Sasaki2, Sravanti Addepalli1, Ali Al-Shamma1, Chin-Yu Chen1, Mayank Gupta1, Greg Hilton1, Saurabh Joshi1, Acha
ISSCC 2013
Session 11
Memory
A Scalable 2.9mW 1Mb/s eTextiles Body Area Network Transceiver with Remotely Powered Sensors and Bi-Directional Data Communication
Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates 1 2 Advances in sensor design have made ambulatory health monitoring possible and have created the need for low-power communication systems to r
ISSCC 2013
Session 11
Memory
Retrodirective Transponder Array with Universal On-Sheet Reference for Wireless Mobile Sensor Networks Without Battery or Oscillator
A rotating shaft in a wheel, a motor and a turbine uses sensors to measure torque, vibration, and acceleration for better control and maintenance of a machine. Such data is currently acquired in a laboratory and utilized
ISSCC 2013
Session 11
Memory
Gb/s 3.9pJ/b Mono-Phase Pulse-Modulation Inductive-Coupling Transceiver for mm-Range Board-to-Board Communication
relaxing hardware requirements and leading to low energy consumption in the transceiver. Figure 11.6.4 shows the spectrum waveform of the receiver output. The 1.09GHz free running frequency is locked to the 1.2GHz clock
ISSCC 2013
Session 11
Memory
A 0.15mm-Thick Non-Contact Connector for MIPI Using Vertical Directional Coupler
capabilities should also be improved to achieve higher overall system performance. This paper proposes a new, small-size and high-speed non-contact interconnect between printed circuit boards (PCBs) using a vertical dire
ISSCC 2013
Session 11
Memory
Microwave Amplification with Nanomechanical Resonators
beam resonators. One such mechanical device is illustrated in Fig. 11.4.7. The fabrication relies on e-beam patterning, gas phase HF-etching, and release of the Al-beam using focused ion beam (FIB) cutting, as described
ISSCC 2013
Session 11
Memory
A Versatile Timing Microsystem Based on WaferLevel Packaged XTAL/BAW Resonators with Sub-µW RTC Mode and Programmable HF Clocks
Silvio Dalla Piazza2, Felix Staub2, Kai Zoschke3, Charles Alix Manier3, Hermann Oppermann3, James Dekker4, Tommi Suni4, Giorgio Allegato5 CSEM, Neuchatel, Switzerland, Micro Crystal, Grenchen, Switzerland, 3Fraunhofer IZ
ISSCC 2013
Session 11
Memory
Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating
Ryusuke Nebashi2, Yukihide Tsuji2, Ayuka Morioka2, Tadahiko Sugibayashi2, Sadahiko Miura2, Hiroaki Honjo2, Keizo Kinoshita1, Shoji Ikeda1, Tetsuo Endoh1, Hideo Ohno1, Takahiro Hanyu1 Tohoku University, Sendai, Japan, 2 N
ISSCC 2013
Session 11
Memory
A 3.4pJ FeRAM-Enabled D Flip-Flop in 0.13µm CMOS for Nonvolatile Processing in Digital Systems
Texas Instruments, Dallas, TX 1 2 Nonvolatile processing—continuously operating a digital circuit and retaining state through frequent power interruptions—creates new applications for portable electronics operating from
ISSCC 2012
Session 25
Memory
128Gb 3b/Cell NAND Flash Memory in 19nm Technology with 18MB/s Write Rate and 400Mb/s Toggle Mode
Nima Mokhlesi1, Cynthia Hsu1, Jason Li1, Venky Ramachandra1, Teruhiko Kamei1, Masaaki Higashitani1, Tuan Pham1, Mitsuaki Honma2, Yoshihisa Watanabe2, Kazumi Ino2, Binh Le1, Byungki Woo1, Khin Htoo1, Tai-Yuan Tseng1, Long
ISSCC 2012
Session 25
Memory
A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using LowVoltage Current-Mode Sensing Scheme with 45ns Random Read Time
mobile chips, such as energy-harvestingpowered devices and biomedical applications, require low-VDD on-chip nonvolatile memory (NVM) for low-power active-mode access and power-off data storage. However, conventional NVMs
ISSCC 2012
Session 25
Memory
An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput
Yoshikazu Katoh1, Kouhei Tanabe2, Toshihiro Nakamura2, Yoshihiko Sumimoto2, Naoki Yamada2, Nobuyuki Nakai2, Shoji Sakamoto2, Yukio Hayakawa1, Kiyotaka Tsuji1, Shinichi Yoneda1, Atsushi Himeno1, Ken-ichi Origasa2, Kazuhik
ISSCC 2012
Session 25
Memory
A 64Gb 533Mb/s DDR Interface MLC NAND Flash in Sub-20nm Technology
Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byung-Jun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang
ISSCC 2012
Session 25
Memory
Bitline-Capacitance-Cancelation Sensing Scheme with 11ns Read Latency and Maximum Read Throughput of 2.9GB/s in 65nm Embedded Flash for Automotive
Christian Peters1, Christoph Parzinger1, Christoph Roll1, Stephan Kassenetter1, Stefanie Thierold1, Doris Schmitt-Landsiedel2 Infineon, Neubiberg, Germany, 2Technical University Munich, Munich, Germany 1 The markets tren
ISSCC 2012
Session 25
Memory
Gb/s Multi-Threaded BCH Encoder and Decoder for Multi-Channel SSD Controllers
Solid-state drives (SSDs), built with many flash memory channels, is usually connected to the host through an advanced high-speed serial interface such as SATA III associated with a transfer rate of 6Gb/s [1-2]. However,
ISSCC 2012
Session 25
Memory
Over-10×-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme
This paper presents solid-state drives (SSDs) with two high reliability techniques. First, an error-prediction (EP) low-density-parity-check (LDPC) errorcorrecting code (ECC) that realizes an over 10× extended lifetime.
ISSCC 2012
Session 25
Memory
A 19nm 112.8mm2 64Gb Multi-Level Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface
T. Shimizu1, T. Sugimoto1, T. Kobayashi1, K. Inuzuka1, N. Kanagawa1, Y. Kajitani1, T. Ogawa1, J. Nakai1, K. Iwasa1, M. Kojima1, T. Suzuki1, Y. Suzuki1, S. Sakai1, T. Fujimura1, Y. Utsunomiya1, T. Hashimoto1, M. Miakashi1
ISSCC 2012
Session 2
Memory
A 7Gb/s/Link Non-Contact Memory Module for MultiDrop Bus System Using Energy-Equipartitioned Coupled Transmission Line
increases as well. Recently, the memory interface has been improved up to 20Gb/s/link [1]. Considering PCB routing area, a multi-drop bus architecture is still preferable for large memory capacity to the point-to-point c
ISSCC 2012
Session 2
Memory
An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band Simultaneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression
Morgantown, WV 3 TSMC, Hsinchu, Taiwan 1 2 The demand for higher power efficiency and bandwidth is increasing as mobile devices keep enhancing its graphic computing and media processing capabilities. Current memory inter
ISSCC 2012
Session 2
Memory
A 283.2µW 800Mb/s/pin DLL-Based Data Self-Aligner for Through-Silicon Via (TSV) Interface
Dae-Han Kwon2, Jong-Ho Kang2, Yunsaing Kim2, Young-Jung Choi2, Kunwoo Park2, Byong-Tae Chung2, Chulwoo Kim1 Korea University, Seoul, Korea Hynix Semiconductor, Icheon, Korea 1 2 The process variation among 512 DRAM sampl
ISSCC 2012
Session 2
Memory
A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth
Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Duckmin Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, Min Gu Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaehwan Kim, Yong-Jun Lee, Qi Wang, Sooho C
ISSCC 2012
Session 2
Memory
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with Input Skew Calibration and Enhanced Control Scheme
Yonggwon Jeong, Kwang-Sook Noh, Younghoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo Sun Choi, Kyungseok Oh Samsung Elec
ISSCC 2012
Session 2
Memory
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with Bank Group and ×4 Half-Page Architecture
Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yongju Kim, Youngdo Hur, Yunsaing Kim, Byongt
ISSCC 2012
Session 2
Memory
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme
Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki-Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang S
ISSCC 2012
Session 13
Memory
A 28nm 360ps-Access-Time Two-Port SRAM with a Time-Sharing Scheme to Circumvent Read Disturbs°
growth in the market for mobile information terminals such as smart phones and tablets, the performance of image processing engines (e.g., operation speed, accuracy in digital images) has improved remarkably. In these pr
ISSCC 2012
Session 13
Memory
Capacitive-Coupling Wordline Boosting with SelfInduced VCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM
embedded memory arrays used as register files and low-level caches that typically share the same supply voltage as the core [1]. The desire for wide voltage range operation to optimize power and performance dictates the
ISSCC 2012
Session 13
Memory
A 6T SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Fails That Achieves 57% Faster Read and 31% Lower Read Energy
Semiconductor Technology Academic Research Center, Yokohama, Japan 1 2 Decreasing operating margins due to random variations is a key issue for voltage scaling in SRAM technology. It is particularly severe for half-selec
ISSCC 2012
Session 13
Memory
A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active VMIN-Enhancing Assist Circuitry
reduced power consumption, which motivates the pursuit of high-performance at reduced operating voltages. Random and systematic device variations pose significant challenges to SRAM VMIN and low-voltage performance as te
ISSCC 2011
Session 14
Memory
A 28nm High-Density 6T SRAM with Optimized Peripheral-Assist Circuits for Operation Down to 0.6V
Massachusetts Institute of Technology, Cambridge, MA, Texas Instruments, Dallas, TX An increasing amount of embedded memory is used in today’s ICs and consequently the design of low-power, high-density SRAM is becoming c
ISSCC 2011
Session 14
Memory
An 8MB Level-3 Cache in 32nm SOI with ColumnSelect Aliasing
Chris Helt1, Ryan Freese1, Tommy Miles1, Anita Karegar1, Russell Schreiber2, Bryan Schneller1, John Wuu1 1 AMD, Fort Collins, CO, AMD, Austin, TX 2 High-performance multi-core processors require efficient multi-level cac
ISSCC 2011
Session 14
Memory
A 4R2W Register File for a 2.3GHz Wire-Speed POWERTM Processor with Double-Pumped Write Operation
Sherman M. Dance2, Sebastian Ehrenreich3, Bruce M. Fleischer1, Thomas W. Fox1, Kyle M. Holmes4, Junichi Mihara5, Yutaka Nakamura5, Shohji Onishi5, Robert Shearer2, Dieter Wendel6, Leland Chang1 1 IBM T. J. Watson Reseach
ISSCC 2011
Session 14
Memory
A 64Mb SRAM in 32nm High-k Metal-Gate SOI
Harold Pilo1, Igor Arsovski1, Kevin Batson1, Geordie Braceras1, John Gabric1, Robert Houle1, Steve Lamphier1, Frank Pavlik1, Adnan Seferagic1, Liang-Yu Chen2, Shang-Bin Ko2, Carl Radens2 1 IBM Systems and Technology Grou
ISSCC 2011
Session 11
Memory
A 7MB/s 64Gb 3-Bit/Cell DDR NAND Flash Memory in 20nm-Node Technology
In-Mo Kim, Bo-Geun Kim, Min-Seok Kim, Yoon-Hee Choi, Seung-Hwan Shin, Youngson Song, Joo-Yong Park, Jae-Eun Lee, Chang-Gyu Eun, Ho-Chul Lee, Hyeong-Jun Kim, Jun-Hee Lee, Jong-Young Kim, Tae-Min Kweon, Hyun-Jun Yoon, Taeh
ISSCC 2011
Session 11
Memory
A 4Mb Conductive-Bridge Resistive Memory with 2.3GB/s Read-Throughput and 216MB/s Program-Throughput
higher performance in the storage and access of data in various consumer electronic and computing devices has driven the development of nonvolatile memory (NVM) technologies. The promising candidates for future NVM such
ISSCC 2011
Session 11
Memory
A Low-Voltage 1Mb FeRAM in 0.13µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin in Scaled CMOS
Massachusetts Institute of Technology, Cambridge, MA, Texas Instruments, Dallas, TX 2 Low-power portable electronics such as implantable medical devices require low-access-energy non-volatile memory to deliver longer bat
ISSCC 2011
Session 11
Memory
An Offset-Tolerant Current-Sampling-Based Sense Amplifier for Sub-100nA-Cell-Current Nonvolatile Memory
Yu-Fan Lin1, Shang-Chi Wu1, Chia-En Huang1,2, Han-Chao Lai1,2, Ya-Chin King1, Chorng-Jung Lin1, Hung-Jen Liao2, Yu-Der Chih2, Hiroyuki Yamauchi3 National Tsing Hua University, Hsinchu, Taiwan, TSMC, Hsinchu, Taiwan, 3 Fu
ISSCC 2011
Session 11
Memory
95%-Lower-BER 43%-Lower-Power Intelligent SolidState Drive (SSD) with Asymmetric Coding and Stripe Pattern Elimination Algorithm
memory errors by 95% and reduce power consumption by 43%. Figure 11.4.1 shows the measured memory cell error in the data retention and program disturb of 4X, 3X and 2Xnm NAND flash memories. As the memory size decreases,
ISSCC 2011
Session 11
Memory
A 32Gb MLC NAND Flash Memory with Vth Margin-Expanding Schemes in 26nm CMOS
Byoung-sung You, kwang-ho Baek, Jae-ho Lee, Chang-won Yang, Misun Yun, Min-su Kim, Jong-woo Kim, Eun-seong Jang, Hyun Chung, Sang-o Lim, Bong-Seok Han, Yo-Hwan Koh Hynix Semiconductor, Icheon, Korea As the NAND flash mem