ISSCC 2017
Session 23
Memory
An 8Gb 12Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications
Cristian Chetreanu1, Stefan Dietrich1, Fabien Funfrock1, Marcos Alvarez Gonzalez1, Thomas Hein1, Eugen Huber1, Daniel Lauber1, Milena Ivanov1, Maksim Kuzmenka1, Chris Mohr2, Francisco Emiliano Munoz1, Juan Ocon Garrido1,
ISSCC 2017
Session 12
Memory
Gsearch/s 2Mb/mm2 TCAM Using Two-PhasePrecharge ML Sensing and Power-Grid PreConditioning to Reduce Ldi/dt Power-Supply Noise by 50%
Van Butler1,2, Raymond Kim3, Ramon Rodriguez1, Tom Maffitt4, Joseph J. Oler1, John Goss1, Christopher Parkinson5,6, Michael A. Ziegerhofer1, Steven Burns1 Globalfoundries, Essex Junction, VT Green Mountain Semiconductor,
ISSCC 2017
Session 12
Memory
A Low-Power and High-Performance 10nm SRAM Architecture for Mobile Applications
Johnny Yang2, Hau-Tai Hsieh2, Frank Wu2, Jung-Ping Yang2, Atul Katoch3, Arun Achyuthan3, Donald Mikan1, Bryan Sheffield1, Jonathan Chang2 TSMC Design Technology, Austin, TX TSMC Design Technology, Hsinchu, Taiwan 3 TSMC
ISSCC 2017
Session 12
Memory
A 7nm FinFET SRAM Macro Using EUV Lithography for Peripheral Repair Analysis
Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Ch
ISSCC 2017
Session 12
Memory
A 7nm 256Mb SRAM in High-K Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications
Hank Cheng1, Hidehiro Fujiwara1, Jih-Yu Lin1, Kao-Cheng Lin1, John Hung1, Robin Lee1, Hung-Jen Liao1, Jhon-Jhy Liaw2, Quincy Li2, Chih-Yung Lin2, Mu-Chi Chiang2, Shien-Yang Wu2 TSMC Design Technology, Hsinchu, Taiwan TSM
ISSCC 2017
Session 11
Memory
A 512Gb 3b/cell 64-Stacked WL 3D V-NAND Flash Memory
Doo-Hyun Kim, Daewoon Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-lo Ahn, Jiyoung Lee, Jong-hoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jonghoo
ISSCC 2017
Session 11
Memory
A 10nm 32Kb Low-Voltage Logic-Compatible Anti-Fuse One-Time-Programmable Memory with Anti-Tampering Sensing Scheme
breakdown as a programming scheme is fabricated and characterized. The antifuse OTP bitcell is composed of an NMOS as antifuse element and as a select transistor. Characterization shows that this solution is a viable tec
ISSCC 2017
Session 11
Memory
A 1Mb Embedded NOR Flash Memory with 39μW Program Power for mm-Scale High-Temperature Sensor Nodes
Jingcheng Wang1, Kaiyuan Yang1, Yen-Po Chen1, Junjie Dong1, Minchang Cho1, Gyouho Kim1, Wei-Keng Chang2, Yun-Sheng Chen2, Yu-Der Chih2, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI TSMC, Hsinchu
ISSCC 2017
Session 11
Memory
A 512Gb 3b/Cell Flash Memory on 64-Word-LineLayer BiCS Technology
Toshio Yamamura2, Hiroyuki Mizukoshi1, Shingo Zaitsu1, Minoru Yamashita1, Shunichi Toyama1, Norihiro Kamae1, Juan Lee1, Shuo Chen1, Jiawei Tao1, William Mak1, Xiaohua Zhang1, Ying Yu1, Yuko Utsunomiya2, Yosuke Kato1, Man
ISSCC 2016
Session 7
Memory
A 768Gb 3b/cell 3D-Floating-Gate NAND Flash Memory
Koichi Kawai1, Jae-Kwan Park2, Shigekazu Yamada1, Feng Pan2, Yuichi Einaga1, Ali Ghalam2, Toru Tanzawa1, Jason Guo2, Takaaki Ichikawa1, Erwin Yu2, Satoru Tamada1, Tetsuji Manabe1, Jiro Kishimoto1, Yoko Oikawa1, Yasuhiro
ISSCC 2016
Session 7
Memory
A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175°C
Takashi Hashimoto2, Hideaki Yamakoshi2, Shinichiro Abe2, Takashi Kono1, Yasuhiko Taito1, Takashi Ito1, Takashi Krafuji1, Kenji Noguchi1, Hideto Hidaka1, Tadaaki Yamauchi1 Renesas Electronics, Kodaira, Japan, Renesas Elec
ISSCC 2016
Session 7
Memory
A 128Gb 2b/cell NAND Flash Memory in 14nm Technology with tPROG=640μs and 800MB/s I/O Rate
Sung-won Yun, Min-su Kim, Jong-hoon Lee, Minseok Kim, Kangbin Lee, Taeeun Kim, Byungkyu Cho, Dooho Cho, Sangbum Yun, Jung-no Im, Hyejin Yim, Kyung-hwa Kang, Suchang Jeon, Sungkyu Jo, Yang-lo Ahn, Sung-Min Joe, Suyong Kim
ISSCC 2016
Session 7
Memory
A 256b-Wordlength ReRAM-based TCAM with 1ns Search-Time and 14× Improvement in WordLength-EnergyEfficiency-Density Product using 2.5T1R cell
Yen-Ning Chiang1, Hsiang-Jen Tsai3, Geng-Hau Yang3, Ya-Chin King1, Chrong Jung Lin1, Tien-Fu Chen3, Meng-Fan Chang1 National Tsing Hua University, Hsinchu, Taiwan, TSMC, Hsinchu, Taiwan, 3 National Chiao Tung University,
ISSCC 2016
Session 7
Memory
A Resistance-Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage-Class Memory Applications
Tzu-Hsiang Su1,3, Keng-Hao Yang3, Tien-Fu Chen3, Tien-Yen Wang1, Hsiang-Pang Li1, Matthew BrightSky4, SangBum Kim4, Hsiang-Lam Lung1, Chung Lam4 Macronix International, Hsinchu, Taiwan, National Tsing Hua University, Hsi
ISSCC 2016
Session 7
Memory
4Mb STT-MRAM-Based Cache with MemoryAccess-Aware Power Optimization and WriteVerify-Write / Read-Modify-Write Scheme
Keiichi Kushida1, Atsushi Kawasumi1, Hiroyuki Hara1, Keiko Abe1, Naoharu Shimomura1, Junichi Ito1, Shinobu Fujita1, Takashi Nakada2, Hiroshi Nakamura2 Toshiba, Kawasaki, Japan, University of Tokyo, Tokyo, Japan 1 2 Two p
ISSCC 2016
Session 7
Memory
256Gb 3b/Cell V-NAND Flash Memory with 48 Stacked WL Layers
Yong Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Jeong-Don Ihm, Doogon Kim, Young-Sun Min, Moo-Sung Kim, An-Soo Park, Jae-Ick Son, I
ISSCC 2016
Session 18
Memory
An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with Non-Contact Microbump I/O Test Scheme
Tae Yong Lee, Nohhyup Kwak, Woo Yeol Shin, Na Yeon Kim, Yunseok Hong, Kyeong Pil Kang, Dong Yoon Ka, Seong Ju Lee, Yong Sun Kim, Young Kyu Noh, Jaehoon Kim, Dong Keum Kang, Ho Uk Song, Hyeon Gon Kim, Jonghoon Oh SK hynix
ISSCC 2016
Session 18
Memory
A 1.2V 64Gb 8-Channel 256GB/s HBM DRAM with Peripheral-Base-Die Architecture and Small-Swing Technique on Heavy Load Interface
Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Yeon Ok Kim, Jae Hwan Kim, Jin Ho Kim, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jeajin Lee, Hyeon Gon Kim, Jun Hyun Chun,
ISSCC 2016
Session 18
Memory
A 1.2V 20nm 307GB/s HBM DRAM with At-Speed Wafer-Level I/O Test Scheme and Adaptive Refresh Considering Temperature Distribution
Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jae-Wook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Ki
ISSCC 2016
Session 18
Memory
A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an
Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Young-Ju Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwan
ISSCC 2016
Session 17
Memory
A Reconfigurable Dual-Port Memory with Error Detection and Correction in 28nm FDSOI
systems-on-chip and usually limits their voltage scalability, due to the major impact of process/voltage/temperature (PVT) variations at low voltages [1]. Assist techniques to extend SRAM operating voltage range improve
ISSCC 2016
Session 17
Memory
Mb/mm2 1R1W 8T SRAM Arrays Operating down to 560mV Utilizing Small-Signal Sensing with Charge-Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology
which use multiport memories to improve performance by enabling multiple simultaneous operations in the same memory bank. Conventional 2-read/write 8T dual-port SRAMs (2RW) suffer from read and write disturb issues when
ISSCC 2016
Session 17
Memory
A 10nm FinFET 128Mb SRAM with Assist
Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyuhong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, ES Jung, Ste
ISSCC 2015
Session 7
Memory
Enterprise-Grade 6× Fast Read and 5× Highly Reliable SSD with TLC NAND-Flash Memory for Big-Data Storage
techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic VTH optimization and auto data recovery reduce the NAND F
ISSCC 2015
Session 7
Memory
1GB/s 2Tb NAND Flash Multi-Chip Package with Frequency-Boosting Interface Chip and low-to-high hysteresis by implementing MN4 and MN3, respectively, to block the extra toggle.
Joon-Ho Shin, Chae-Hoon Kim, Seung-Woo Yu, Ji-Yeon Shin, Seon-Kyoo Lee, Devraj Rajagopal, Sang-Tae Kim, Kyeong-Tae Kang, Jeong-Joon Park, Yong-Jin Kwon, Min-Jae Lee, Sung-Hoon Kim, Seung-Hoon Shin, Hyung-Gon Kim, Jin-Tae
ISSCC 2015
Session 7
Memory
A 3.3ns-Access-Time 71.2μW/MHz 1Mb Embedded STT-MRAM Using Physically Eliminated Read-Disturb Scheme and Normally-Off Memory Architecture
Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita Toshiba, Kawasaki, Japan Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being devel
ISSCC 2015
Session 7
Memory
A Covalent-Bonded Cross-Coupled Current-Mode Sense Amplifier for STT-MRAM with 1T1MTJ Common Source-Line Structure Array
candidate for next-generation universal memory technology with high density, high-speed access time, and nonvolatile characteristics. Due to good scalability of the magnetic tunnel junction (MTJ) cell in sub-20nm technic
ISSCC 2015
Session 7
Memory
A 28nm Embedded SG-MONOS Flash Macro for Automotive Achieving 200MHz Read Operation and 2.0MB/s Write Throughput at Tj of 170°C
Accelerated advances in automotive technology, such as sophisticated real-time engine controls for higher fuel efficiency and advanced driver-assistance systems (ADAS), are expanding the application range of Flash MCUs,
ISSCC 2015
Session 7
Memory
A 128Gb 3b/cell V-NAND Flash Memory with 1Gb/s I/O Rate
Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, You-Se Kim, Hyun-Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jin-Ho Ryu, Sang-Won Shim, Kyung-Tae Kang, Sung-Ho Choi, Jeong-Don Ihm,
ISSCC 2015
Session 7
Memory
A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology
Kazuyoshi Muraoka1, Masaki Fujiu1, Fumihiro Kouno1, Michio Nakagawa1, Masami Masuda1, Koji Kato1, Yuri Terada1, Yuki Shimizu1, Mitsuaki Honma1, Akihiro Imamoto1, Tomoko Araya1, Hayato Konno1, Takuya Okanaga1, Tomofumi Fu
ISSCC 2014
Session 19
Memory
A 16Gb ReRAM with 200MB/s Write and 1GB/s Read in 27nm Technology
Duane Mills1, Keiichi Tsutsui4, Jahanshir Javanifard1, Kerry Tedrow1, Tomohito Tsushima2, Yoshiyuki Shibahara4, Glen Hush3 Micron, Folsom, CA, Sony, Boise, ID, 3 Micron, Boise, ID, 4 Sony, Kanagawa, Japan 1 2 Resistive R
ISSCC 2014
Session 19
Memory
Hybrid Storage of ReRAM/TLC NAND Flash with RAID-5/6 for Cloud Data Centers
RAID-5/6 is developed to meet cloud data-center requirements of reliability, speed and capacity. The storage controller enhances reliability and performance through five techniques with minimal area overhead. The first t
ISSCC 2014
Session 19
Memory
Three-Dimensional 128Gb MLC Vertical NAND FlashMemory with 24-WL Stacked Layers and 50MB/s High-Speed Programming are reprogrammed in the next program pulse. As a result, the wider programmed
with performance of 50MB/s write throughput. Ki-Tae Park, Jin-man Han, Daehan Kim, Sangwan Nam, Kihwan Choi, Min-Su Kim, Pansuk Kwak, Doosub Lee, Yoon-He Choi, Kyung-Min Kang, Myung-Hoon Choi, Dong-Hun Kwak, Hyun-wook Pa
ISSCC 2014
Session 19
Memory
Embedded 1Mb ReRAM in 28nm CMOS with 0.27-to1V Read Using Swing-Sample-and-Couple Sense Amplifier and Self-Boost-Write-Termination Scheme
Ting-Chin Yang1, Wen-Chao Shen1, Ya-Chin King1, Chorng-Jung Lin1, Ku-Feng Lin2, Yu-Der Chih2, Sreedhar Natarajan2, Jonathan Chang2 National Tsing Hua University, Hsinchu, Taiwan, 2TSMC, Hsinchu, Taiwan 1 Resistive RAM (R
ISSCC 2014
Session 19
Memory
KIOPS-Random-Read 690MB/s-Sequential-Read Universal Flash Storage Device Controller with Unified Memory Extension
Kenichi Maeda1, Toshio Fujisawa1, Junji Wadatsumi2, Daisuke Miyashita2, Shouhei Kousai2, Yasuo Unekawa2, Shinsuke Fujii2, Takuma Aoyama2, Takayuki Tamura1, Atsushi Kunimatsu1, Yukihito Oowaki1 Toshiba, Yokohama, Japan, 2
ISSCC 2014
Session 19
Memory
A 93.4mm2 64Gb MLC NAND-Flash Memory with 16nm CMOS Technology
Sunghyun Jung, Kichang Chun, Namkyeong Kim, Wanseob Lee, Taisik Shin, Hyunjong Jin, Hyunchul Cho, Sunghoon Ahn, Yonghwan Hong, Ingon Yang, Byoungyoung Kim, Pilseon Yoo, Youngdon Jung, Jinwoo Lee, Jaehyeon Shin, Taeyun Ki
ISSCC 2014
Session 19
Memory
A 128Gb MLC NAND-Flash Device Using 16nm Planar Cell
Cairong Hu1, Heonwook Kim1, Kalyan Kavalipurapu1, Eric Lee1, Ali Mohammadzadeh1, Dan Nguyen1, Vipul Patel1, Ted Pekny1, Bill Saiki1, Daesik Song1, Jeff Tsai1, Vimon Viajedor1, Luyen Vu1, Tinwai Wong1, Jung Hee Yun1, Rami
ISSCC 2014
Session 13
Memory
A 32kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS
Singapore 1 2 Voltage scaling is widely used to improve SRAM energy efficiency [1-2], particularly in mobile systems with tight power budgets. The resulting energy benefits are limited by the minimum voltage ensuring err
ISSCC 2014
Session 13
Memory
A Reconfigurable Sense Amplifier with Auto-Zero Calibration and Pre-Amplification in 28nm CMOS
High-performance SRAMs are critical elements in microprocessors and SoCs. Fast and robust bitline sensing is a key requirement in such memories. With process scaling, increased mismatch in the sense amplifier (SA) circui
ISSCC 2014
Session 13
Memory
A 28nm 400MHz 4-Parallel 1.6Gsearch/s 80Mb Ternary CAM
enable signal (MLPRE) is negated, the ML is discharged (search miss) or maintains the VDD level (match). The ML reference voltage REFVD is generated by charge sharing between REFVD and REFVS nodes, lowering to 700mV and
ISSCC 2014
Session 13
Memory
A 16nm 128Mb SRAM in High-κ Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications
Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang TSMC, Hsinchu, Taiwan FinFET technology has become a mainstream te
ISSCC 2014
Session 13
Memory
A 7ns-Access-Time 25µW/MHz 128kb SRAM for Low-Power Fast Wake-Up MCU in 65nm CMOS with 27fA/b Retention Current
Yasuhisa Takeyama1, Tsuyoshi Midorikawa1, Kenji Hashimoto2, Ichiro Wakiyama2, Shinji Miyano1, Takehiko Hojo1 Toshiba, Kawasaki, Japan, 2Toshiba Microelectronics, Kawasaki, Japan 1 Battery lifetime is the key feature in t
ISSCC 2014
Session 13
Memory
20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists
local variation in transistor characteristics, which has been deteriorating the operation margin of SRAM. This trend necessitates assist circuits for SRAM to increase the immunity against variations, and many papers in t
ISSCC 2014
Session 13
Memory
A 14nm FinFET 128Mb 6T SRAM with VMINEnhancement Techniques for Low-Power Applications
Jaeho Park, Sunghyun Park, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyuhong Kim, Jintae Kim, Youngkeun Lee, Kee Sup Kim, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi Samsung Electronics, Yon
ISSCC 2014
Session 13
Memory
A 1Gb 2GHz Embedded DRAM in 22nm Tri-Gate CMOS Technology
Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang Intel, Hillsboro, OR CMOS technology scaling continues to drive higher levels of integration in VLS
ISSCC 2013
Session 18
Memory
7GHz L1 Cache SRAMs for the 32nm zEnterpriseTM EC12 Processor
Uma Srinivasan1, Daniel Rodko1, Pradip Patel1, Thomas J. Knips1, Tobias Werner2 IBM, Poughkeepsie, NY, 2IBM, Boeblingen, Germany 1 The L1 cache for the 5.5 GHz 32nm zEnterpriseTM EC12 processor requires SRAM designs that
ISSCC 2013
Session 18
Memory
A 64Mb SRAM in 22nm SOI Technology Featuring Fine-Granularity Power Gating and Low-Energy Power-Supply-Partition Techniques for 37% Leakage Reduction
Steven M. Lamphier1, Michael M. Lee1, Frank M. Pavlik1, Sushma N. Sambatur3, Adnan Seferagic1, Richard Wu1, Mohammad I. Younus4 IBM, Essex Junction, VT, 2IBM, Rochester, MN, 3IBM, Bangalore, India, IBM, Hopewell Junction
ISSCC 2013
Session 18
Memory
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit
Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa Toshiba, Kawasaki, Japan This paper presents a dual-power-supply SRAM that reduces active and sta
ISSCC 2013
Session 18
Memory
An SRAM Using Output Prediction to Reduce BL-Switching Activity and Statistically-Gated SA for up to 1.9× Reduction in Energy/Access
Mobile applications such as tablets pack increasingly more processing capability comparable to workstations or laptops but can do little for cooling or extending the battery life in their form factors. SRAMs account for
ISSCC 2013
Session 18
Memory
A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications
Hung-Jen Liao, Quincy Li, Stanley Chang, Sreedhar Natarajan, Robin Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, George H. Chang TSMC, Hsinchu, Taiwan A 20nm high-κ metal-gate planar CMOS t