Memory

A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation

A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-CellBased Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit

A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µm2 Cell Size Using Self-Adaptive Delayed Termination and MultiCell Reference

A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips VGBL= (VMM15 × CGBL15 + VMM14 × CGBL14 + … + VMM0 × CGBL0)/(CGBL15 + CGBL14 + … + CGBL0). The voltage of GBLB (VGBLB) is the pMACV of 2bIN×1bW with 16-channel accumulation using the LSB part of a 4b-input (IN10).

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications

A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models

A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface

An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique

A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor

A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo

A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs

A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices

A 22nm 32Mb Embedded STT-MRAM with 10ns Read

A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique pairs for low input offset to reduce a random dopant fluctuation. In order to reduce an input offset, the error amplifier designs that DC gain is above 74dB with all PVT variations. The Monte-Carlo simulation shows the variation is decreased by 46.9%, comparing to conventional one.

Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation

A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology

A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate ReadDisturb-Write Issue

A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller

A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a

A 7.5Gb/s/pin LPDDR5 SDRAM with WCK Clocking and

A 512Gb 3-bit/Cell 3D Flash Memory on 128-WordlineLayer with 132MB/s Write Performance Featuring CircuitUnder-Array Technology

A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface In this work, to minimize the capacitive coupling between WLN and WLN+1, we

A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique

A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-LineLayer Technology

A 1Tb 4b/Cell 64-Stacked-WL 3D NAND Flash Memory with 12MB/s Program Throughput

A Flash Memory Controller for 15μs Ultra-Low-Latency SSD Using High-Speed 3D NAND Flash with 3μs Read Time

A 512Gb 3b/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology

A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with Improved Power Distribution and Repair Strategy

A 16Gb/s/pin 8Gb GDDR6 DRAM with Bandwidth Extension Techniques for High-Speed Applications

A 1.2V 64Gb 341GB/s HBM2 Stacked DRAM with Spiral Point-to-Point TSV Structure and Improved Bank Group Data Control

A 16Gb LPDDR4X SDRAM with an NBTI-Tolerant

A 16Gb 18Gb/s/pin GDDR6 DRAM with Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

A 5GHz 7nm L1 Cache Memory Compiler for High-Speed Computing and Mobile Applications

A 7nm FinFET SRAM Using EUV Lithography with Dual Write-Driver-Assist Circuitry for Low-Voltage Applications

A 23.6Mb/mm2 SRAM in 10nm FinFET Technology with Pulsed PMOS TVC and Stepped-WL for Low-Voltage Applications

An 8-Channel 4.5Gb 180GB/s 18ns-Row-Latency RAM for the Last Level Cache

A 1V 7.8mW 15.6Gb/s C-PHY Transceiver Using Tri-Level Signaling for Post-LPDDR4

A Time-Based Receiver with 2-tap DFE for a 12Gb/s/pin Single-Ended Transceiver of Mobile DRAM Interface in 0.8V 65nm CMOS

A 0.6V 4.266Gb/s/pin LPDDR4X Interface with AutoDQS Cleaning and Write-VWM Training for Memory Controller

A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture

An Extremely Low-Standby-Power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for Wearable Devices

A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with Sub-100μA Self-Refresh Current for IoT Applications

A 5Gb/s/pin 8Gb LPDDR4X SDRAM with PowerIsolated LVSTL and Split-Die Architecture with 2-Die ZQ Calibration Scheme