MediaTek

Abstract This work presents a single-rail, 21.04Mb/mm2 logic-bitcell 2-port SRAM in a 2nm nanosheet technology for CPU, GPU and NPU caches. The implemented xBIT cell in a 2R×1C configuration uses dual BL for balanced NMO

modulation schemes, such as 4K-QAM, and impose stringent phase-noise requirements on frequency synthesizers. In the past few years, an increasing number of frac-N PLLs with excellent jitter performance, i.e., sub-100fs,

High-speed SerDes is accompanied by high channel loss. Channel loss is usually compensated by transmitter feed-forward equalization (FFE), receiver continuous time linear equalization (CTLE), and receiver decision-feedba

Direct RF sampling reduces complexity for receiver design. However, SNDR and speed specifications of its ADCs are stringent, which makes the time-interleaved (TI) ADC attractive for the required sampling rate. There is a

*Equally-Credited Authors (ECAs) Recently, both the number of smart devices and the amount of data transfered to and from these devices have grown at unprecedented rates. To provide users with a highquality experience, w

Growing traffic in data centers imposes multiple challenges on serial link design with higher speed and stringent power requirements. Clocking is one major challenge due to the significant portion of total power that clock

applications due to their low power and small area. SNR of 60-70dB is necessary to meet the noise budget for the downlink chain in the 802.11 ac/ax standards. Comparator noise and quantization noise are typically the dom

Three major design issues that arise for high-fidelity audio decoders are: 1) DAC reference noise limiting achievable SNR [1,2]; 2) THD+N degradation at large output swing [3,4]; and 3) Distortion arising from limited amp

The successive approximation register (SAR) ADC is the most energy efficient architecture with moderate conversion rate and resolution. However, its comparator noise limits its resolution without sacrificing power effici

A high power-supply rejection ratio (PSRR) and high-linearity Class-D audio amplifier (CDA) becomes important as the CDA is directly connected to a battery supply for efficiency considerations in mobile phone application

The successive-approximation-register (SAR) architecture is well-known for its high power efficiency in medium-resolution A/D conversions. Together with time interleaving, it can challenge the regime of flash ADCs in hig

baseband ADC of an LTE-A receiver. To boost user throughput and increase network capacity, CT-DSMs will need to increase signal bandwidth (BW) while maintaining sufficient dynamic range (DR) and good power efficiency. Fo

With limited frequency allocation in the radio spectrum, spectral efficiency has always been the core development of communication systems. To accommodate the increase in demand for wireless data services, RF systems hav

Ring PLLs play an important role in mobile baseband applications. In cases where fine frequency resolution and low jitter are both needed, wideband fractional-N PLL architectures with quantization noise (Q-noise) cancell

evolution of cellular phone networks. New-generation cellular standards use wider channel bandwidth and more sophisticated modulation to obtain higher data-rates. Due to various cellular standards, chip providers are req

(RVCOs) ([oscillation frequency change %] / [VDD change %] typically lies in the range from 1 to 2 [1]), an LDO has to provide over 40dB power-supply-rejection ratio (PSRR) to maintain VCO phase noise. However, the volta

Fractional-N PLLs play an important role in both wireless and wireline circuits. Finer timing resolution is needed to reduce the quantization noise in the phase domain. In conventional designs, a phase interpolator (PI)

because of the fundamental correlation between data rate and transmit power. Furthermore, the high peak-to-average power ratio (PAPR) of the modulated signals causes a degradation in PA efficiency, since the supply volta

compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially signific

For minimizing the power consumption in portable devices, efficient DC-DC converters with a wide range of regulated voltages and currents are needed. Considering the required footprint area, cost, and chip count, integra

In modern analog front-ends, there is an increasing demand on high- performance analog-to-digital converters (ADCs), which require high sampling frequency and low-jitter sampling clock. This makes low-jitter phase-locked

J. Watson, Yorktown Heights, NY 2 For point-to-point multi-Gb/s applications in mobile devices with single antennas, low-cost, highly integrated solutions are preferred, and CMOS technology is a candidate for mm-Wave SoC

Due to their inherent anti-aliasing properties and potential for low-power design, continuous-time (CT) ∆Σ ADCs are an indispensable component in wireless communication systems such as GSM/WCDMA, since a precise sampling