ISSCC 2026
Session 13
Other
Medusa: A Quantum-Inspired 200-Variable 1016-Clause Analog k-SAT Solver
Abstract A quantum-inspired analog variable k-SAT solver supporting up to 200 variables and 1016 clauses. Enabling techniques include make/break feedback, distributed k-SAT logic, digital macro coupling, and feedback opt
ISSCC 2022
Session 24
RF & Wireless
A 110µW 2.5kb/s -103dBm-Sensitivity Dual-Chirp Modulated ULP Receiver Achieving -41dB SIR
*Equally-Credited Authors (ECAs) As the number of devices connected to the IoT has increased rapidly in recent years, stricter requirements have been placed on IoT radio receivers (RX) that can operate in an increasingly
ISSCC 2021
Session 27
Data Converters
-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC
IoT sensors are in rising demand and they often require low power, yet high precision measurements. Under constrained energy, Nyquist-rate SAR ADCs are typically used for readout as they are energy efficient and easy to
ISSCC 2021
Session 14
mm-Wave
A Fully Integrated 62-to-69GHz Crystal-Less Transceiver with 12 Channels Tuned by a Transmission-LineReferenced FLL in 0.13µm BiCMOS
The progress towards smaller Wireless Sensor Networks (WSNs) has expanded the applications for ubiquitous sensing. However, the form-factor of a WSN is typically limited by bulky off-chip components, mainly the crystal r
ISSCC 2021
Session 10
Data Converters
A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer
Emerging communication and radar applications place enormous demands on ADC performance by requiring wide BW (100MHz) and high DR (70dB). Continuous-time delta-sigma modulators (CT-DSM) [1-2] are a mainstream solution as
ISSCC 2020
Session 9
Data Converters
A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth
High-resolution, sub-MHz-bandwidth data converters are essential for audio and sensor applications and are conventionally implemented as sigma-delta (SD) converters. The dependence of SD ADCs on op-amps inherently result
ISSCC 2020
Session 3
Analog Circuits
A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection
minimum power while disturbing the oscillation as little as possible. In order to achieve subnW power consumption, there are three fundamental considerations: the loss in the crystal, the efficiency of energy injection,
ISSCC 2019
Session 28
AI / ML
A 606µW mm-Scale Bluetooth Low-Energy Transmitter Using Co-Designed 3.5×3.5mm2 Loop Antenna and Transformer-Boost Power Oscillator
Wireless communication has been a limiting factor for achieving millimeter-sized wireless sensor nodes because of the high power consumption, large antenna size and off-chip components typically required. Several mm-scal
ISSCC 2019
Session 20
Data Converters
A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC
Noise-Shaping SAR (NS-SAR) is an emerging ADC architecture that offers both high resolution and high energy efficiency. State-of-the-art NS-SAR ADCs eliminate the need for op-amps, which relaxes design complexity and tech
ISSCC 2018
Session 23
Other
A 301.7-to-331.8GHz Source with Entirely On-Chip Feedback Loop for Frequency Stabilization in 0.13μm BiCMOS
King Abdulaziz City for Science and Technology, Riyadh, Saudi Arabia, 4 STMicroelectronics, Crolles, France 1 3 The THz band has shown its unique characteristics and great potential in many applications. Harmonic oscilla
ISSCC 2018
Session 15
RF & Wireless
A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS Fractional-N FMCW Chirp Synthesizer PLL with a Continuous-Time Bandpass Delta-Sigma Time-to-Digital Converter rotation allows us to emulate the divider-ratio step size of 8/32 = 1/4. Since the phase rotation occurs ahead of the final divider stage, we perform only one phase shift per divider output cycle to retain the step size of 1/4 for the entire divider chain. A 2nd-order ΔΣ modulator controls the phase rotation for fractional-N division. Finally, on-chip chirp control logic modulates the PLL division ratio to generate the desired FMCW waveform profile.
Broadcom, Irvine, CA 1 Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-di
ISSCC 2018
Session 13
AI / ML
A 1.8Gb/s 70.6pJ/b 128×16 Link-Adaptive Near-Optimal Massive MIMO Detector in 28nm UTBB-FDSOI
Lund University, Lund, Sweden data movements using holding buffers to maximize data reuse. The data reuse is especially advantageous in our design, as it requires a relatively long 28b data bit width to support a wide ra
ISSCC 2017
Session 8
Digital Circuits
A 553F2 2-Transistor Amplifier-Based Physically Unclonable Function (PUF) with 1.67% Native Instability
Physically Unclonable Functions (PUFs) are among the most promising security primitives for low cost solutions of key storage, chip authentication, and supply chain protection. Two types of PUFs exist in literature [1-6]
ISSCC 2017
Session 4
Image Sensors
A Sub-nW 80mlx-to-1.26Mlx Self-Referencing Light-to-Digital Converter with AlGaAs Photodiode
Wearable sensors are increasingly common and continue to grow more diverse in their sensing modalities, ranging from glucose to heart rate monitoring. One compelling sensing modality for wearable sensors is cumulative li
ISSCC 2017
Session 20
Digital Circuits
A 13.8µW Binaural Dual-Microphone Digital ANSI S1.11 Filter Bank for Hearing Aids with Zero-ShortCircuit-Current Logic in 65nm CMOS
This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural tim
ISSCC 2016
Session 27
Data Converters
Area-Efficient 1GS/s 6b SAR ADC with ChargeInjection-Cell-Based DAC
To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is
ISSCC 2016
Session 12
Power Management
A Rational-Conversion-Ratio Switched-Capacitor DC-DC Converter Using Negative-Output Feedback
Switched-capacitor (SC) DC-DC converters have several advantages over inductive DC-DC converters in that they are easily integrated on-chip and can scale to desired power levels, rendering themselves promising for integr
ISSCC 2015
Session 8
Digital Circuits
Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic
Recent low-voltage design techniques have enabled dramatic improvements in miniaturization and lifetime of wireless sensor nodes [1-3]. These systems typically use a secondary battery to provide energy when the sensor is
ISSCC 2015
Session 26
Data Converters
A 1mW 71.5dB SNDR 50MS/s 13b Fully Differential Ring-Amplifier-Based SAR-Assisted Pipeline ADC
The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [1]. Consisting of two low-resolution charge-redistribution SAR ADCs coupled by a residue amplifier, a SAR-assisted pipeline ADC relax
ISSCC 2015
Session 18
Digital Processors
A 2.4mm2 130mW MMSE-Nonbinary-LDPC Iterative Detector-Decoder for 4×4 256-QAM MIMO in 65nm CMOS
The latest multiple-input multiple-output (MIMO) wireless systems have adopted iterative detection and decoding (IDD) to reduce the signal-to-noise ratio (SNR) required for a reliable transmission. An IDD system consists
ISSCC 2015
Session 14
Digital Processors
A Physically Unclonable Function with BER <10-8 for Robust Chip Authentication Using Oscillator Collapse in 40nm CMOS
Security is a key concern in today’s mobile devices and a number of hardware implementations of security primitives have been proposed, including true random number generators, differential power attack avoidance, and ch
ISSCC 2015
Session 12
Power Management
PWM Buck Converter with >80% PCE in 45µA-to-4mA Loads Using Analog-Digital Hybrid Control for Implantable Biomedical Systems
Implantable biomedical systems usually operate in energy-limited environments and exhibit large variation of power consumption ranging from constant lowpower (bio-signal sensing) to sporadic high-power (stimulation and/o
ISSCC 2014
Session 7
Image Sensors
pJ/pixel Bio-Inspired Time-Stamp-Based 2D Optic Flow Sensor for Artificial Compound Eyes
Miniaturized low-power artificial compound eyes in a small form factor and a low payload can be a promising approach to provide wide-field information for micro-air-vehicle (MAV) applications. Recently, research efforts
ISSCC 2014
Session 27
Digital Circuits
An 821MHz 7.9Gb/s 7.3pJ/b/iteration Charge-Recovery LDPC Decoder
This paper presents a 576b LDPC decoder test-chip designed using a chargerecovery logic family. The chip has been fabricated in a 65nm CMOS process and relies on 16 integrated inductors to achieve energy-efficient operat
ISSCC 2014
Session 13
Memory
A Reconfigurable Sense Amplifier with Auto-Zero Calibration and Pre-Amplification in 28nm CMOS
High-performance SRAMs are critical elements in microprocessors and SoCs. Fast and robust bitline sensing is a key requirement in such memories. With process scaling, increased mismatch in the sense amplifier (SA) circui
ISSCC 2014
Session 11
Data Converters
A 100MS/s 10.5b 2.46mW Comparator-less Pipeline ADC Using Self-Biased Ring Amplifiers
Samsung Electronics, Yongin, Korea 1 2 Pipelined ADCs require accurate amplification; however traditional OTAs limit power efficiency since they require high quiescent current for slewing. In addition, it is difficult to
ISSCC 2013
Session 27
Image Sensors
A 3.4μW CMOS Image Sensor with Embedded Feature-Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging
Distributed sensor nodes typically operate under the constraint of limited energy source, and power consumption is an important factor to extend the lifetime of sensor systems. Several low-power imagers have been reporte
ISSCC 2013
Session 24
Digital Circuits
A 1.15Gb/s Fully Parallel Nonbinary LDPC Decoder with Fine-Grained Dynamic Clock Gating
The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signalto-noise ratio (SNR). State-of-the-art channel codes including tu
ISSCC 2012
Session 8
Data Converters
A 12mW Low-Power Continuous-Time Bandpass ΔΣ Modulator with 58dB SNDR and 24MHz Bandwidth at 200MHz IF
Analog Devices, Wilmington, MA 1 A continuous-time bandpass ΔΣ modulator (CTBPDSM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in the digital backend and also decreases the comple
ISSCC 2012
Session 6
Image Sensors
A 1.36µW Adaptive CMOS Image Sensor with Reconfigurable Modes of Operation From Available Energy/Illumination for Distributed Wireless Sensor Network
For outdoor surveillance, sensitivity and dynamic range are important to deliver reliable images over widely changing illumination. However, constant monitoring with maximum awareness requires large power consumption and
ISSCC 2012
Session 27
Data Converters
A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC
In recent years, charge-redistribution SAR (Successive Approximation) ADCs have exhibited the highest conversion efficiencies for ADCs with moderate resolution and bandwidth [1-3]. For effective resolutions beyond 10b or
ISSCC 2012
Session 21
Analog Circuits
A 5.58nW 32.768kHz DLL-Assisted XO for Real-Time Clocks in Wireless Sensing Applications
There is a growing interest in ultra-low-power wireless microsystems [1]. Synchronization between different nodes in a wireless sensor network plays an important role in the overall node energy budget due to the high pow
ISSCC 2011
Session 6
Power Management
A Self-Supplied Inertial Piezoelectric Energy Harvester with Power-Management IC
Harvesting energy from ambient vibrations is a promising technology for fully autonomous wireless sensor nodes, which can give birth to new applications in biomedical, industrial, and environmental monitoring. There have
ISSCC 2011
Session 16
mm-Wave
A 60GHz Antenna-Referenced Frequency-Locked Loop in 0.13µm CMOS for Wireless Sensor Networks
Some applications of wireless sensor networks (WSN) require long-term deployments and vanishingly-small unit volumes to make them cost effective and unobtrusive. Energy- and area-efficient circuits, as well as eliminatin
ISSCC 2009
Session 3
Digital Processors
Secure AES Engine with A Local Switched-Capacitor Current Equalizer
Hardware implementations of the popular AES encryption algorithm [1,2] provide attackers with important side-channel information (delay, power consumption or EM radiation) that can be used to disclose the secret key of t
ISSCC 2008
Session 22
Other
A Charge-Injection-Based Active-Decoupling Technique for Inductive-Supply-Noise Suppression
Aggressive scaling and increasing clock frequency have exacerbated inductive (Ldi/dt) supply noise, decreasing the robustness of power delivery networks. Ldi/dt is further aggravated by commonly used power-reduction tech
ISSCC 2008
Session 22
Other
Compact In-Situ Sensors for Monitoring NegativeBias-Temperature-Instability Effect and Oxide Degradation
Semiconductor reliability is a growing issue as device critical dimensions shrink and integration levels continue to grow at a rapid pace. Aggressive oxide thickness scaling has led to large vertical electric fields in M