子分类 · Data Converters

Time-Interleaved ADC

19 篇相关 JSSC 论文

JSSC 2024第12期Data ConvertersTime-Interleaved ADCNeural Network Accelerator
A 12-GSs 12-b 4 Time-Interleaved ADC Using Input-Independent Timing Skew Calibra
本文介绍了一种12-GS/s 12位4×时间交织ADC，采用全局抖动注入技术实现输入无关的时序偏差校准。
28nm CMOS, 1.2V, 12-GS/s
JSSC 2023第1期RF & WirelessTime-Interleaved ADCEqualizer
A 141-pJb 224-Gbs PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable o
一篇关于在5纳米FinFET工艺中实现224Gb/s PAM4 ADC基SerDes接收器的论文
5nm FinFET, 224Gb/s, 1.41 pJ/b
JSSC 2021第3期Data ConvertersDelta-Sigma ADCTime-Interleaved ADC
Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator
设计并实现了一款20MHz带宽的单比特连续时间ΔΣ ADC，采用65nm CMOS工艺，采样率2.56GHz。
65nm CMOS, 1.1V, 2.56GHz采样率, 82.1dB SNDR, 11.3mW功耗
JSSC 2020第4期RF & WirelessTime-Interleaved ADCEqualizer
112-Gb-s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channel
采用10nm FinFET工艺实现的112Gb/s PAM4 ADC基SERDES接收器，支持长距离通信。
112Gb/s, -35dB Nyquist通道, 1e-6预FEC BER
JSSC 2019第3期RF & WirelessTime-Interleaved ADC
A 56-GSps 8-bit Time-Interleaved ADC
本文介绍了一种56GS/s时间交织ADC，采用多种技术提升带宽和ENOB。
28nm CMOS, 56GS/s, 5.7-b ENOB, 31.5GHz BW
JSSC 2015第6期Data ConvertersTime-Interleaved ADCPLL
A High-Linearity Digital-to-Time Converter Technique Constant-Slope Charging Jia
提出恒定斜率充电法实现高线性度数字时间转换器（DTC）。
65nm CMOS, 10 bit DAC, 19 ps to 189 ps delay, 19 fs to 185 fs resolution, 0.17% INL at 189 ps, 1.8 mW
JSSC 2014第8期Data ConvertersSAR ADCTime-Interleaved ADC
A 128 GSs Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 46
本文介绍了一种12.8 GS/s 32路分层时间交织SAR ADC，采用65 nm CMOS工艺，实现4.6 ENOB和25 GHz有效分辨率带宽。
12.8 GS/s, 4.6 ENOB, 25 GHz ERBW, 0.23 mm², 162 mW
JSSC 2014第8期Data ConvertersTime-Interleaved ADC
A n8B i t4G S s1 2 0m WC M O SA D C
采用四通道时间交织ADC及新型时序失配检测算法，实现44.4 dB SNDR和219 fJ/转换步的能效。
44.4 dB SNDR, 219 fJ/conversion-step
JSSC 2014第12期Data ConvertersTime-Interleaved ADC
A6 9 5m W2 0G S s6 bT i m e - I n t e r l e a v e dA D C With Embedded Time-to
32nm CMOS SOI工艺下实现的20GS/s 6位时间交织ADC，嵌入时间数字转换器校准时序偏差，功耗69.5mW。
20GS/s, 6bit, 30.7dB SNDR, 69.5mW, 124J/conv-step FoM
JSSC 2013第3期Data ConvertersTime-Interleaved ADCNeural Network Accelerator
A Reconfigurable 1 GSps to 250 MSps 7-bit to 9-bit Highly Time-Interleaved Counte
提出一种可重构的时间交织ADC架构，支持1GSps 7-bit至250MSps 9-bit的灵活配置。
0.13μm CMOS, 400fJ/step, 1GSps@7b/500MSps@8b/250MSps@9b
JSSC 2013第4期Data ConvertersDACTime-Interleaved ADC
A 28 GSs 446 mW Time-Interleaved ADC A c h i e v i n g5 0 9d BS N D Ra n d3d BE
一款65nm CMOS工艺下实现2.8 GS/s采样率、50.9 dB峰值SNDR的低功耗时间交错SAR ADC
2.8 GS/s, 50.9 dB SNDR, 44.6 mW@1.2V, 76fJ/conversion-step FoM
JSSC 2011第5期Data ConvertersTime-Interleaved ADCNeural Network Accelerator
A CMOS 6-Bit 16-GSs Time-Interleaved ADC Using Digital Background Calibration Te
采用65nm CMOS工艺的6位16GS/s时间交织ADC，集成数字背景校准技术。
65nm CMOS, 1.5V, 16GS/s, 30.8dB SNDR, 435mW
JSSC 2011第12期Data ConvertersSAR ADCTime-Interleaved ADC
A 480 mW 26 GSs 10b Time-Interleaved ADC With 485 dB SNDR up to Nyquist in 65 nm
本文介绍了一种65nm CMOS工艺下的64倍交织10位2.6 GS/s SAR ADC，采用分层交织结构和开环缓冲阵列。
65nm CMOS, 1.2/1.3/1.6V, 2.6 GS/s, 10b, 48.5 dB SNDR
JSSC 2010第10期Data ConvertersPipeline ADCTime-Interleaved ADC
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Tim
一种四通道时间交织ADC，采用数字校准技术，提升信号质量。
11-bit, 160-MS/s, 0.35-μm CMOS
JSSC 2009第3期RF & WirelessPipeline ADCTime-Interleaved ADC
A 48 GSs 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization Aida
设计了一款5位4.8 GS/s 4路时间交织ADC，采用0.13微米CMOS技术，用于接收器前端。
5-bit, 4.8 GS/s, 30.4 dB SNDR, 300 mW功耗, 1.2-V电源
JSSC 2009第9期Data ConvertersTime-Interleaved ADC
A1 0 15-bit 60-MSs Floating-Point ADC With Digital Gain and Offset Calibration
一种具有数字增益和偏移校准功能的15位60-MS/s浮点ADC
15-bit 60-MS/s, 80 dBFS系统噪声, 300 mW功耗
JSSC 2008第4期Data ConvertersTime-Interleaved ADC
A 135 GSs 10 b 175 mW Time-Interleaved AD Converter in 013 µm CMOS
介绍了一种16通道时间交织ADC，结合高采样率和良好能效，采用超前逻辑减少延迟。
1.35 GS/s, 7.7 ENOB, 1 GHz ERBW, 0.6 pJ/step FoM
JSSC 2007第10期Data ConvertersPipeline ADCTime-Interleaved ADC
A CMOS 15-bit 125-MSs Time-Interleaved ADC With Digital Background Calibration
一款采用数字后台校准的15位125MS/s时间交织ADC，在0.18μm CMOS工艺下实现高动态范围。
0.18μm CMOS, 1.8V, 125MS/s, 91.9dB SFDR, 69.9dB SNDR
JSSC 2006第12期Data ConvertersTime-Interleaved ADC
A 1-GSs 11-bit ADC With 55-dB SNDR 250-mW Power Realized by a High Bandwidth Sca
提出一种消除时序偏移的高带宽时间交错ADC架构，实现1GS/s 11-bit 55dB SNDR性能。
1GS/s 11-bit 55dB SNDR 250mW 3.5mm²