ISSCC 2026
Session 8
Wireline I/O
A 1.59pJ/b 112Gb/s PAM-4 and 1.06pJ/b 168Gb/s PAM-8 Resistor-Less 7-Bit SST DAC-Based Transmitter with 8-Tap FFE in 28nm CMOS
Abstract A resistor-less 7b SST DAC-based TX with 8-tap FFE and 3 types of segments is presented to achieve low parasitic capacitance, compact area, and scaling friendliness. To reduce intersymbol-interference jitter at
ISSCC 2026
Session 24
Sensors
A 144mW 161Mpixels/s Tensor Display Processor for 3D Virtual Reality
Abstract This work presents a 3D display processor that converts the focal stack to tensor display. Algorithm-architecture co-optimization is applied to reduce the computational complexity and hardware complexity. It ach
ISSCC 2025
Session 2
Digital Processors
A 210fps Image Signal Processor for 4K Ultra HD True Video Super Resolution
Google, Mountain View, CA 1 2 Video super-resolution (VSR) aims to convert low-resolution (LR) videos to high-resolution (HR) videos with high image quality [1]. It can be used for various video applications, such as str
ISSCC 2025
Session 17
Hardware Security
A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation
Secure data processing has become critical to privacy-preserving in the data-driven AI era. Multi-party computation (MPC) enables computations among multiple parties (users) in a collaborative way while preserving data p
ISSCC 2025
Session 15
AI / ML
A 3.9mW 200words/min Neural Signal Processor in Speech Decoding for Brain-Machine Interface
Brain-machine interfaces (BMIs) are a promising technology that can be applied to AR/VR interfaces, neural prostheses, and machine control. Figure 15.1.1 shows BMI systems based on the source of decoded neural activities
ISSCC 2022
Session 33
Digital Processors
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction
Epilepsy is a common neurodegenerative disease that affects more than 50 million people worldwide. Closed-loop neuromodulation is a promising solution to epileptic seizure control through an implantable device that deliv
ISSCC 2021
Session 4
Digital Processors
A 91mW 90fps Super-Resolution Processor for Full HD Images
Super resolution is the process of reconstructing a high-resolution (HR) image from a low-resolution (LR) one. Super-resolution technology enables high-resolution video streaming, image zoom-in, and far object recognitio
ISSCC 2021
Session 29
Digital Circuits
A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration
A compact, low-power, low-jitter clock system supporting multiple output frequencies is required in many applications. Using several PLLs to generate multiple frequencies consumes large power and chip area [1]. Alternati
ISSCC 2020
Session 25
Digital Circuits
A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique are generated from the reference frequency, to perform a frequency-shaping SSPD, the associated switch size needs to be minimized to avoid additional spurs at the output.
These PLLs exhibit features like small area, large tuning range, and multiple output phases. However, their jitter performance is worse than that in LC-oscillator-based PLLs. Although a wider PLL bandwidth can reduce the
ISSCC 2020
Session 21
Digital Processors
A 1.5µJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots
Autonomous micro robots have been deployed for various applications, ranging from unmanned package delivery to smart aerial surveillance. These robots possess intelligence for perception, make decisions based on the coll
ISSCC 2018
Session 13
AI / ML
A 232-to-1996KS/s Robust Compressive-Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring
Compressive sensing (CS) techniques enable new reduced-complexity designs for sensor nodes and help reduce overall transmission power in wireless sensor network [1-2]. Prior CS reconstruction chip designs have been descr
ISSCC 2017
Session 6
Wireline I/O
A 56Gb/s PAM-4/NRZ Transceiver in 40nm CMOS
Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/dese
ISSCC 2017
Session 14
Digital Processors
A 135mW Fully Integrated Data Processor for Next-Generation Sequencing
National Chiao Tung University, Hsinchu, Taiwan 1 2 DNA sequencing is the process of determining the precise order of nucleotides (A, C, G, T) within a DNA molecule and is now indispensable for genetics and medical resea
ISSCC 2016
Session 27
Data Converters
A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration
Recent radio architectures, such as WiGig and 5G, require ADCs with bandwidth beyond 1GHz and ENOB of 6-to-8b while retaining excellent power efficiency for long battery life. Therefore, many time-interleaved SAR ADCs ar
ISSCC 2016
Session 19
Digital Circuits
A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation
Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring oscillator are integrated togeth
ISSCC 2015
Session 5
Analog Circuits
A 2-Channel -83.2dB Crosstalk 0.061mm2 CCIA with an Orthogonal Frequency Chopping Technique
Area-efficient low-noise instrumentation amplifiers (IAs) are required in various multi-channel sensing and monitoring applications. These IAs must be designed to achieve low noise and low power, good noise efficiency fa
ISSCC 2014
Session 21
Clocking & PLLs
A 2.3GHz Fractional-N Dividerless Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise
Recently, dividerless PLL architectures, including sub-sampling PLLs [1] and injection-locked PLLs [2], have been reported to achieve superior phase noise with respect to conventional PLL architectures. However, these di
ISSCC 2014
Session 11
Data Converters
A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS
Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong battery life in these applications
ISSCC 2012
Session 28
Power Management
A 1.0TOPS/W 36-Core Neocortical Computing Processor with 2.3Tb/s Kautz NoC for Universal Visual Recognition
Unlike human brains, where various kinds of visual recognition tasks are carried out with homogeneous neocortical circuits and a unified working mechanism, existing visual recognition processors [1-4] rely on multiple al
ISSCC 2012
Session 15
mm-Wave
A 1V 19.3dBm 79GHz Power Amplifier in 65nm CMOS
For a highly integrated wireless system including on-chip antennas, high-outputpower power amplifiers (PA) are required to cover the desired transmission range. In order to achieve the output power level, power-combining
ISSCC 2012
Session 14
Digital Circuits
A 6.7MHz-to-1.24GHz 0.0318mm2 Fast-Locking All-Digital DLL in 90nm CMOS
synchronization in high performance digital systems. The design of analog DLLs has become a challenge due to the trends associated with CMOS scaling, namely, high leakage current, low supply voltage, etc. Consequently, m
ISSCC 2011
Session 9
Wireless
An 87GHz QPSK Transceiver with Costas-Loop Carrier Recovery in 65nm CMOS
Modern high-speed wireless data links such as 60GHz RF and point-to-point communications activate research on Gb/s transceivers for V-band (50 to 75GHz) and W-band (75 to 110GHz). Conventional approaches in SiGe or III-V
ISSCC 2011
Session 8
Wireline I/O
A 40Gb/s TX and RX Chip Set in 65nm CMOS
Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth an
ISSCC 2011
Session 25
Wireline I/O
A 20Gb/s Digitally Adaptive Equalizer/DFE with Blind Sampling
As data rates increase, the backplane communication systems suffer from serious inter-symbol interference (ISI). Due to different channel lengths, loss, and environment variations, an adaptive equalizer is an attractive
ISSCC 2011
Session 20
Wireline I/O
A 6Gb/s Receiver with 32.7dB Adaptive DFE-IIR Equalization
To ensure the signal integrity over a lossy channel, an analog equalizer and/or a decision-feedback equalizer (DFE) [2-6] are widely adopted in high-speed data transmission. An adaptive analog equalizer or adaptive DFE i
ISSCC 2010
Session 20
RF & Wireless
A 2×25Gb/s Deserializer with 2:5 DMUX for 100Gb/s Ethernet Applications
The ever growing bandwidth requirement for novel server technologies including multi-core processing, virtualization, and networked storage leads to multichannel Internet connectivity such as 100GbE. Among the proposed s
ISSCC 2010
Session 16
Data Converters
A 10b 100MS/s 4.5mW Pipelined ADC with a Time Sharing Technique
For the applications requiring medium-to-high resolution ADCs, the pipelined architecture is considered to be the most optimal structure in terms of power consumption and area. With range overlap and redundant bit at eac
ISSCC 2010
Session 11
mm-Wave
A Fully Integrated 77GHz FMCW Radar System in 65nm CMOS
Millimeter-wave anti-collision radars have been widely investigated in advanced CMOS technologies recently. This paper presents a fully integrated 77GHz FMCW radar system in 65nm CMOS. The FMCW radar transmits a continuo
ISSCC 2009
Session 5
Wireline I/O
Subharmonically Injection-Locked PLLs for UltraLow-Noise Clock Generation
In this paper, complete analysis and validation of subharmonic injection locking that can substantially reduce the PLL phase noise at negligible cost is presented. Two 20GHz PLLs based on this technique demonstrate 149 a
ISSCC 2009
Session 23
Clocking & PLLs
A Leakage-Suppression Technique for Phase-Locked Systems in 65nm CMOS
In nanoscale CMOS processes, the leakage current [1,2] is becoming one of the important issues to cope with for high-performance analog and mixed-signal integrated circuits. For digital circuits, the leakage current resu
ISSCC 2009
Session 16
mm-Wave
A 128.24-to-137.00GHz Injection-Locked Frequency Divider in 65nm CMOS
Owing to the nanoscale CMOS technology, mm-wave circuits have been recently attracting a lot of attention for communication, sensing and imaging systems. Several mm-wave components with operation frequencies around or mo
ISSCC 2009
Session 16
mm-Wave
A 43.7mW 96GHz PLL in 65nm CMOS
Advances in nanoscale CMOS technology have made it feasible to implement W-Band circuits in CMOS. Recently, CMOS implementation of high-frequency circuits for applications such as 77GHz anti-collision systems, 94GHz imag
ISSCC 2008
Session 5
Wireline I/O
A 20Gb/s Duobinary Transceiver in 90nm CMOS
The ever growing volume of backplane communications pushes the data rate toward 20Gb/s for the next-generation transceivers. Over the years, chip designers have been seeking different data formats to overcome the loss of
ISSCC 2008
Session 5
Wireline I/O
A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR
Modern broadband communication systems require high-speed receivers to process serial data at tens of gigabits per second. As the data rate reaches 40Gb/s, skin-effect and dielectric loss in the transmission medium cause
ISSCC 2008
Session 28
Digital Circuits
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation
A conventional DLL employs a phase detector (PD), a charge pump, and a loop filter to compare and adjust the phase difference between the reference clock and the delayed clock. Ideally, when the DLL is locked, the delay
ISSCC 2008
Session 25
Wireline I/O
mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology
The frequency divider (FD) [1,2] is one of the key components in very-high-frequency (VHF) PLLs. Conventionally, injection-locked frequency divider (ILFD) [3], Miller frequency divider [4], and CML static divider are wid
ISSCC 2008
Session 24
Analog Circuits
A 1V 16.9ppm/°C 250nA Switched-Capacitor CMOS Voltage Reference
circuits like analog-to-digital converters, voltage regulators, DRAMs, flash memories and other communication devices. The demands for smaller area, lower power consumption, and lower sensitivity to changes in supply vol
ISSCC 2008
Session 11
Wireline I/O
A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells
PON is one of the promising solutions for the last-mile communication systems. In PONs, the fast-locked CDR circuit must lock within tens of bit times once the data packets arrive. The socalled burst-mode CDR (BMCDR) cir