ISSCC 2016
Session 22
RF & Wireless
A 141µW Sensor SoC on OLED/OPD Substrate for SpO2/ExG Monitoring Sticker
applications for broader light emission and low fabrication cost. In addition, Organic Photo Detector (OPD) and OLED can be fabricated on the same substrate with the same process and the OLED film itself can be used for
ISSCC 2016
Session 22
RF & Wireless
A 176-Channel 0.5cm3 0.7g Wireless Implant for Motor Function Recovery after Spinal Cord Injury
Brian Kim, Kuanfu Chen, Parag Gad, V. Reggie Edgerton, Wentai Liu University of California, Los Angeles, CA Epidural spinal stimulation has shown effectiveness in recovering the motor function of spinal cord transected r
ISSCC 2016
Session 20
RF & Wireless
A 1.92mW Filtering Transimpedance Amplifier for RF Current Passive Mixers
Nowadays, current passive mixers represent the state of the art for signal downconversion in wireless receivers. In such kind of structures, noise, distortions and losses are strictly correlated to the performance of the
ISSCC 2016
Session 20
RF & Wireless
A Dual-Frequency 0.7-to-1GHz Balance Network for Electrical Balance Duplexers
seeks to address several key challenges of 4G and 5G mobile systems [1]. The basic principle is shown in Fig. 20.8.1. Duplexer isolation is achieved when the signals in paths 1 and 2 cancel and prevent the TX signal from
ISSCC 2016
Session 20
RF & Wireless
An RF-PA Supply Modulator Achieving 83% Efficiency and -136dBm/Hz Noise for LTE-40MHz and GSM 35dBm Applications
constant supply voltage, has raised interest in enhancing the overall SM-PA efficiency. In the average-powertracking (APT) method, a buck converter simply generates stair-case voltages for a PA according to its required
ISSCC 2016
Session 20
RF & Wireless
A 28GHz Efficient Linear Power Amplifier for 5G Phased Arrays in 28nm Bulk CMOS
driving fifthgeneration (5G) wireless standardization towards the deployment of gigabit-per-second mm-Wave technology by 2020. Paving the road to 5G, 200m coverage in non-line-of-sight (NLOS) urban cells was demonstrated
ISSCC 2016
Session 20
RF & Wireless
A 300GHz Wirelessly Locked 2×3 Array Radiating 5.4dBm with 5.1% DC-to-RF Efficiency in 65nm CMOS
CMOS technology innovations over the last decades opened doors to the possibility of designing fully integrated systems in CMOS at THz frequencies. Small antenna sizes at THz frequencies make CMOS and silicon attractive
ISSCC 2016
Session 20
RF & Wireless
An 86-to-94.3GHz Transmitter with 15.3dBm Output Power and 9.6% Efficiency in 65nm CMOS
Southeast University, Nanjing, China to the TA high gain, the detection inaccuracy of Δt due to the circuit mismatch in PD and CP2 becomes negligibly small. VCCP is designed as a voltage-controlled current source as show
ISSCC 2016
Session 20
RF & Wireless
A Frequency-Reconfigurable mm-Wave Power Amplifier with Active-Impedance Synthesis in an Asymmetrical Non-Isolated Combiner
A frequency-agile mm-Wave power amplifier capable of reconfiguring itself to operate near-optimally over a wide range of tunable frequencies, yet producing output power >22dBm with PAE>20%, is useful for a wide range of
ISSCC 2016
Session 20
RF & Wireless
A 68.1-to-96.4GHz Variable-Gain Low-Noise Amplifier in 28nm CMOS
To allow a maximum theoretical data-rate of 25Gb/s over a 1km distance using 64QAM, an E-Band system should feature a 20dBm-output-power TX and an RX with 10dB maximum noise figure (NF) over two bands of 5GHz from 71 to
ISSCC 2016
Session 20
RF & Wireless
A 300GHz 40nm CMOS Transmitter with 32-QAM 17.5Gb/s/ch Capability over 6 Channels
Shinsuke Hara2, Akifumi Kasamatsu2, Koichi Mizuno3, Kazuaki Takahashi3, Takeshi Yoshida1, Minoru Fujishima1 Hiroshima University, Hiroshima, Japan, National Institute of Information and Communications Technology, Koganei
ISSCC 2016
Session 2
RF & Wireless
A 2GHz 244fs-Resolution 1.2ps-Peak-INL EdgeInterpolator-Based Digital-to-Time Converter in 28nm CMOS
Universität München, Munich, Germany 1 4 Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2
ISSCC 2016
Session 2
RF & Wireless
A Mixed-Mode Injection Frequency-Locked Loop for Self-Calibration of Injection Locking Range and Phase Noise in 0.13μm CMOS
Virginia Tech, Blacksburg, VA Injection-locked oscillators (ILOs) are widely used to realize low-noise carrier sources, particularly at mm-Waves by leveraging harmonic injection, but only within a narrow locking range (Δ
ISSCC 2016
Session 2
RF & Wireless
A 0.003mm2 1.7-to-3.5GHz Dual-Mode TimeInterleaved Ring-VCO Achieving 90-to-150kHz 1/f3 Phase-Noise Corner
Instituto Superior Tecnico, Lisbon, Portugal 1 3 Ring-VCOs (RVCOs) [1] have been avoided for over a decade for highperformance RF systems due to their much lower FOM (<165dB [2]) than that of their LC counterparts from l
ISSCC 2016
Session 2
RF & Wireless
A 190.5GHz Mode-Switching VCO with 20.7% Continuous Tuning Range and Maximum Power of -2.1dBm in 0.13μm BiCMOS
Wideband mm-Wave and terahertz (THz) applications, including high data-rate communications, high-resolution radar and spectroscopy, require wideband signal sources. Nevertheless, low quality factor of varactors and lossy
ISSCC 2016
Session 2
RF & Wireless
A Complementary VCO for IoE that Achieves a 195dBc/Hz FOM and Flicker Noise Corner of 200kHz
An LC oscillator can achieve near optimal performance if the common-mode of the circuit is designed to resonate at twice the oscillation frequency [1-3]. Common-mode resonance can be accomplished with an explicit tail in
ISSCC 2016
Session 2
RF & Wireless
A 2-to-16GHz BiCMOS ΔΣ Fractional-N PLL Synthesizer with Integrated VCOs and Frequency Doubler for Wireless Backhaul Applications
STMicroelectronics, Catania, Italy The flourishing of ubiquitous wireless communication networks has pushed the development and deployment of complex RF telecom systems. Concurrently, the IC industry has been making an e
ISSCC 2016
Session 2
RF & Wireless
A 4.2μs-Settling-Time 3rd-Order 2.1GHz PhaseNoise-Rejection PLL Using a Cascaded TimeAmplified Clock-Skew Sub-Sampling DLL
tuning range compared with LC-VCO-based PLLs. However, they typically have higher jitter and larger frequency drift due to high sensitivity to PVT variations. Several PLL architectures were proposed to reject the phase n
ISSCC 2016
Session 2
RF & Wireless
A Scalable 28GHz Coupled-PLL in 65nm CMOS with Single-Wire Synchronization for LargeScale 5G mm-Wave Arrays
Demonstrations of mm-Wave arrays with >50 elements in silicon has led to an interest in large-scale mm-Wave MIMO arrays for 5G networks, which promise substantial improvements in network capacity [1,2]. Practical conside
ISSCC 2016
Session 2
RF & Wireless
An Integrated 0.56THz Frequency Synthesizer with 21GHz Locking Range and -74dBc/Hz Phase Noise at 1MHz Offset in 65nm CMOS
Richard Al Hadi1, Yanghyo Kim1,2, Adrian Tang1,2, Theodore Reck2, Huan-Neng Chen3, Chewnpu Jou3, Fu-Lung Hsueh3, Mau-Chung Frank Chang1,4 University of California, Los Angeles, CA, Jet Propulsion Laboratory, Pasadena, CA
ISSCC 2015
Session 25
RF & Wireless
A ±3ppm 1.1mW FBAR Frequency Reference with 750MHz Output and 750mV Supply
Multiple emerging wireless applications (body-worn devices and IoT, for example) will demand previously impossible thin-film form factors and low system cost. One key enabling technology for this paradigm is a new class
ISSCC 2015
Session 25
RF & Wireless
A 2.4GHz VCO with FOM of 190dBc/Hz at 10kHz-to2MHz Offset Frequencies in 0.13μm CMOS Using an ISF Manipulation Technique
For the last few decades, phase-noise (PN) improvement of VCOs has been an intriguing problem and remains as one of the challenges in transceiver design. PN in CMOS VCOs, especially close-in PN, greatly suffers from flic
ISSCC 2015
Session 25
RF & Wireless
A 2.4GHz 4mW Inductorless RF Synthesizer
Recent developments in RF receiver design have eliminated all on-chip inductors except for that used in the local oscillator. This paper addresses this “last inductor” problem and proposes an integer-N synthesizer archit
ISSCC 2015
Session 25
RF & Wireless
A 70.5-to-85.5GHz 65nm Phase-Locked Loop with Passive Scaling of Loop Filter
(PLLs) are required to have wide a frequency tuning range from 71 to 86GHz and low phase noise of -90dBc/Hz @1MHz [1], which are still very challenging even with aggressive CMOS scaling [2]. Another issue associated with
ISSCC 2015
Session 25
RF & Wireless
A 320GHz Phase-Locked Transmitter with 3.3mW Radiated Power and 22.5dBm EIRP for Heterodyne THz Imaging Systems
STMicroelectronics, Crolles, France 1 2 Non-ionizing terahertz imaging using solid-state integrated electronics has been gaining increasing attention over the past few years. However, there are currently several factors
ISSCC 2015
Session 25
RF & Wireless
A 1/f Noise Upconversion Reduction Technique Applied to Class-D and Class-F Oscillators
The 1/f (flicker) noise upconversion degrades the close-in spectrum of CMOS RF oscillators. The resulting 1/f3 phase noise (PN) can be an issue in PLLs with a loop bandwidth of <1MHz, which practically implies all cellul
ISSCC 2015
Session 25
RF & Wireless
A VCO with Implicit Common-Mode Resonance
CMOS VCO performance metrics have not improved significantly over the last decade. Indeed, the best VCO Figure of Merit (FOM) currently reported was published by Hegazi back in 2001 [1]. That topology, shown in Fig. 25.3
ISSCC 2015
Session 25
RF & Wireless
A 2.2GHz -242dB-FOM 4.2mW ADC-PLL Using Digital Sub-Sampling Architecture
loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequenc
ISSCC 2015
Session 25
RF & Wireless
A Highly-Digital Frequency Synthesizer Using RingOscillator Frequency-to-Digital Conversion and Noise Cancellation
Digital fractional-N PLLs are increasingly used in place of analog fractional-N PLLs as frequency synthesizers in wireless applications, because they avoid large analog loop filters and can tolerate device leakage and lo
ISSCC 2015
Session 13
RF & Wireless
A 5.8GHz RF-Powered Transceiver with a 113μW 32-QAM Transmitter Employing the IF-based Quadrature Backscattering Technique
network (WSN) application would deeply exacerbate the spectral congestion issue, RF-powered sensor nodes [1,2] still support only low spectral-efficiency modulation such as OOK. State-of-the-art standard-compliant RF tra
ISSCC 2015
Session 13
RF & Wireless
A +10dBm 2.4GHz Transmitter with sub-400pW Leakage and 43.7% System Efficiency
Extreme energy constraints inherent in many exciting new wireless sensing applications (such as [1-3]) virtually dictate that such systems operate with extremely low duty cycles, harvesting and storing energy over long p
ISSCC 2015
Session 13
RF & Wireless
A 600μW Bluetooth Low-Energy Front-End Receiver in 0.13μm CMOS Technology
*Now at Qualcomm, San Diego, CA One of the main goals for the next generation of radios for wireless sensor and body-area networks (WSN and WBAN) is a sub-mW receiver (RX) compliant with energy-harvested supplies. In thi
ISSCC 2015
Session 13
RF & Wireless
A -97dBm-Sensitivity Interferer-Resilient 2.4GHz Wake-Up Receiver Using Dual-IF Multi-N-Path Architecture in 65nm CMOS
University of Lille, Lille, France 1 3 Wake-up receivers are considered as practical solutions to enable ultra-lowpower (ULP) wireless sensor nodes (WSN) in a dense environment. A low data-rate (<~50kb/s) wake-up receive
ISSCC 2015
Session 13
RF & Wireless
A 6.3mW BLE Transceiver Embedded RX ImageRejection Filter and TX Harmonic-Suppression Filter Reusing On-Chip Matching Network
Kenichi Shibata2, Kenji Toyota2, Tatsuhito Saitou3, Hisayasu Sato1, Koichi Yahagi2, Yoshihiro Hayashi4 Renesas Electronics, Itami, Japan, 2Renesas Electronics, Kawasaki, Japan, Renesas System Design, Kawasaki, Japan, 4 R
ISSCC 2015
Session 13
RF & Wireless
A 10mW Bluetooth Low-Energy Transceiver with On-Chip Matching
Rahul Todi, William Aartsen, Wim Kruiskamp, Johan Haanstra, Enno Opbroek, Søren Rievers, Peter Seesink, Harrie Woering, Chris Smit Dialog Semiconductor, 's-Hertogenbosch, The Netherlands Wireless sensor nodes present a d
ISSCC 2015
Session 13
RF & Wireless
A 3.7mW-RX 4.4mW-TX Fully Integrated Bluetooth Low-Energy/IEEE802.15.4/Proprietary SoC with an ADPLL-Based Fast Frequency Offset Compensation in 40nm CMOS
Ao Ba1, Benjamin Busze1, Ming Ding1, Pieter Harpe2, Gert-Jan van Schaik1, Georgios Selimis1, Hans Giesen1, Jordy Gloudemans1, Adnane Sbai1, Li Huang1, Hiromu Kato3, Guido Dolmans1, Kathleen Philips1, Harmke de Groot1 Hol
ISSCC 2015
Session 13
RF & Wireless
A 227pJ/b -83dBm 2.4GHz Multi-Channel OOK Receiver Adopting Receiver-Based FLL
The OOK demodulator and symbol timing-recovery circuits convert the ED output into final digital bit streams. In Fig. 13.1.2, for the incoming OOK signal, the initial tuning for the VCO frequency is done by the AFC. The
ISSCC 2014
Session 3
RF & Wireless
An RF-to-BB Current-Reuse Wideband Receiver with Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF
UMTEC, Macao, China, 3 Instituto Superior Tecnico, Lisbon, Portugal 1 2 The latest passive-mixer-first wideband receiver (RX) [1] has managed to squeeze the power (10 to 12mW) via resonant multi-phase LO and current-reus
ISSCC 2014
Session 3
RF & Wireless
A Fully Integrated Highly Reconfigurable DiscreteTime Super-Heterodyne Receiver
Since the invention of radio, superheterodyne has been the architecture of choice for receivers (RX). Thanks to its high intermediate-frequency (IF), the problems related to flicker noise, time-varying dc offsets, in-ban
ISSCC 2014
Session 3
RF & Wireless
A Noise-Cancelling Receiver with Enhanced Resilience to Harmonic Blockers
By employing two passive-mixer-based downconversion paths, the frequencytranslational noise-cancelling receiver (FTNC-RX) achieves a low noise figure and can tolerate most out-of-band blockers up to 0dBm with little perf
ISSCC 2014
Session 3
RF & Wireless
A 1.0-to-2.5GHz Beamforming Receiver with Constant-Gm Vector Modulator Consuming < 9mW per Antenna Element in 65nm CMOS
Frank E. van Vliet1,2 University of Twente, Enschede, The Netherlands, TNO Science and Industry, The Hague, The Netherlands The inverter transconductor in Fig. 3.5.3 is self-biased, and consists of standardVt transistors
ISSCC 2014
Session 3
RF & Wireless
A 1.95GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier with Envelope/Phase Generator and Timing Aligner for WCDMA and LTE
Yoichi Kawano1, Noriaki Shirai2, Hideki Kano2, Masahiro Kudo2, Tomotoshi Murakami2, Tetsuro Tamura2, Shigeaki Kawai2, Shinji Yamaura2, Kazuo Suto2, Hiroshi Yamazaki1, Toshihiko Mori1 Fujitsu Laboratories, Kawasaki, Japan
ISSCC 2014
Session 3
RF & Wireless
Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier
efficiency and achieve a long battery life. Therefore, both the peak efficiency and the efficiency loss due to antenna impedance mismatch or power back-off are highly critical design issues. In particular, the challenge
ISSCC 2013
Session 5
RF & Wireless
A 200mW 100MHz-to-4GHz 11th-Order Complex Analog Memory Polynomial Predistorter for Wireless Infrastructure RF Amplifiers Frederic Roger
base stations (macro-BTS) with lightweight and easy to deploy small cells calls for inexpensive and efficient Power Amplifier (PA) linearizers. Current macroBTSs relying on Digital Predistortion Techniques (DPD) are too
ISSCC 2013
Session 5
RF & Wireless
A New TX Leakage-Suppression Technique for an RFID Receiver Using a Dead-Zone Amplifier Then, IB, (W/L)13, and VLKG, but is not dependent on Vt.
continuous wave (CW) to provide energy to the tag while the RX receives data from it. Due to the simultaneous operation of the RX and TX, large TX leakage is the main issue in securing RX sensitivity. Although external i
ISSCC 2013
Session 5
RF & Wireless
A 1.8GHz Linear CMOS Power Amplifier with Supply-Path Switching Scheme for WCDMA/LTE Applications
Low-cost CMOS PAs for mobile terminals have been a focus of attention in recent years. Self-contained, linear CMOS PAs are particularly attractive for smooth replacement of conventional compound semiconductor PA products
ISSCC 2013
Session 5
RF & Wireless
A 30.3dBm 1.9GHz-Bandwidth 2×4-Array Stacked 5.3GHz CMOS Power Amplifier
RF power amplifiers (PA) implemented in a scaled CMOS technology typically have a low maximum output power because they operate from a low supply voltage. This paper proposes an array RF PA able to deliver a large output
ISSCC 2013
Session 5
RF & Wireless
A Phase-Noise and Spur Filtering Technique Using Reciprocal-Mixing Cancellation
Recent passive-mixer-based architectures, such as [1], have shown that blockers as large as 0dBm can be tolerated without excessive gain compression. However, even in a perfectly linear receiver, reciprocal mixing of the
ISSCC 2013
Session 5
RF & Wireless
Simultaneous Spatial and Frequency-Domain Filtering at the Antenna Inputs Achieving up to +10dBm Out-of-Band/Beam P1dB
Multi-antenna transceivers with beam-forming are recently gaining interest for low GHz frequencies (<6GHz) [1-4]. In the antenna beam, (phase-shifted) signals from multiple antennas add constructively, improving SNR, whi
ISSCC 2013
Session 5
RF & Wireless
SAW-Less Analog Front-End Receivers for TDD and FDD either of the two inputs is low. The divider gives a quadrature 25% duty-cycle clock with -174dBc/Hz phase noise at 20MHz offset for 6mA of current consumption (simulated from extracted layout).
*Now at the University of Toronto, Toronto, ON, Canada 2 In cellular receivers, out-of-band blockers are generally managed by surfaceacoustic-wave (SAW) filters between the antenna and the low-noise amplifier (LNA). For