子分类 · Memory

Emerging Memory

37 篇相关 JSSC 论文

JSSC 2025第1期MemoryEmerging Memory
An Edge Accelerator With 5 MB of 0256 pJ bit Embedded RRAM and a Localization S
一款集成5MB RRAM的边缘加速器，具备低功耗和高性能特性。
0256 pJ/bit, 5MB RRAM
JSSC 2025第5期MemoryEmerging Memory
A Fully Row Column Parallel MRAM in Memory Computing Macro With
一篇关于全行列并行MRAM内存计算宏的IEEE JSSC论文
无
JSSC 2024第1期MemorySRAMEmerging Memory
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking Ashwin
提出一种异构RRAM内存计算和SRAM近内存计算的SoC，用于融合帧和事件视觉处理。
40nm TSMC ULP工艺
JSSC 2024第1期MemoryEmerging MemoryNeural Network Accelerator
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices
提出一种基于STT-MRAM的8位精度近存计算宏，采用系统-电路协同设计解决能效和延迟问题。
22nm STT-MRAM, 436GB/s读取带宽, 20ns计算延迟, 53.6-190.2 TOPS/W能效
JSSC 2024第2期Data ConvertersEmerging MemoryNeural Network Accelerator
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip Junjie Wang , Teng Zhang, Shuang Liu , Yihe Liu, Yuancong Wu
设计并实现了一种基于180nm CMOS技术的1Mb RRAM存内计算芯片，采用时间分复用电路和稀疏感知技术，免除了DAC和ADC需求。
180nm CMOS, 13.32 Mb/mm2 (22nm节点归一化), 17.36 TOPS/W (INT4)
JSSC 2024第4期Power ManagementEmerging Memory
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 ◦C Takahiro Shimoi , Ken Matsubara , Tomoya Saito, Tomoya Ogawa
22纳米32Mb嵌入式STT-MRAM宏，实现59ns随机读取和74%写入能耗降低。
22nm CMOS, 59ns随机读取, 7.4MB/s写入吞吐量
JSSC 2024第7期MemoryEmerging MemoryCIM
A 65-nm RRAM Compute-in-Memory Macro for Genome Processing
首款基于RRAM的存内计算宏单元，专为基因组处理优化。
65nm CMOS, 1.0V, 2.07 TOPS/W, 2.12 G suffixes/J
JSSC 2024第7期MemoryEmerging Memory
A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for Noise Rejection
基于22nm FD-SOI工艺的256kb MRAM存内计算宏，采用差分读出架构解决电源和耦合噪声问题。
256kb, 22nm FD-SOI, 128-512行和512列全并行
JSSC 2024第7期Power ManagementEmerging Memory
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage
EMBER提出高效多比特RRAM宏设计，优化读写电路并提升存储密度与可靠性。
100 MHz, 64k×48=3M cells
JSSC 2024第7期MemoryEmerging Memory
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine Arpan
16nm异构RISC-V SoC Siracusa，集成MRAM神经引擎，提升XR能效。
65.2 GOp/s/mm², 8.84 TOp/J
JSSC 2024第8期MemoryEmerging Memory
RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM
RoboVisio是一款高效灵活的专用SoC，用于微型机器人自主导航中的视觉任务。
22nm CMOS, 0.22 nJ/pixels, 3.5 TOPS/W
JSSC 2024第9期MemoryFlash MemoryEmerging Memory
Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro Bastien Giraud , Sebastien Ricavy , Cyrille Laffond, Ilan Sever, Valentin Gherman
提出智能写入算法提升RRAM宏的性能与可靠性
128kb RRAM宏, 130nm CMOS, 28.1µA读取裕度, BER<10⁻⁷
JSSC 2024第10期MemoryEmerging Memory
AIMMI: Audio and Image Multi-Modal Intelligence via a Low-Power SoC With 2-MByte On-Chip MRAM for IoT Devices
提出了一种超低功耗多模态信号处理SoC，集成DNN引擎和音像信号处理加速器，适用于物联网场景。
3-10 TOPS/W峰值能效，功耗0.25-3.84 mW
JSSC 2024第10期MemoryEmerging Memory
Algorithm 1 NE Code Example for CONV 1: procedure CONVOLUTION LAYER 2: #Load weights from MRAM to weight cache 3: LD_WEIGHT(addr_MRAM, addr_WeightCache, . . . ) 4: convolution_loop: 5: #Load activation from activation memory to local memory. Then do convolution. 6: MOV(row, col, addr_ActMem, addr_LocalMem, . . . ) 7: CONV(row, col, channel, kernel_size, stride, . . . ) 8: #Register control in NCU for for-loop
论文提出了一种基于MRAM的卷积神经网络加速器设计，优化了权重加载和卷积计算流程。
1.5-kB双端口FFT内存，8-kB乒乓存储器，支持32/64 Mel通道
JSSC 2023第8期MemoryEmerging Memory
TinyV ers: A Tiny V ersatile System-on-Chip With State-Retentive eMRAM for ML Inference at the
TinyVers是一款超低功耗多功能SoC，支持边缘设备的机器学习应用。
17.6 GOPS, 1.7 µW to 20 mW, 17 TOPS/W
JSSC 2023第10期MemoryEmerging MemoryNeural Network Accelerator
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference Wang Ye , Linfang Wang , Zhidao Zhou, Junjie An, Weizeng Li, Hanghang Gao, Zhi Li
28nm工艺的2T1R RRAM存内计算宏单元，提升边缘智能设备能效。
28nm HKMG, 1-bit IN/3-bit W/4-bit O, 30.34–154.04 TOPS/W
JSSC 2022第1期MemoryEmerging MemoryCIM
A 40-nm, 64-Kb, 56.67 TOPS/W V oltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With V erification and Online Read-Dis turb Detection Jong-Hyeok Y oon , Member , IEEE
40纳米工艺64Kb RRAM宏单元，支持1-8位可编程向量矩阵乘法，峰值能效达56.67 TOPS/W。
56.67 TOPS/W, 1-8位输入和权重, 20位输出
JSSC 2022第1期MemoryEmerging Memory
V ega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive
Vega是一款面向物联网终端节点的十核SoC，支持DNN加速和认知唤醒，具有超低功耗和高能效。
1.7μW睡眠功耗，32.2 GOPS峰值性能，615 GOPS/W (8-bit INT), 1.3 TOPS/W (8-bit DNN), 79 GFLOPS/W (32-bit FP), 129 GFLOPS/W (16-bit FP)
JSSC 2022第3期MemoryEmerging MemoryCIM
A 40-nm 118.44-TOPS/W V oltage-Sensing Compute-in-Memory RRAM Macro With Write V erification and Multi-Bit Encoding Jong-Hyeok Y oon , Member , IEEE
40纳米工艺下基于电压感知的RRAM内存计算宏单元，实现118.44 TOPS/W能效
40nm CMOS, 118.44 TOPS/W, 256×256阵列
JSSC 2022第4期MemoryEmerging Memory
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference Kartik Prabhu , Albert Gural, Student Member , IEEE, Zainab F. Khan
CHIMERA是一款基于40nm CMOS工艺的非易失性边缘AI加速器，支持训练和推理，采用RRAM技术。
40nm CMOS, 0.92-TOPS峰值性能, 2.2-TOPS/W能效
JSSC 2022第6期Wireline I/OEmerging MemoryNeural Network Accelerator
A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device Y en-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang
22纳米1Mb 1024位读取数据保护的STT-MRAM宏，采用近存移位旋转功能降低峰值电流和能耗。
42.67 GB/s读取带宽，0.23 pJ/bit能效
JSSC 2022第9期Data ConvertersEmerging MemoryCIM
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-V erify, and Temperature-Independent ADC References Wantong Li ,X i a o y uS u n , Shanshi Huang
40nm MLC-RRAM计算内存宏，支持稀疏控制和片上写验证，加速DNN推理。
40nm CMOS, 97.8 GOPS/mm², 44.5 TOPS/W
JSSC 2021第4期MemoryEmerging Memory
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition
本文展示了一种基于SOT-MRAM的非易失性存储器，采用55nm CMOS工艺，实现60MHz写入和90MHz读取操作。
55nm CMOS, 1.2V, 60MHz写入, 90MHz读取
JSSC 2021第4期MemoryEmerging Memory
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator
提出一种基于RRAM和模型压缩的全片上权重存储DNN加速器，适用于移动机器学习应用。
TSMC-22 nm ULL CMOS, 127.9 mW, 123 GOPs, 0.96 TOPs/W
JSSC 2020第4期MemoryEmerging MemoryCIM
Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor with Monolithically Integrated ReRAM Yu e Z h a , Student Member , IEEE
Liquid Silicon是一款非易失性全可编程存内计算处理器，结合了FPGA的灵活性和专用加速器的高效性。
650mV低电压操作，1.2V下60.9 TOPS/W神经网络推理，480 GOPS/W基于内容的相似性搜索
JSSC 2019第1期MemoryEmerging Memory
A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination
28纳米1T1MTJ STT-MRAM存储器，采用单电容失调消除感测放大器和原位写入自终止技术
1-Mb容量, 2.8ns/3.6ns读取时间(25°C/120°C), 47%/60%写入功耗降低(25°C/120°C)
JSSC 2019第4期MemoryEmerging Memory
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5-nS Read
40纳米逻辑工艺兼容16Mb嵌入式垂直MRAM，采用混合电阻参考和单元位置补偿技术提升读取性能。
40nm CMOS, <±1 µA分辨率, 17.5 nS读取时间, -40°C至125°C工作温度
JSSC 2019第9期MemorySRAMEmerging Memory
Self-Convergent Trimming SRAM True Random Number Generation With In-Cell Storage Po-Shao Yeh, Chih-An Yang , Yi-Hong Chang, Yue-Der Chih, Chrong-Jung Lin, and Ya-Chin King
首次实现基于4T-2R自对准氮化物SRAM单元的真随机数生成器，通过自收敛修调机制减少工艺变异影响。
未明确提及（需补充具体参数如CMOS工艺/电压/速度）
JSSC 2019第11期MemoryEmerging MemoryProcessor/CPU
A 47.14- µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications
一种低功耗高性能的非易失性微控制器单元，采用STT-MRAM技术。
4714-µW, 200-MHz
JSSC 2015第5期MemoryEmerging Memory
Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology
提出一种高密度1TNR RRAM阵列架构，解决互连线压降问题并验证可行性。
未明确提及
JSSC 2014第8期MemoryEmerging Memory
A Bit-by-Bit Re-Writable E fla s hi naG e n e r i c6 5n m Logic Process for Moderate-Density Nonvolatile Memory Applications Seung-Hwan Song, Ki Chul Chun, and Chris H. Kim , Senior Member , IEEE
提出一种在65nm逻辑工艺中实现的可逐位重写的嵌入式闪存技术，解决未选字线干扰问题。
65nm CMOS, 未提及电压及速度
JSSC 2013第2期MemoryEmerging Memory
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory Ki Chul Chun, Hui Zhao , Student Member , IEEE, Jonathan D. Harms
本文研究了从65nm到8nm工艺节点下平面和垂直MTJ STT-MRAM的可扩展性及读写性能。
10年保留时间的热稳定因子
JSSC 2009第8期MemoryEmerging Memory
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, and
提出一种新型非易失性磁触发器（MFF），用于无待机功耗的SoC设计。
150nm CMOS, 1.5V, 3.5GHz, 500MHz存储操作
JSSC 2008第8期MemoryEmerging Memory
A 180 Kbit Embeddable MRAM Memory Module Joseph J. Nahas , Senior Member , IEEE, Thomas W. Andre
开发了一种180 Kbit MRAM模块，采用0.28微米CMOS工艺，具有双感测放大器和切换电容写入驱动。
180 Kbit, 0.28 micron CMOS
JSSC 2007第4期MemoryEmerging Memory
MRAM Cell Technology for Over 500-MHz SoC
新型MRAM单元技术实现500MHz以上SoC应用
200MHz操作速度/500MHz随机存取/2ns访问时间
JSSC 2007第11期Clocking & PLLsSRAMEmerging Memory
A 16-Mb Toggle MRAM With
介绍了一种采用分布式驱动宽摆幅电流镜方案的16Mb Toggle MRAM，支持100MHz突发模式。
16Mb容量, 100MHz突发模式, 0.13μm CMOS, 0.24μm MRAM工艺
JSSC 2006第3期MemoryEmerging Memory
Noise-Shaping Sense Amplifier for MRAM Cross-Point Arrays Matthew B. Leslie and R.
提出一种用于MRAM交叉点阵列的噪声整形读出放大器技术，无需精密元件和校准，降低电源噪声影响。
180nm CMOS, 20μV RMS噪声, 5μs读出时间, 10μA电流@100MHz