技术领域

RF & Wireless

362 篇相关论文 (2008–2026)

ISSCC 2024 Session 4 RF & Wireless
A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal
Jongsoo Lee, Jaehyuk Jang, Wooseok Lee, Bosung Suh, Heeyong Yoo,
Beomyu Park, Jeongkyun Woo, Jaeeun Jang, Inhyo Ryu, Honggul Han, Jaeyoung Kim, Byoungjoong Kang, Minchul Kang, Hojung Kang, John Kang, Minseob Lee, Danbi Lee, Hyeonuk Son, Suhyeon Lee, Soyeon Kim, Hongjong Park, Sangsung
ISSCC 2024 Session 4 RF & Wireless
A 79.7µW Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS
Nikolaj Andersen1, Sumit Bagga1, Jørgen Andreas Michaelsen1,
Håkon A. Hjortland1, Lieuwe Leene1, Torleif Skår1, Espen Stenersen1, Dag T. Wisland1,2 Novelda, Oslo, Norway University of Oslo, Oslo, Norway 1 2 In recent years ultra-wideband (UWB) radios have found increasing use in a
ISSCC 2024 Session 19 RF & Wireless
A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique
Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Zhihua Wang, Baoyong Chi
Voltage-controlled-oscillators (VCOs) with simultaneous low phase noise and wide frequency tuning range (FTR) spanning from tens GHz to millimeter-wave (mm-wave) bands are required for various standardized applications,
Tsinghua University, Beijing, China
ISSCC 2024 Session 19 RF & Wireless
A 0.07mm2 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10MHz and 200.7dBc/Hz FoMA in 65nm CMOS
Ya Zhao*1, Chao Fan*1, Qiuyu Fang1, Guohe Zhang1, Jun Yin2, Pui-in Mak2, Li Geng1
low phase noise (PN) and low phase errors are the cornerstone of high-data-rate wireless transceivers, especially with the increasingly more complex modulation schemes. Frequency division, polyphase filters, and ring osci
Xi’an JiaoTong University, Xi’an, China University of Macau, Macao, Ch
ISSCC 2024 Session 19 RF & Wireless
An 8.9-to-21.9GHz Single-Core Oscillator with Reconfigurable Class-F-1 and Enhanced-Colpitts Dual-Mode Operation Achieving 209dBc/Hz FoMT
Zehui Kang, Chen Yu, Liang Wu
Emerging needs for incorporating multistandard or software-defined-radio transceivers onto a single chip necessitate oscillator signals with an octave coverage for enabling seamless full-range frequency synthesis. Althoug
Chinese University of Hong Kong, Shenzhen, China
ISSCC 2024 Session 19 RF & Wireless
A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with
a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference, Spur
multipliers, as it can lower the phase noise of a VCO beyond what can be achieved by the PLL loop bandwidth. The amount of phase-noise reduction depends on the injection strength and reaches a maximum when the clock edge
Hangil Choi, SeongHwan Cho Korea Advanced Institute of Science and Tec
ISSCC 2024 Session 18 RF & Wireless
A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET
R. L. Nguyen1, A. Mellati1, A. Fernandez2, A. Iyer3, A. Fan1, B. Reyes2, C. Abidin1,
C. Nani4, D. Albano4, F. Ahmad1, F. Solis2, G. Minoia4, G. Hatcher1, M. Bachu3, M. Garampazzi4, M. Hassanpourghadi1, N. Fan1, P. Prabha1, S. Fan3, S. Ho5, T. Dusatko5, T. Wu1, W. Elsharkasy1, Z. Sun6, S. Jantzi1, L. Tse3
ISSCC 2024 Session 18 RF & Wireless
An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm
periods (Ts and 2Ts). This duty cycle target estimation is common for all the slices, considering that slice-to-slice tr
eq (1) F. Ahmad1, A. Mellati1, A. Fernandez2, A. Iyer 3, A. Fan1, B. Reyes 2, C. Abidin 1, C. Nani 4, D. Albano 4, F. Solis 2, G. Minoia 4, G. Hatcher 1, H. Carrer 2, K. Kota 1, L. Wang 1, M. Bachu 3, M. Garampazzi 4, M.
ISSCC 2024 Session 18 RF & Wireless
A 4×64Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter
Susnata Mondal, Junyi Qiu, Sashank Krishnamurthy, Joe Kennedy,
from limited reach due to channel loss. Multi-mode vertical-cavity surface-emitting laser (VCSEL)-based optical interconnects can enable high-bandwidth connectivity while extending the reach to tens of meters [1-3]. Plug
Soumya Bose, Tolga Acikalin, Shuhei Yamada, James Jaussi, Mozhgan Mans
ISSCC 2024 Session 18 RF & Wireless
A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS
is symmetric from PLL to the four ADCs. In order to reduce jitter and random skew, it, uses only two stages of CMOS buff
clock channel of 1.2mm. The transmission line effect of the clock channel is carefully modeled to make sure the ADC clock has low jitter and low skew with sharp rail-to-rail edges. Guansheng Li1, Adesh Garg1, Tim He1, Ul
ISSCC 2024 Session 13 RF & Wireless
A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency
Chanheum Han*, Ki-Soo Lee*, Joo-Hyung Chae
*Equally Credited Authors (ECAs) The demand for high-bandwidth data communication in various data-centric applications has increased significantly. It requires many repetitive data transfers between processing units and o
Kwangwoon University, Seoul, Korea
ISSCC 2024 Session 13 RF & Wireless
A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with
WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver, and Parasitic Capacitance Reduction
Yangho Seo*, Jihee Choi*, Sunki Cho, Hyunwook Han, Wonjong Kim, Gyeongha Ryu, Jungil Ahn, Younga Cho, Sungphil Choi, Seohee Lee, Wooju Lee, Chaehyuk Lee, Kiup Kim, Seongseop Lee, Sangbeom Park, Minjun Choi, Sungwoo Lee,
ISSCC 2024 Session 13 RF & Wireless
A 1Tb Density 3b/Cell 3D-NAND Flash on a 2YY-Tier Technology with a 300MB/s Write Throughput
Koichi Kawai1, Yuichi Einaga1, Yoko Oikawa1, Yankang He2, Biagio Iorio3,
Shigekazu Yamada1, Yoshihiko Kamata1, Tomoko Iwasaki2, Andrea D’alessandro3, Erwin Yu2, Arvind Muralidharan4, Qinge Li2, Henry Nguyen2, Kim-Fung Chan2, Michele Piccardi2, Takaaki Ichikawa1, Jeff Yu2, Guan Wang2, Kwangwon
ISSCC 2024 Session 13 RF & Wireless
A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration lines can be reduced by ¼ compared to a conventional direct feedback DFE [1]. Furthermore, instead of using a CML buffer in the current-summing DFE, the CTLE serves as the DFE summer; hence, overall power consumption is reduced.
Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An,
Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gunhee Cho, Chanyong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok,
ISSCC 2024 Session 13 RF & Wireless
A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS
Weitao Wu*, Hongzhi Wu*, Liping Zhong, Xuxu Cheng, Xiongshi Luo,
massive computing and AI technologies, the memory interface is critical to achieve higher computational throughput. Increasing the parallel-channel density is an effective solution to improve the throughput [1]. However,
Dongfan Xu, Catherine Wang, Zhenghao Li, Quan Pan Southern University
ISSCC 2024 Session 13 RF & Wireless
A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization
Jinhyung Lee*, Kyungjun Cho*, Chang Kwon Lee, Yeonho Lee,
Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang,
ISSCC 2024 Session 13 RF & Wireless
A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate
Wontaeck Jung, Hyunggon Kim, Do-Bin Kim, Tae-Hyun Kim, Namhee Lee,
Dongjin Shin, Minyoung Kim, Youngsik Rho, Hun-Jong Lee, Yujin Hyun, Jaeyoung Park, Taekyung Kim, Hwiwon Kim, Gyeongwon Lee, Jisang Lee, Joonsuc Jang, Jungmin Park, Sion Kim, Su Chang Jeon, Suyong Kim, Jung-Ho Song, Min-S
ISSCC 2024 Session 13 RF & Wireless
A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process Figure 13.2.4(a) shows a conceptual DRAM read block diagram. The DLL matches the skew of CLK and DQS. The quadrature-error corrector (QEC) matches the 4-phase skew.
Previously, the output of the DLL goes directly into the QEC[1]. The code change of the, DLL due to any external factor
does not change properly or shows slow response, a deterministic jitter is generated. In our design, an open-loop DCC, shown in Fig. 13.2.4(b), is added before the QEC. Dutycycle distortion, from DLL code variation, is n
ISSCC 2024 Session 13 RF & Wireless
A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets
Kihwan Seong, Wooseuk Oh, Hyunwoo Lee, Gyeomje Bae, Youngseob Suh,
Hyemun Lee, Juyoung Kim, Eunsu Kim, Yeongeon Kang, Gunhu Mo, Youjin Lee, Mingyeong Kim, Seongno Lee, Donguk Park, Byoung-Joo Yoo, Hyo-Gyuem Rhew, Jongshin Shin Samsung Electronics, Hwaseong, Korea With the development of
ISSCC 2024 Session 13 RF & Wireless
A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry
Jaehyeok Yang*, Hyeongjun Ko*, Kyunghoon Kim, Hyunsu Park, Jihwan Park,
Ji-Hyo Kang, Jinyoup Cha, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sangyeon Byeon, Sungkwon Lee, Hyeony
ISSCC 2024 Session 12 RF & Wireless
A 64.4% Efficiency 5.8GHz RF Wireless Power Transfer Receiver with GaAs E-pHEMT Rectifier and 45.2μs MPPT Time SIDITO Buck-Boost Converter Using VOC Prediction Scheme
Kyohei Ichikawa1, Tatsuki Iwata1, Saya Onishi1, Tomohiro Higuchi1,
enables long-distance power transfer of 1~10m, eliminating the need for power supply wiring to a huge number of sensors in the IoT era. Recently, above 1W-class power receiver circuits (RX) are becoming required for shor
Yuya Hirose2, Naoki Sakai2, Kenji Itoh2, Kousuke Miyaji1 Shinshu Unive
ISSCC 2024 Session 12 RF & Wireless
A Packageless Anti-Tampering Tag Utilizing Unclonable Sub-THz Wave Scattering at the Chip-Item Interface
silicone glue and iron particle patterns. In Fig. 12.5.2, a digital counter is deployed, so, that the SPDT control codes
responses are sequentially collected and backscattered to the reader. Eunseok Lee, Xibi Chen, Maitreyi Ashok, Jaeyeon Won, Anantha Chandrakasan, Figure 12.5.4 shows the sub-THz BPSK modulator based on a pair of SPDT swit
ISSCC 2024 Session 12 RF & Wireless
A 19μW 200Mb/s IoT Tag Demonstrating High-Definition Video Streaming via a Digital-Switch-Based Reconfigurable 16-QAM Backscatter Communication Technique
Yongling Zhang, Rongliang Luo, Ji Xiong, Siqi Liang, Miao Meng
Recent work in low-power backscatter modulation has enabled a new set of IoT applications requiring low-to-medium throughput [1-4]. However, applications demanding medium-to-high throughput still rely on mW-level convent
Tongji University, Shanghai, China
ISSCC 2024 Session 12 RF & Wireless
A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute Efficiency
Kareem Rashed1, Aswin Undavalli2, Shantanu Chakrabartty2, Aravind Nagulu2, Arun Natarajan1
Louis, St. Louis, MO 1 2 Correlators are fundamental building blocks in radar/communication signal processing and analog-to-information (A-to-I) applications such as spectrum sensing [1]. Typically, correlation, which is
Oregon State University, Corvallis, OR Washington University in St
ISSCC 2024 Session 12 RF & Wireless
A mm-Wave/Sub-THz Synthesizer-Free Coherent Receiver with Phase Reconstruction Through Mixed-Signal Kramer-Kronig Processing
Sherif Ghozzy*, Muhamed Allam*, Emir Ali Karahan, Zheng Liu, Kaushik Sengupta
in the high mmWave and sub-THz frequencies can enable new applications in communication, sensing and imaging, if they can operate with low latency in high resource-constrained environments. In particular, for one-to-many
Princeton University, Princeton, NJ *Equally Credited Authors (ECAs) H
ISSCC 2024 Session 12 RF & Wireless
Monolithically Integrated Sub-63 fJ/b 8-Channel 256Gb/s Optical Transmitter with Autonomous Wavelength Locking in 45nm CMOS SOI
Kaisarbek Omirzakhov, Firooz Aflatouni
Optical links play a key role in many applications ranging from data centers to AI systems. Such links typically consist of a light source chip, a transmitter chip (which may be cointegrated with the light source), and a
University of Pennsylvania, Philadelphia, PA
ISSCC 2023 Session 31 RF & Wireless
A 0.4-to-0.95GHz Distributed N-Path Noise-Cancelling Ultra-Low-Power RX with Integrated Passives Achieving
-85dBm/100kb/s Sensitivity, -41dB SIR and 174dB RX FoM, in 22nm CMOS
(ULP) radios requires ULP RX that can operate in crowded ISM environments across geographies while minimizing off-chip components for low cost and for satisfying wearable/IoT device footprints (Fig. 31.8.1). ULP RX based
Hayden Bialek, Matthew Johnston, Arun Natarajan Oregon State Universit
ISSCC 2023 Session 31 RF & Wireless
A 0.7-to-2.5GHz Sliding Digital-IF Quadrature Digital Transmitter Achieving >40% System Efficiency for Multi-Mode NB-IoT/BLE Applications
Chunxiao Hu, Diyang Zheng, Yun Yin, Jie Lin, Yicheng Li, Wei Li, Hongtao Xu
Cellular narrowband Internet-of-Things (NB-IoT) is an important branch of low-power wide-area IoT applications, which specifies multiple operation bands over 663 to 915MHz (LB) and 1710 to 2010MHz (MB), up to 23dBm outpu
Fudan University, Shanghai, China
ISSCC 2023 Session 31 RF & Wireless
A ULP Long-Range Active-RF Tag with Automatic AntennaInterface Calibration Achieving 20.5% TX Efficiency at -22dBm
EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power
Zhizhan Yang1, Jun Yin1, Wei-Han Yu1, Haochen Zhang1, Pui-In Mak1, Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 For event-driven IoT applicatio
ISSCC 2023 Session 31 RF & Wireless
A Passive Bidirectional BLE Tag Demonstrating Battery-Free
Communication in Tablet/Smartphone-to-Tag,
Tag-to-Tablet/Smartphone, and Tag-to-Tag Modes Ziyi Chang*1, Qijing Xiao*1,2, Weixiao Wang1,2, Yuxuan Luo1, Bo Zhao1 Zhejiang University, Hangzhou, China, 2Microaiot, Hangzhou, China *Equally Credited Authors (ECAs) 1 Wi
ISSCC 2023 Session 31 RF & Wireless
A 128-Channel 2mm×2mm Battery-Free Neural Dielet Merging Simultaneous Multi-Channel Transmission Through Multi-Carrier Orthogonal Backscatter
Changgui Yang, Zhihuan Zhang, Lei Zhang, Yunshan Zhang, Zhuhao Li,
wireless implants have been investigated as an alternative to traditional cable-based neural interfaces. Simultaneous massive-channel recording capability is essential to study cellular interconnections and network prope
Yuxuan Luo, Gang Pan, Bo Zhao Zhejiang University, Hangzhou, China Wit
ISSCC 2023 Session 31 RF & Wireless
A Fully Integrated IEEE 802.15.4/4z-Compliant 6.5-to-8GHz UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28nm Process
Wan Kim1, Hyun-Gi Seok1, Geunhaeng Lee1, Sinyoung Kim1, Jae-Keun Lee1,
Chanho Kim1, Wonkang Kim1, Wonjun Jung1, Youngsea Cho1, Seungyong Bae1, Jongpil Cho1, Hyeokju Na1, Byoungjoong Kang1, Honggul Han1, Hyeonuk Son1, Chiyoung Ahn1, Hoon Kang1, Sukjin Jung1, Hyukjun Sung1, Yeongdae Kim1, Don
ISSCC 2023 Session 31 RF & Wireless
A Quadrature Uncertain-IF IR-UWB Transceiver with Twin-OOK Modulation
Bowen Wang, Woogeun Rhee, Zhihua Wang
Benefiting from good energy efficiency and fine ranging accuracy, impulse-radio ultrawideband (IR-UWB) has been revived recently for short-distance communications. The IR-UWB transceiver, however, faces two major issues
Tsinghua University, Beijing, China
ISSCC 2023 Session 28 RF & Wireless
A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor
Tracking, Refresh-Management Functionality, Per-Row
Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement Woongrae Kim, Chulmoon Jung, Seongnyuh Yoo, Duckhwa Hong, Jeongjin Hwang, Jungmin Yoon, Ohyong Jung, Joonwoo Choi
ISSCC 2023 Session 28 RF & Wireless
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL
Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim,
Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jungbum Shin, Yanggyoon Loh, Chang Yong Lee, Junmyung Woo, Hyeseung Yu, Changhyun Bae, Reum
ISSCC 2023 Session 28 RF & Wireless
A 32Gb/s/pin 0.51pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS
Jung-Hun Park1, Hyeonseok Lee1, Hoyeon Cho1, Sanghee Lee1,
demand, the DRAM interface bandwidth also increases steeply each year; for graphics applications, the bandwidth per pin has increased to 27Gb/s/pin, thanks to T-coils implemented using RDL layers [1]. As I/O hardware exp
Kwang-Hoon Lee1, Han-Gon Ko2, Deog-Kyoon Jeong1 Seoul National Univers
ISSCC 2023 Session 28 RF & Wireless
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection
Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh,
Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyogyuem Rhew, Jongshin Shin Samsung Electronics, Hwaseung, Korea A crit
ISSCC 2023 Session 28 RF & Wireless
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization
Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim,
communication, deep learning, advanced driverassistance systems (ADAS), and extended reality (XR), have fueled demand for increased computing power and per-pin interface bandwidth. Recently, four-level pulse-amplitude mo
Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim,
ISSCC 2023 Session 28 RF & Wireless
A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers
Byungryul Kim, Seungpil Lee, Beomseok Hah, Kangwoo Park, Yongsoon Park,
Kangwook Jo, Yujong Noh, Hyeoncheon Seol, Hyunsoo Lee, Jaehyeon Shin, Seongjin Choi, Youngdon Jung, Sungho Ahn, Yonghun Park, Sujeong Oh, Myungsu Kim, Seonguk Kim, Hyunwook Park, Taeho Lee, Haeun Won, Minsung Kim, Cheulh
ISSCC 2023 Session 25 RF & Wireless
A 1-to-5GHz All-Passive Frequency-Translational 4th-Order N-path Filter with Low-Power Clock Boosting for High Linearity and Relaxed Pdc-Frequency Trade-Off to the LO overlap while using 2× higher-duty-cycle clocks, thereby enabling a 4 to 5× higher operating frequency compared to higher-order N-path filters [1-5]. These inductors do not limit tuning range at all, unlike the coupling inductors in prior higherorder N-path topologies.
Aravind Nagulu1, Mingyu Yi 1, Yi Zhuang1, Sasank Garikapati2, Harish Krishnaswamy2
The higher-order N-path filter was designed to operate from 1 to 5GHz. The three capacitors CF, CG, and CB of the baseband elliptical-LPF loads are designed with a 5b control to program the bandwidth, selectivity, and OO
ISSCC 2023 Session 25 RF & Wireless
A 4b RFDAC at 8GS/s for FMCW Chirps with 4GHz Bandwidth in 10µs
Soumya Krishnapuram Sireesh1,2, Sanaz Hadipour Abkenar1,2,
Niels Christoffers1, Christoph Wagner1, Thorsten Brandt1, Andreas Stelzer2 Infineon Technologies, Linz, Austria Johannes Kepler University, Linz, Austria 1 2 A frequency-modulated continuous-wave (FMCW) radar is highly r
ISSCC 2023 Session 25 RF & Wireless
A 19.7-to-43.8GHz Power Amplifier with Broadband Linearization Technique in 28nm Bulk CMOS
Weisen Zeng1, Li Gao1, Ningzheng Sun1, Hongtao Xu2, Quan Xue1, Xiuyin Zhang1
Fudan University, Shanghai, China 1 2 5G mm-wave systems in the frequency-range-2 (FR2) band (ranging from 24.25 to 43.5GHz) are expected to provide multi-gigabit-per-second (mGb/s) data-rates. Different FR2 bands are em
South China University of Technology, Guangzhou, China
ISSCC 2023 Session 25 RF & Wireless
A 4.1W Quadrature Doherty Digital Power Amplifier with 33.6% Peak PAE in 28nm Bulk CMOS
Jiaxiang Li1, Yun Yin1, Hang Chen2, Jie Lin1, Yicheng Li1, Xianglong Jia1,
and higher output-power requirements, especially at the base station side. As shown in Fig. 25.1.1, compared to the traditional analog-transmitter architectures with high-power GaAs/GaN poweramplifier (PA) modules, digit
Zhen Hu1, Xiuyin Zhang2, Hongtao Xu1 Fudan University, Shanghai, China
ISSCC 2023 Session 12 RF & Wireless
A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver
Ahmed E. Abdelrahman1, Mostafa G. Ahmed1,2, Mahmoud A. Khalil1,
increasing intra-datacenter traffic is pushing the demand for ultra-high-speed optical interconnect that maximizes both power efficiency and data rate per wavelength. Intensity modulation-direct detection (IM-DD) links a
Mohamed Badr Younis1, Kyu-Sang Park1, Pavan Kumar Hanumolu1 University
ISSCC 2023 Session 12 RF & Wireless
A 7 pA/√Hz Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS
Kadaba Lakshmikumar*1, Alexander Kurylak*1, Romesh Kumar Nandwana*1,
amplifier (TIA) is a critical building block that impacts the noise, bandwidth, and power consumption of intensity modulation and direct detection (IMDD) optical links used in data centers. CMOS TIAs using the shunt-feed
Bibhu Das1, Joe Pampanin1, Mike Brubaker1, Pavan Kumar Hanumolu2 CISCO
ISSCC 2023 Session 12 RF & Wireless
A 0.96pJ/b 7×50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies
Mayank Raj1, Chuan Xie1, Ade Bekele1, Adam Chou1, Wenfeng Zhang1,
Ying Cao1, Jae Wook Kim1, Nakul Narang2, Hongyuan Zhao2, Yipeng Wang2, Kee Hian Tan2, Winson Lin1, Jay Im1, David Mahashin1, Santiago Asuncion1, Parag Upadhyaya1, Yohan Frans1 AMD, San Jose, CA AMD, Singapore, Singapore
ISSCC 2022 Session 8 RF & Wireless
A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS
Jitter, -120dBc/Hz PN at 1MHz Offset, and with Retrace Time, of 12.5ns and 2µs Chirp Settling Time
Spain 1 2 At the center of autonomous driving and range and motion sensing in industrial and healthcare applications are FMCW RADARs, which provide the means for object range and velocity estimation. With future widespre
Hyman Shanan1, Declan Dalton2, Vamshi Chillara 3, Pablo Dato4 Analog D
ISSCC 2022 Session 8 RF & Wireless
A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup
Somnath Kundu, Timo Huusari, Hao Luo, Abhishek Agrawal, Eduardo Alban,
Sarah Shahraini, Thao Xiong, Dan Lake, Stefano Pellerano, Jason Mix, Nasser Kurd, Mohamed Abdel-moneum, Brent Carlton Intel, Hillsboro, OR A high-performance clock generator with extremely low jitter, area, and power con
ISSCC 2022 Session 8 RF & Wireless
A 0.0078mm2 3.4mW Wideband Positive-Feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting Gm Boosting
feedforward paths, whose Gm is 2/RS without the current amplification of CM. When, AgmbiasRS=gm3/(gm2+gm3), the sum of F
γ/(gm2+gm3)RS. Accordingly, the noise factor of the LNA, F can be given by Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo Nanyang Technological University, Singapore, Singapore The noise figur
ISSCC 2022 Session 24 RF & Wireless
An LPWAN Radio with a Reconfigurable Data/Duty-CycledWake-Up Receiver
Keun-Mok Kim1, Kyung-Sik Choi1, Hyunki Jung1,2, Byeonghun Yun1, Subin Kim2,
Demands for the low-power wide-area network (LPWAN) are increasing along with a growing market for low data-rate, long-range internet of things (IoT) applications. Although many radios have been released for various LPWA
Wonkab Oh2, Eui-Soo Lee3, Sujin Park2, Eui-Rim Jeong3, Jinho Ko2, Sang