JSSC 分类

Analog Circuits

99 篇期刊论文

子分类 Subcategories
Op-Amp
14 篇
Bandgap Reference
12 篇
JSSC 2025第1期Analog Circuits
Ultrawideband Distributed Amplifier With Positive Feedback and
采用正反馈和堆内耦合技术的超宽带分布式放大器设计
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JSSC 2025第2期Analog Circuits
A 230 NEF Split Steering Amplifier for Switched Capacitor Circuits With 142 dB
一款用于开关电容电路的230 NEF分离转向放大器，具有142 dB性能
230 NEF, 142 dB
JSSC 2025第4期Analog CircuitsOp-Amp
A 038 mW 200 kHz BW Digital Intensive Single Opamp Fourth Order
一篇关于低功耗数字密集型单运放四阶连续时间滤波器的IEEE JSSC论文
038 mW, 200 kHz BW
JSSC 2025第5期Analog Circuits
A 394 TOPS W Matched Filter With Charge Domain Computing for GPS
一种用于GPS信号捕获的电荷域计算匹配滤波器，能效达394 TOPS/W
394 TOPS/W
JSSC 2025第6期Analog Circuits
A Programmable Filtering and Frequency Translation by Aliasing IF
一种基于混叠中频接收机的可编程滤波与频率转换技术
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JSSC 2025第7期Analog Circuits
Design and Implementation of a D Band Bidirectional Common Gate Amplifier in 45
设计并实现了一款45纳米工艺下的D波段双向共栅放大器
45nm CMOS, D波段频率范围
JSSC 2025第8期Analog Circuits
A 947 dB Dynamic Range Fully Passive Switched Capacitor Low Pass Filter
一款具有947 dB动态范围的全被动开关电容低通滤波器
947 dB动态范围
JSSC 2025第8期Analog CircuitsBandgap Reference
Compact PNP BJT Based Temperature Sensor and Sub 1 V Bandgap Reference for SoC
基于紧凑PNP BJT的温度传感器和亚1V带隙基准源设计
亚1V工作电压, 高精度温度传感
JSSC 2025第10期Analog CircuitsNeural Interface
A TDMA Neural Recording SoC With IIR-RLS Adaptive Filters for 83.4 dB Artifact Suppression Across 256 Channels
一种采用TDMA和IIR-RLS自适应滤波器的神经记录SoC，实现834dB刺激伪迹抑制。
65nm CMOS, 4.9/4.8 µVrms噪声, 5.8 µW功耗
JSSC 2025第10期Analog Circuits
An Indirect ToF Sensor With In-Pixel Adaptive 16-Scheme for Background Light Rejection and Floating Diffusion
提出一种自适应16方案间接飞行时间传感器，有效抑制背景光并降低噪声。
160×120分辨率，0.3-2.9m测距范围，<2.7%深度噪声，<2.1%非线性，30fps@50MHz调制频率
JSSC 2025第11期Analog CircuitsNeural Interface
A TDMA Neural Recording SoC With IIR-RLS Adaptive Filters for 83.4 dB Artifact Suppression Across 256 Channels
一款采用IIR-RLS自适应滤波器的TDMA神经记录SoC，实现83.4 dB刺激伪迹抑制
65nm CMOS, 4.9/4.8 µVrms噪声, 5.8 µW功耗
JSSC 2025第11期Analog Circuits
An Indirect ToF Sensor With In-Pixel Adaptive 16-Scheme for Background Light Rejection and Floating Diffusion
提出一种自适应16方案间接飞行时间传感器，有效抑制背景光并降低噪声。
160×120分辨率，0.3-2.9m测距范围，<2.7%深度噪声，<2.1%非线性，30fps@50MHz调制频率
JSSC 2024第2期Analog Circuits
A 46.6 µg/√Hz Single-Chip Accelerometer Exploiting a DTC-Assisted Chopper Amplifier
一款采用DTC辅助斩波放大器的单芯片加速度计，实现超低噪声和偏置不稳定性。
46.6 µg/√Hz热噪声, 472 µg偏置不稳定性, >1000 g满量程
JSSC 2024第5期Analog Circuits
A Sub-5mW Monolithic CMOS-MEMS Thermal Flow Sensing SoC With ±6 m/s Linear Range
提出一种功耗低于5mW的CMOS-MEMS单片集成热流传感器SoC，具有高灵敏度和宽线性范围。
156mV/(m/s)灵敏度，±11m/s检测范围，±6m/s线性范围，86μm/s检测限，<5mW功耗
JSSC 2024第10期Analog Circuits
III. C YCLICALLY CHARGED FIA A. Operation and Stably Controllable Amplifier Bias Point Fig. 2(b) illustrates the schematic and operating principle of a new FIA called CC-FIA. The large single reservoir capacitor in the conventional FIA is divided into several small capacitors whose total capacitance is significantly smaller than one in the conventional FIA. In the reset phase, all the reser- voir capacitors are charged to VDD. During the amplification phase, the reservoir capacitors are alternately connected to the amplifier to sequentially supply charge. The discharged
提出新型CC-FIA，通过分时充电小电容组替代传统大电容，实现稳定可控的放大器偏置。
NC-OVL, NSW, CRES, fSW, IS, VT, VOV等参数控制
JSSC 2023第8期Analog Circuits
A 100-to-10-kHz 5.4-to-216-µW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for MEMS
提出一种适用于物联网MEMS加速度计的动态放大器闭环读取电路，解决增益变化问题。
0.18-µm CMOS, 1.8V, 10 kHz to 1 MHz, 100 Hz to 10 kHz, 5.4 to 216 µW
JSSC 2023第10期Analog Circuits
A 1984-Pixels, 1.26 nW/Pixel Retinal Prosthesis Chip With Time-Domain In-Pixel Image Processing and Bipolar Stimulating Electrode Sharing Dong-Hwi Choi
一款1984像素视网膜假体芯片，采用时域像素内图像处理技术，显著降低功耗。
180 nm CMOS, 1.26 nW/pixel
JSSC 2023第10期Analog Circuits
A Process-Scalable Ultra-Low-V oltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less Resistance Multiplier
提出一种采用时间域放大器的超低电压睡眠定时器，实现高精度温度校准和低功耗。
65nm CMOS, 0.4V, 63nW, 180kHz, 2.73ppm/°C
JSSC 2023第11期Analog Circuits
A 65-nm CMOS Fluorescence Sensor for Dynamic Monitoring of
65纳米CMOS荧光传感器用于活细胞动态监测
65nm CMOS, 1.05fA最小检测电流, SNR>18dB
JSSC 2023第12期Analog Circuits
A Third-Order Quasi-Elliptic N-Path Filter With Enhanced Linearity Through
提出一种新型三阶准椭圆N路径滤波器，通过时钟增强线性度，实现高频操作与高功率处理能力。
1-5 GHz工作范围，+8.8 dBm带内P1dB，+23 dBm带内IIP3，+36 dBm带外IIP3
JSSC 2022第3期Analog CircuitsNeural Interface
A Digitally Assisted Multip lexed Neural Recording System With Dynamic Electrode Offset Cancellation via an LMS Interference-Canceling Filter
提出一种低功耗、面积高效的植入式神经记录系统，支持高密度神经植入应用。
每通道面积0.00248 mm²，功耗3.38 µW，输入参考噪声2.6 µVrms，噪声效率因子1.83
JSSC 2022第4期Analog Circuits
A − 121.5-dB THD Class-D Audio Amplifier With 49-dB LC Filter
提出一种双环路架构的D类音频放大器，抑制LC滤波器非线性49dB，THD达-121.5dB。
180-nm BCD, -121.5-dB THD, -107.1-dB THD+N, 21W@4Ω, 12W@8Ω
JSSC 2022第12期Analog Circuits
Monolithic GaN-Based Driver and GaN Switch With Diode-Emulated GaN Technique for 50-MHz Operation and Sub-0.2-ns Deadtime Control Tz-Wun Wang, Y u-Y ung Kao, Sheng-Hsi Hung, Y ong-Hwa Wen, Tzu-Hsien Y ang
基于GaN的单片驱动器和开关采用二极管仿真技术，实现高频高效转换
50 MHz工作频率，120 V/ns转换速率，95.4%峰值效率
JSSC 2021第1期Analog CircuitsBandgap Reference
A 1.16-V 5.8-to-13.5-ppm/ ◦C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers
一种高精度电流模式带隙基准电路，采用共享偏移补偿方案，适用于宽温度范围。
1.16V输出, 3.3V供电, -40°C至150°C温度范围, ±8.2mV输出变化
JSSC 2021第4期Analog CircuitsBandgap Reference
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3 σ Inaccuracy of +0.02%, − 0.12% for Battery-Monitoring Applications Jun-Ho Boo , Student Member , IEEE
提出一种单修调开关电容带隙基准电路，采用β补偿和曲率校正技术，结合DEM技术，实现高精度温度稳定性。
3σ不准确度+0.02%, −0.12%（-40°C至125°C），功耗17μA@27°C，面积0.38mm²
JSSC 2021第10期Analog CircuitsBandgap Reference
A Single BJT Bandgap Reference With Frequency Compensation Exploiting
提出一种单BJT带隙基准源，通过频率补偿优化稳定性和功耗
温度系数26.3 ppm/°C(-40°C~140°C)，电压精度0.33%，PSR -52dB@100Hz/-44dB@1MHz，功耗192nW
JSSC 2020第10期Analog Circuits
A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter Ya n g X u , Member , IEEE,H a n gH u
提出一种基于耦合源跟随器的低功耗高线性度五阶低通滤波器。
0.18µm CMOS, 1.3V, 0.5mA, 20MHz带宽, 76.9dB动态范围
JSSC 2019第3期Analog Circuits
Integrated Synthetic Fourth-Order Q-Enhanced Bandpass Filter With High Dynamic Range, Tunable Frequency, and Fractional
本文展示了一种可调谐的微波四阶Q增强带通滤波器，采用130nm SiGe BiCMOS工艺实现。
4-8GHz中心频率可调, 2%-25%带宽可调, 151-166dB·Hz动态范围, 112-125mW功耗
JSSC 2019第7期Analog CircuitsBandgap Reference
A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From −45◦C to 125 ◦C
提出了一种在7nm FinFET工艺中实现的可编程温度系数的1V精密电压参考源。
1V, 最大误差±0.2%, 最小温度系数6ppm/°C, 线调节率0.1%/V, 面积0.078mm²
JSSC 2019第7期Analog Circuits
A Fast T&H Overcurrent Detector for a Spinning Hall Current Sensor With Ping-Pong and
一种快速TH过流检测器，用于具有乒乓结构的旋转霍尔电流传感器
568 ns总体延迟，250 kHz旋转频率，85 μT残余偏移，136 μT rms输入参考噪声，1.7 MHz带宽
JSSC 2019第12期Analog CircuitsBandgap Reference
A 192-pW V oltage Reference Generating Bandgap–Vth With Process and Temperature Dependence Compensation Youngwoo Ji , Jungho Lee
提出一种利用工艺偏差维度效应补偿阈值电压变化的192皮瓦超低功耗电压基准电路
0.18µm CMOS, 192pW, 0.0045mm², 0.53%工艺偏差, 33ppm/°C温度系数
JSSC 2018第2期Analog Circuits
A Continuous Time Digital IIR Filter With Signal Derived Timing and
一篇关于连续时间数字IIR滤波器的IEEE JSSC论文，重点介绍了信号衍生时序和全敏捷设计。
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JSSC 2018第3期Analog Circuits
A 1 V 025 μW Inverter Stacking Amplifier With 107 Noise Efficiency Factor JSSC
一种1V 0.25μW的逆变器堆叠放大器，噪声效率因子达107
1V, 0.25μW, 107 Noise Efficiency Factor
JSSC 2018第7期Analog Circuits
A 12 V Dynamic Bias Latch Type Comparator in 65 nm CMOS With 04 mV
65nm CMOS工艺下12V动态偏置锁存型比较器，输入噪声04mV
12V, 04mV输入噪声
JSSC 2018第10期Analog CircuitsOp-Amp
A 535 mW 10 MHz Single Opamp Third Order CT ΔΣ Modulator With CTC Amplifier
一种采用CTC放大器的535mW 10MHz单运放三阶连续时间ΔΣ调制器
535mW功耗, 10MHz带宽
JSSC 2018第10期Analog CircuitsBandgap Reference
A Digitally Calibrated Bandgap Reference With 006 Error for Low Side
一种数字校准带隙基准源，适用于低侧电流检测，误差为0.06%。
0.06%误差
JSSC 2018第12期Analog Circuits
A Low Quiescent Current Low THDN Class D Audio Amplifier With Area Efficient PW
一篇关于低静态电流低THDN D类音频放大器的IEEE JSSC期刊论文
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JSSC 2017第1期Analog CircuitsBiosignal
An EEG Acquisition and Biomarker Extraction System Using Low Noise Amplifier an
该论文提出了一种使用低噪声放大器的EEG采集和生物标志物提取系统。
无
JSSC 2017第2期Analog Circuits
496 Offset Canceling Current Sampling Sense Amplifier for
一种用于电阻式非易失性存储器的偏移消除电流采样感测放大器
无
JSSC 2017第2期Analog Circuits
505 A Performance Aware Low Quiescent Headphone Amplifier in 65 nm CMOS
65纳米CMOS工艺下的高性能低静态耳机放大器设计
65nm CMOS, 1.2V
JSSC 2017第2期Analog Circuits
528 A 026 n J node 400 k Hz Tx Driving Filtered Fully Differential Readout IC W
一款528A、0.26nJ/节点、400kHz的Tx驱动滤波全差分读出IC
528A, 0.26nJ/node, 400kHz
JSSC 2017第3期Analog CircuitsNeural Interface
A High Dynamic Range Neural Recording Chopper Amplifier for
一种用于同步神经记录的高动态范围斩波放大器
无
JSSC 2017第6期Analog Circuits
A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent Off Instant On Filters in
使用MLC ReRAM的3T1R非易失性TCAM，实现频繁断电即时开启的过滤器
无
JSSC 2017第7期Analog Circuits
Low Power Wideband Analog Channelization Filter Bank Using Passive Polyphase FF
本文提出了一种低功耗宽带模拟信道化滤波器组，采用被动多相FF技术。
无
JSSC 2017第8期Analog Circuits
A Spur and Phase Noise Filtering Technique for Inductor Less Fractional N Injec
提出一种无电感分数N注入锁相环的杂散和相位噪声滤波技术
无
JSSC 2017第11期Analog Circuits
A 54490 GHz Low Noise Amplifier in 65 nm CMOS
一篇关于65nm CMOS工艺下54490 GHz低噪声放大器的IEEE JSSC论文
65nm CMOS, 54490 GHz
JSSC 2017第11期Analog Circuits
A Noise Efficient 36 nVHz Chopper Amplifier Using an Inverter Based 02 V Supply
一种基于逆变器的0.2V电源噪声高效36 nVHz斩波放大器
36 nVHz, 0.2V
JSSC 2017第12期Analog Circuits
A 19 nVHz Noise 2 μV Offset 75 μA Capacitive Gain Amplifier With
一款低噪声、低偏移的电容增益放大器设计
19 nV/√Hz噪声, 2 μV偏移, 75 μA电流
JSSC 2017第12期Analog Circuits
Wideband Mixed Domain Multi Tap Finite Impulse Response Filtering of Out of Ban
宽带混合域多抽头有限脉冲响应滤波器设计
无
JSSC 2016第2期Analog Circuits
A 10 Gbs Inductorless AGC Amplifier With 40 dB Linear Variable Gain Control in
一款无电感AGC放大器，具有10 Gbps速度和40 dB线性可变增益控制
10 Gbps, 40 dB线性可变增益控制
JSSC 2016第3期Analog Circuits
A Low Power High CMRR Neural Amplifier System Employing CMOS Inverter Based OTA
一种基于CMOS逆变器OTA的低功耗高CMRR神经放大器系统
关键性能指标（如：CMRR值, 功耗, 增益）
JSSC 2016第5期Analog Circuits
An 80 GHz Low Noise Amplifier Resilient to the TX Spillover in
一款抗TX泄漏的80GHz低噪声放大器
80GHz, 低噪声, 相位调制
JSSC 2016第6期Analog Circuits
A 24 mA Quiescent Current 1 W Output Power Class D Audio Amplifier With
一款静态电流24mA、输出功率1W的D类音频放大器
24mA静态电流，1W输出功率
JSSC 2016第9期Analog Circuits
55 nm SiGe BiCMOS Distributed Amplifier Topologies for Time Interleaved 120 Gbs
55 nm SiGe BiCMOS分布式放大器拓扑结构用于时间交织120 Gbps应用
120 Gbps
JSSC 2016第9期Analog CircuitsOp-Amp
A 56 nV Hz Chopper Operational Amplifier Achieving a 05 μV Maximum
一款56 nV/√Hz斩波运算放大器，最大偏移仅0.5 μV
56 nV/√Hz噪声密度，0.5 μV最大偏移
JSSC 2016第10期Analog Circuits
A Load Adaptive Class G Headphone Amplifier With Supply Rejection
一种负载自适应的G类耳机放大器，具有电源抑制带宽增强功能
无
JSSC 2016第11期Analog Circuits
A ReRAM Based 4T2R Nonvolatile TCAM Using RC Filtered Stress Decoupled Scheme f
一篇关于使用RC滤波应力解耦方案的4T2R非易失性TCAM的ReRAM研究论文
无
JSSC 2015第8期Analog CircuitsOp-Amp
A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3 Bo Wu, Student Member , IEEE, and Y
40纳米CMOS工艺下实现的可编程带宽带通滤波器，采用新型零电容扩展技术
85-225 MHz中心频率，5%-40%带宽比，31 dBm IIP3，33 mA@1.5V
JSSC 2014第2期Analog CircuitsOp-Amp
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF
一款12mW低功耗连续时间带通ΔΣ调制器，采用新型高效谐振器，实现58dB SNDR和24MHz带宽。
65nm CMOS, 12mW, 58dB SNDR, 24MHz带宽, 800MS/s
JSSC 2014第11期Analog Circuits
A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Ampli fier Linfei Guo
提出一种新型无滤波器D类放大器，具有高PSRR和低THD+N，适用于智能手机和SoC集成。
65nm CMOS, 3.6V, 500mW@8Ω, THD+N 0.0027%, 效率94%, PSRR -101dB@217Hz
JSSC 2014第11期Analog Circuits
Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter Massoud Tohidian, Student Member , IEEE , Iman Madadi , Student Member , IEEE
提出一种基于电荷共享旋转的高阶离散时间无源IIR低通滤波器，支持电压采样和电荷采样模式。
65nm CMOS, 1.2V, 800MS/s, 400kHz-30MHz带宽, 100dB阻带抑制, +21dBm IIP3, 4.57nV/√Hz噪声, 2mW功耗, 0.42mm²面积
JSSC 2014第12期Analog Circuits
Switched-Mode Operational Ampli fiers and Their Application to Continuous-Time Filters in Nanoscale CMOS
提出新型开关模式运算放大器(SMOA)，在65nm CMOS中实现高效低电压连续时间滤波器
65nm CMOS, 0.6V供电, 70MHz带宽, 25.4mW功耗, 55.8dB SNDR
JSSC 2013第6期Analog CircuitsBandgap Reference
1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs Yu j i O s a k i, Member , IEEE,T e t s u y a H i r o s e,M e m b e r ,I E E E
提出一种用于纳瓦级LSI的带隙基准和亚带隙基准电路，无需电阻，仅使用MOSFET和双极晶体管。
1.09V/0.548V参考电压, 100nW/52.5nW功耗
JSSC 2013第7期Analog Circuits
Complementary Constant- Biasing of Nauta-Transconductors in Low-Power – Filters to ±2% Accuracy Over Temperature Richard J. E. Jansen , Member , IEEE, Johan Haanstra, and
设计了一种用于低功耗低频CMOS带通滤波器的Nauta跨导器静态互补恒偏置电路，优化并修调以实现工艺和温度无关的滤波器性能。
180nm CMOS, 2MHz带宽, 中心频率稳定, 120°C温度范围内偏差<2%
JSSC 2013第12期Analog Circuits
Design of Active N-Path Filters
提出一种基于回转器的主动N路径滤波器设计方法，实现宽频带可调谐和高线性度。
65nm LP CMOS, 1.2V, 0.1-1.2GHz可调, 6阶, 2.8dB NF, +25dB增益, +26dBm IIP3
JSSC 2012第2期Analog CircuitsOp-AmpBandgap Reference
A Novel Wide-Temperature-Range, 3.9 ppm/ C CMOS Bandgap Reference Circuit Charalambos M. Andreou , Student Member , IEEE
提出一种新型宽温度范围CMOS带隙基准电路，温度系数低至39 ppm/°C。
3.9 ppm/°C (165°C范围), 13.7 ppm/°C (200°C范围), 0.039% V线性调整率
JSSC 2012第6期Analog CircuitsOp-Amp
Comments and Corrections Correction to “A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS” Mohammad Taherzadeh-Sani and Anas Hamoui In [1, Sec. III-A], paper [2], which presents a similar compensation technique to that presented in [1, Sec. III-A], should have been cited. Manuscript received March 02, 2012; a ccepted March 26, 2012. Date of cur- rent version May 22, 2012. The authors are with the Department of Electrical and Computer Engineering
本文是对先前论文中遗漏引用的修正说明。
JSSC 2012第7期Analog CircuitsOp-Amp
Analysis and Design of a High Speed Continuous-time Modulator Using the Assisted Opamp Technique Ankesh Jain, Muthusubramaniam V enkatesan
采用辅助运放技术设计的高速连续时间调制器，实现1 GS/s采样率和15.625 MHz带宽内的10位分辨率。
0.13μm CMOS, 67 dB动态范围, 4 mW功耗
JSSC 2012第9期Analog CircuitsOp-Amp
A 88-dB DR, 84-dB SNDR V ery Low-Power Single Op-Amp Third-Order Modulator
一种适用于便携式传感器系统的低功耗单运放三阶Σ-Δ调制器
0.18μm CMOS, 1.5V, 3.2MHz时钟, 100kHz带宽, 84dB SNDR, 88dB DR, 140μW功耗
JSSC 2012第11期Analog Circuits
A 0.5-V R-MOSFET-C Filter Design Using Subthreshold R-MOSFET Resistors and OTAs With Cross-Forward Common-Mode
0.5V低功耗高线性度可调谐R-MOSFET-C滤波器设计
0.18μm CMOS, 0.5V, 91-268kHz可调, 61.0dB动态范围, 0.6mW
JSSC 2012第12期Analog CircuitsOp-Amp
Analog Filter Design Using Ring
提出使用环形振荡器积分器设计高性能模拟滤波器，克服传统积分器增益受限问题。
90nm CMOS, 0.5V电源, 2.9mW功耗, 7MHz带宽, 61.4dB SNR, 67.6dB SFDR, 60.1dB THD
JSSC 2011第3期Analog CircuitsOp-Amp
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS Mohammad Taherzadeh-Sani and Anas A. Hamoui
提出一种低电压下工艺不敏感且电流可扩展的两级运放设计，通过伪共源共栅补偿和体偏置技术提升直流增益。
1-V 65-nm CMOS, 直流增益提升4倍（12 dB）, 单位增益频率提升40%, 相位裕度保持稳定
JSSC 2011第4期Analog Circuits
Comments and Corrections Correction to “An IF Bandpass Filter Based on a Low Distortion Transconductor” Ha Le-Thai, Huy-Hieu Nguyen, Hoai-Nam Nguyen, Hong-Soon Cho, Jeong-Seon Lee, and Sang-Gug Lee In the above paper [1], papers [2] and [3] on linearization techniques applying parallel structures should have been included as references. The authors would like to thank Professor A. S. Korotkov for pointing out this missing information. REFERENCES
对两篇论文的参考文献和公式错误进行更正
无
JSSC 2011第5期Analog Circuits
A Biomedical Sensor Interface With a sinc Filter and
一种用于生物医学应用的紧凑型低功耗数字辅助传感器接口，采用过采样和混合信号反馈技术。
0.18μm CMOS, 1.5V, 255nW-2.5μW
JSSC 2011第7期Analog Circuits
Active-RC Filters Using the Gm-Assisted OTA-RC Technique Siva V . Thyagarajan, Student Member , IEEE
提出Gm辅助OTA-RC技术，结合Gm-C和主动RC积分器，提升线性度和速度，同时保持低噪声和功耗。
20 MHz带宽，0.18μm CMOS工艺
JSSC 2011第10期Analog Circuits
Design and Analysis of a Self-Oscillating Class D Audio Amplifier Employing a Hysteretic Comparator
设计并分析了一种采用迟滞比较器的三阶自激振荡D类音频放大器。
0.7μm CMOS, 116.5 dB动态范围, 0.0012% THD+N, 125 mW@8Ω, 84%效率@1W
JSSC 2011第11期Analog CircuitsBandgap Reference
A Single-Trim CMOS Bandgap Reference With a Inaccuracy of 0.15% From 40 C to 125 C
一种仅需单次修调即可在-40°C至125°C范围内实现0.15%精度的CMOS带隙基准源。
0.15% inaccuracy, 55μA@1.8V, 0.12mm²
JSSC 2010第2期Analog Circuits
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications Mohamed Mobarak, Student Member , IEEE , Marvin Onabajo , Student Member , IEEE
提出一种基于衰减预失真线性化技术的CMOS OTA设计，通过数字校正实现高频线性度提升
350MHz带宽下IM3<-74dB, 70dB SNR@1MHz, 5.2mW功耗
JSSC 2010第9期Analog Circuits
Current-Mode, WCDMA Channel Filter With In-Band
提出一种新型管道滤波器，通过带内噪声整形技术实现WCDMA应用中的低噪声和高线性度
32μV带内噪声（2MHz带宽），+36dBm带外IIP3，75dB SFDR，1.25mW功耗
JSSC 2010第11期Analog Circuits
An IF Bandpass Filter Based on a Low Distortion Transconductor Ha Le-Thai, Huy-Hieu Nguyen, Hoai-Nam Nguyen, Hong-Soon Cho, Jeong-Seon Lee
提出一种基于低失真跨导器的IF带通滤波器，通过并行差分结构抵消非线性，实现高线性度和平坦频率响应。
80 MHz带通滤波器，0.1 dB波纹，27 dB三次谐波抑制，IIP3 50dBm，NF 21.5 dB，11 mA@1.2V
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