ISSCC 2017
Session 6
Wireline I/O
A 60Gb/s 288mW NRZ Transceiver with Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65nm CMOS Technology
Qualcomm Atheros, San Jose, CA 1 2 The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decr
ISSCC 2017
Session 27
Medical & Bio
A 2.8µW 80mVpp-Linear-Input-Range 1.6GΩ-Input Impedance Bio-Signal Chopper Amplifier Tolerant to Common-Mode Interference up to 650mVpp
Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to administer therapy in patients suffering from drug-resistant neurological ailments. However, stimulation generates large artifacts at th
ISSCC 2017
Session 26
Digital Processors
A 0.4-to-1V 1MHz-to-2GHz Switched-Capacitor Adiabatic Clock Driver Achieving 55.6% Clock Power Reduction
Clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactanc
ISSCC 2017
Session 24
Wireless
A Time-Interleaved Filtering-by-Aliasing Receiver Front-End with >70dB Suppression at <4×Bandwidth Frequency Offset
Programmable receiver front-ends have been a topic of enormous interest in recent years. Both N-path filtering [1,2] and charge-domain filtering [2] achieve sharp filtering but suffer from poor matching [1] or high noise
ISSCC 2017
Session 21
Digital Processors
2pJ/MAC 14b 8×8 Linear Transform Mixed-Signal Spatial Filter in 65nm CMOS with 84dB Interference Suppression
machine learning (ML) and the internet-of-things (IoT) have resulted in a renewed interest in analog matrix-vector multiplication (MvM) accelerators [1-3]. Classification based tasks have exploited low-to-medium resoluti
ISSCC 2017
Session 20
Digital Circuits
A 100nA-to-2mA Successive-Approximation Digital LDO with PD Compensation and Sub-LSB Duty Control Achieving a 15.1ns Response Time at 0.5V
Modern subthreshold SoC designs feature multiple power domains to dynamically track the maximum energy-efficiency point (0.32-0.45V [1]) in response to application demands. While analog low-drop-out (LDO) regulators have
ISSCC 2017
Session 2
Power Management
A Class-G Voltage-Mode Doherty Power Amplifier
In modern communication, wideband and high-spectral-efficiency modulation results in high peak-to-average power ratio (PAPR), up to 8 to 10dB. Well-known PA-efficiency-enhancement techniques, such as Doherty and outphasi
ISSCC 2017
Session 19
Clocking & PLLs
A 2.4GHz RF Fractional-N Synthesizer with 0.25fREF BW
The loop bandwidth of conventional RF fractional-N synthesizers has been limited to about fREF/10 despite the use of methods that suppress the ΔΣ-modulator quantization noise [1-4]. The trade-off between the loop bandwid
ISSCC 2017
Session 17
Wireline I/O
A 318-to-370GHz Standing-Wave 2D Phased Array in 0.13μm BiCMOS
Fully integrated implementation of mm-wave/THz radiators and phased arrays presents new potentials for applications like spectroscopy, imaging, and high data-rate communication. These applications demand sufficient radia
ISSCC 2016
Session 5
Analog Circuits
A 2µW 40mVpp Linear-Input-Range ChopperStabilized Bio-Signal Amplifier with Boosted Input Impedance of 300MΩ and Electrode-Offset Filtering
Modern neuromodulation requires closed-loop functionality, where neural recordings are used to adapt stimulation patterns in real time. A closed-loop system requires the neural sensing front-end to record small neural si
ISSCC 2016
Session 25
mm-Wave
A 0.43K-Noise-Equivalent-ΔT 100GHz Dicke-Free Radiometer with 100% Time Efficiency in 65nm CMOS
Jet Propulsion Laboratory, Pasadena, CA 1 2 Silicon based mm-Wave radiometers for sensing, passive imaging, and even biomedical imaging have become an emerging area with many excellent systems demonstrated up to W-band [
ISSCC 2016
Session 23
Wireline I/O
A 40Gb/s 14mW CMOS Wireline Receiver
Reaching a power efficiency of 1mW/Gb/s has proven difficult for wireline transceivers operating at tens of gigabits per second. At 40Gb/s, recent receivers consume from 150mW [1] to 1W [2]. This paper describes a receiv
ISSCC 2016
Session 2
RF & Wireless
A 190.5GHz Mode-Switching VCO with 20.7% Continuous Tuning Range and Maximum Power of -2.1dBm in 0.13μm BiCMOS
Wideband mm-Wave and terahertz (THz) applications, including high data-rate communications, high-resolution radar and spectroscopy, require wideband signal sources. Nevertheless, low quality factor of varactors and lossy
ISSCC 2016
Session 13
Wireless
A Microwave Injection-Locking Outphasing Modulator with 30dB Dynamic Range and 22% System Efficiency in 45nm CMOS SOI
University of California, Santa Barbara, CA 1 2 High-capacity microwave systems demand high-efficiency transmit architectures that support complex waveforms with high peak-to-average-power-ratio (PAPR) modulation. The ou
ISSCC 2016
Session 12
Power Management
A Flying-Domain DC-DC Converter Powering a Cortex-M0 Processor with 90.8% Efficiency
Modern SoC designs employed in battery-life-constrained mobile applications feature multiple power domains to dynamically scale power-performance tradeoffs in response to application demands. Since each power domain requ
ISSCC 2015
Session 25
RF & Wireless
A 2.4GHz 4mW Inductorless RF Synthesizer
Recent developments in RF receiver design have eliminated all on-chip inductors except for that used in the local oscillator. This paper addresses this “last inductor” problem and proposes an integer-N synthesizer archit
ISSCC 2015
Session 11
Image Sensors
Integrated Ultrasonic System for Measuring Body-Fat Composition
solution for accurate assessment of body fat is presented that addresses a growing consumer interest in economical and easy-to-use solutions for monitoring personal health and fitness. Unlike the prevalent present soluti
ISSCC 2014
Session 8
Wireline I/O
An 8.2-to-10.3Gb/s Full-Rate Linear Reference-less CDR Without Frequency Detector in 0.18µm CMOS
Broadcom, Irvine, CA 1 2 As an alternative to the conventional dual-loop architecture, reference-less CDR architectures have become more popular in industry because of their simplicity and flexibility [1-5]. However, the
ISSCC 2014
Session 4
Power Management
An 85%-Efficiency Fully Integrated 15-Ratio Recursive Switched-Capacitor DC-DC Converter with 0.1-to-2.2V Output Voltage Range
The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. Dynamic voltage scaling (DVS) can he
ISSCC 2014
Session 27
Digital Circuits
A Multi-Granularity FPGA with Hierarchical Interconnects for Efficient and Flexible Mobile Computing
Following the rapid expansion of mobile computing in the past decade, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy efficiency. An increasi
ISSCC 2014
Session 20
Wireless
A 20mW GSM/WCDMA Receiver with RF Channel Selection
Recent work on RF receivers has exploited N-path filters to address two critical issues, namely, blocker tolerance and high RF selectivity [1,2]. However, these designs face three drawbacks: (1) the low-noise amplifier (
ISSCC 2014
Session 2
Wireline I/O
A 25Gb/s 5.8mW CMOS Equalizer
The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a gr
ISSCC 2014
Session 14
mm-Wave
A 300GHz Frequency Synthesizer with 7.9% Locking Range in 90nm SiGe BiCMOS
University of California, Davis, CA 1 2 The THz/sub-mm-Wave band is known to provide unique applications in spectroscopy, imaging and high-data-rate wireless communication. An accurate THz source is essential in coherent
ISSCC 2013
Session 21
Power Management
A Sub-ns Response Fully Integrated BatteryConnected Switched-Capacitor Voltage Regulator Delivering 0.19W/mm2 at 73% Efficiency
Lithium-ion batteries are the dominant power source in mobile devices. However, while the supply voltage required for processors and SoCs has scaled down to ~1V, the voltage range of this popular battery remains ~2.9V-4.
ISSCC 2013
Session 2
Wireline I/O
A 0.94mW/Gb/s 22Gb/s 2-Tap Partial-Response DFE Receiver in 40nm LP CMOS
A decision-feedback equalizer (DFE) reconstructs the post-cursor inter-symbol interference (ISI) pattern from the detected data sequence and subtracts it from the received signal before detecting the next symbol. Therefo
ISSCC 2013
Session 2
Wireline I/O
A 32-to-48Gb/s Serializing Transmitter Using Multiphase Sampling in 65nm CMOS
Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the
ISSCC 2013
Session 2
Wireline I/O
A 66Gb/s 46mW 3-Tap Decision-Feedback Equalizer in 65nm CMOS
Given the continuously climbing data rates of high-speed I/O’s, equalizer circuits—and particularly decision-feedback equalizer (DFE) designs—are being pushed to operate at ever-higher speeds. At 20 to 40Gb/s data-rates,
ISSCC 2013
Session 19
Wireless
A Digitally Modulated 2.4GHz WLAN Transmitter with Integrated Phase Path and Dynamic Load Modulation in 65nm CMOS
Wi-Fi transmitters (TXs) has been continuously rising, and has hence become increasingly problematic for mobile devices. To extend battery life, the TX must be efficient not only at peak power but also at backoff, due to
ISSCC 2013
Session 16
Medical & Bio
A 37.6mm2 1024-Channel High-Compliance-Voltage SoC for Epiretinal Prostheses
Retinal implants elicit light perception for people blinded by photoreceptor loss. Commercialized 60-channel retinal prostheses allow patients to perform simple tasks, but several hundreds to a thousand electrodes are re
ISSCC 2013
Session 13
Wireless
A Mixed-Signal 32-Coefficient RX-FFE 100Coefficient DFE for an 8Gb/s 60GHz Receiver in 65nm LP CMOS
The 60GHz band has opened the opportunity for multi-Gb/s wireless communications, and is being commercially supported by transceiver solutions utilizing the WirelessHD and/or WiGig standards. However, the hundreds of mWs
ISSCC 2013
Session 13
Wireless
A 50mW-TX 65mW-RX 60GHz 4-Element Phased-Array Transceiver with Integrated Antennas in 65nm CMOS
The 60GHz band has gained great interest as an enabler for multi-Gb/s wireless links. Recent efforts [1-4] have focused on reducing transceiver power to drive adoption of 60GHz in mobile devices. To further accelerate th
ISSCC 2012
Session 16
Power Management
A 92%-Efficiency Wide-Input-Voltage-Range Switched-Capacitor DC-DC Converter
The traditional inductor-based buck converter has been the dominant design for step-down switched-mode voltage regulators for decades. Switched-capacitor (SC) DC-DC converters, on the other hand, have traditionally been
ISSCC 2011
Session 7
Digital Processors
A Direct Digital Frequency Synthesizer with Minimized Tuning Latency of 12ns
A downside for all direct digital synthesizer (DDS) architectures is that every DDS has a phase accumulator (PA) whose normalized phase value φ must be updated for each (sin 2πφ, cos 2πφ) output-pair produced, and such u
ISSCC 2011
Session 24
Other
A Compact 1V 18.6dBm 60GHz Power Amplifier in 65nm CMOS
One of the remaining challenges in implementing CMOS 60GHz radios is to cover longer communication distance as the high path loss at mm-Wave frequencies demands higher EIRP, which in turn requires considerable design eff
ISSCC 2011
Session 17
Medical & Bio
A 0.013mm2 5µW DC-Coupled Neural Signal Acquisition IC with 0.5V Supply
interfaces has provided hope for patients with spinal-cord injuries, Parkinson’s disease, and other debilitating neurological conditions [1], and has boosted interest in electronic recording of cortical signals. State-of
ISSCC 2011
Session 16
mm-Wave
183GHz 13.5mW/Pixel CMOS Regenerative Receiver for mm-Wave Imaging Applications
Terahertz- and mm-Wave-based imagers have recently gained interest for imaging in security screening and bio-imaging applications [1,2]. For these applications to become practical, the core pixel circuits employed in an
ISSCC 2010
Session 8
Wireline I/O
A 20Gb/s 40mW Equalizer in 90nm CMOS Technology
In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transfo
ISSCC 2010
Session 25
Wireless
A 65nm CMOS 2.4GHz 31.5dBm Power Amplifier with a Distributed LC Power-Combining Network and Improved Linearization for WLAN Applications
greatest challenges facing the designers of complex wireless SoCs. Recently, there has been a significant effort to implement PA’s in CMOS [1-4]. The 802.11g standard utilizes OFDM modulation, which has a very high peak-
ISSCC 2010
Session 23
mm-Wave
A High-Gain 60GHz Power Amplifier with 20dBm Output Power in 90nm CMOS
input matching network of the second stage is matched with 50Ω to minimize loss while the output matching network is designed to deliver maximum output power using power contours which were determined by load-pull simula
ISSCC 2010
Session 16
Data Converters
A Mostly Digital Variable-Rate Continuous-Time ADC ΔΣ Modulator
modulator is presented that consists mostly of digital circuitry. It does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a lowjitter clock. Unlike conventional ΔΣ
ISSCC 2009
Session 9
Data Converters
A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction
A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancella
ISSCC 2009
Session 4
Data Converters
A 10b 500MHz 55mW CMOS ADC
Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11b has faced speed limitations with a single channel [1] or employed interleaving, but with a relatively high power
ISSCC 2009
Session 29
mm-Wave
A 26dB-Gain 100GHz Constructive-Wave Amplifier Si/SiGe Cascaded
The availability of W-band (75 to 111GHz) silicon integrated circuits will potentially revolutionize medical and security imaging, as well as high-capacity wireless communications. Traditional W-band circuits rely on GaA
ISSCC 2008
Session 9
mm-Wave
A Broadband Distributed Amplifier with Internal Feedback Providing 660GHz GBW in 90nm CMOS
Wideband circuits find applications in various fields such as highspeed links, broadband radio transceivers, high-resolution radar and imaging systems. Recently, distributed amplifiers (DAs) with large bandwidths have be
ISSCC 2008
Session 9
mm-Wave
A 60GHz CMOS Receiver Using a 30GHz LO
Recent work on receivers for the 60GHz band has considered various frequency plans to ease the design of the building blocks, particularly the local oscillator (LO) and the frequency dividers [1-3]. A natural choice of t
ISSCC 2008
Session 9
mm-Wave
A Robust 24mW 60GHz Receiver in 90nm Standard CMOS
Emerging applications for the 60GHz spectrum include extremely high-data-rate short-range communication systems. Many of these applications are expected to enter the realm of consumer electronics where low cost and mass
ISSCC 2008
Session 6
RF & Wireless
A 1.8Gpulses/s UWB Transmitter in 90nm CMOS
The potential of pulse-based ultra-wideband (UWB) technology has been demonstrated for high-data-rate short-distance wireless personal area networks (e.g., wireless USB) [1-3]. With the allocation of the spectrum from 3.
ISSCC 2008
Session 32
Sensors
A Mode-Matching ΔΣ Closed-Loop VibratoryGyroscope Readout Interface with a 0.004°/s/√Hz Noise Floor over a 50Hz Band
floors, mode matching is necessary to moderate interface power dissipation. Mode matching increases sense displacements by the sense mode quality factor and thereby relaxes the precision requirements of the front-end, bu
ISSCC 2008
Session 31
AI / ML
A 60GHz 1V +12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS
The opening up of the mm-wave band has created opportunities for high-data-rate communication, radar and medical imaging. The cost and size advantages of CMOS have motivated research on 60GHz CMOS front-end design [1]. H
ISSCC 2008
Session 29
Other
A 2GHz 52µW Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF Architecture
A wake-up receiver (WuRx) is used in wireless sensor networks (WSN) to detect wireless traffic directed to a node’s receiver and activate it upon detection, improving network latency and energy dissipation by maximizing