Papers 2008–2026

AMD InstinctTM MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems

An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%

A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion

A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique

A 45.5fs-Integrated-Random-Jitter and -75dBc-IntegerBoundary-Spur BiCMOS Fractional-N PLL with Suppression

A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter

An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM

Fueling Semiconductor Innovation and Entrepreneurship in the Next Decade Lip-Bu Tan

Computing in the Era of Generative AI Jonah Alben AI Will Transform Your Business An important takeaway from how DLSS reshaped NVIDIA’s core business is that AI should not be viewed solely as a revenue opportunity. Instead, believe that it will fundamentally transform the semiconductor industry – and your business.

Racing Down the Slopes of Moore’s Law Bram Nauta

Semiconductor Industry: Present & Future Kevin Zhang Senior Vice President of Business Development & Overseas Operations Office

An In-depth Look at the Intel IPU E2000

NVLink-C2C: A Coherent Off Package Chip-to-Chip Interconnect with 40Gbps/pin Single-ended Signaling

A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor

D1: A 7nm ML Training Processor with Wave Clock Distribution

An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating

A 28GHz Scalable Inter-Core-Shaping Multi-Core Oscillator with DM/CM-Configured Coupling Achieving 193.3dBc/Hz FoM and 205.5dBc/Hz FoMA at 1MHz Offset

A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving −138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz If the frequency mismatch exists in the adjacent cores (f1 = f3 > f2 = f4), a strong coupling (k2) between LG13 and LG24 also helps reduce the output amplitude variation. Consequently, the PN penalty of our dual-path-synchronized oscillator is ~0dB at a 5% frequency mismatch, which is even lower than that of the conventional design (0.2dB).

An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique

CTLE-Ising: A 1440-Spin Continuous-Time Latch-Based Ising Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States

A 22nm Delta-Sigma Computing-In-Memory (∆ΣCIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing

CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction

A 70.85–86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation

A 28nm Horizontal-Weight-Shift and Vertical-Feature-ShiftBased Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks

A 4nm 6163-TOPS/W/b 4790-TOPS/mm2/b SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update disabled, to save power, in 8b mode. The INWIDTH[1:0] bus controls the XIN width: 00 for 8b, 01 for 12b, and 10 for 16b modes. To support a signed format with width flexibility, the first 4 cycles are signed 4b operations and the rest of the cycles are unsigned 4b operations, regardless of INWIDTH.

A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-PointComputing-Unit and Double-Bit 6T-SRAM Computing-inMemory Macro for Floating-Point CNNs

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm the selected FFE setting, with proper shift operations involved. This approach minimizes the area and power overhead for the FFE multiplexing, while still covering a sufficient range of configurations for representative channels.

A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS

A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications one point. VREFPM is set slightly above h0, and VREFPN is set slightly under $h0 for the optimal point. In this work, a single-stage CTLE is implemented for an energy-efficient equalizer, and the second lock option is chosen.

A 37.8dB Channel Loss 0.6µs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques

A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS

A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET detection can either use a low-latency short FFE to minimize peaking in the jitter transfer curve or use the main FFE/DFE output for very high loss channels (> 40dB).

A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology

Dual-Port CMOS Image Sensor with Regression-Based HDR Flux-to-Digital Conversion and 80ns Rapid-Update Pixel-Wise Exposure Coding

55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes

A 400×200 600fps 117.7dB-DR SPAD X-Ray Detector with Seamless Global Shutter and Time-Encoded Extrapolation Counter

A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS Image Sensor with 73dB Dynamic Range

A 0.64µm 4-Photodiode 1.28µm 50Mpixel CMOS Image Sensor with 0.98e- Temporal Noise and 20Ke- Full-Well Capacity Employing Quarter-Ring Source-Follower

A 2.97µm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and Low-Noise Intensity Readout Mode

µm 35.6Mpixel RGB Hybrid Event-Based Vision Sensor with 4.88µm-Pitch Event Pixels and up to 10K Event Frame Rate by Adaptive Control on Event Sparsity

A 3-Wafer-Stacked Hybrid 15MPixel CIS + 1MPixel EVS with

A 0.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms

A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth

A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration constructed DAC voltage (VDAC) is shaped with a high slope (SDAC) in the gain-boosted PD, a high SDAC is achieved by generating a slope on VDAC in the gain-boosted PD, and the DTC delay is used to compensate for the timing error from CLKFB to the voltage crossing.

A 76.7fs-Integrated-Jitter and -71.9dBc In-Band FractionalSpur Bang-Bang Digital PLL Based on an Inverse-ConstantSlope DTC and FCW Subtractive Dithering

A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier