ISSCC 2024
Session 8
Power Management
A 92.7% Peak Efficiency 12V-to-60V Input to 1.2V Output Hybrid DC-DC Converter Based on a Series-Parallel-Connected Switched Capacitor
automotive applications for a higher efficiency power system. Accordingly, an ultra-low voltage-conversion-ratio (VCR) buck converter is in great demand. Previous ultra-low VCR buck converters use flying capacitors (CFs) a
ISSCC 2024
Session 8
Power Management
An Integrated Dual-side Series/Parallel Piezoelectric Resonator-based 20-to-2.2V DC-DC Converter Achieving a 310% Loss Reduction
CEA-Léti, Grenoble, France 1 2 Piezoelectric resonators (PRs) have recently emerged as an attractive substitute for inductors to process energy in DC-DC converters, due to their low-volume planar formfactors, superior vo
ISSCC 2024
Session 8
Power Management
A Fast-Transient 3-Fine-Level Buck-Boost Hybrid DC-DC Converter with Half-Voltage-Stress on All Switches and 98.2% Peak Efficiency
Southern University of Science and Technology, Shenzhen, China 1 Figure 8.4.3 exhibits the overall structure of the proposed buck-boost converter including the power stage and control stage. All circuits are implemented
ISSCC 2024
Session 8
Power Management
A Li-ion-Battery-Input 1-to-6V-Output Bootstrap-Free Hybrid Buck-or-Boost Converter Without RHP Zero Achieving 97.3% Peak Efficiency 6μs Recovery Time and 1.13μs/V DVS Rate
today’s mobile devices, buck-boost converters are widely used to convert the Li-ion battery voltage (VIN), typically ranging from 2.7 to 4.2V, to the specific output voltage (VO) levels required by various modules. While
ISSCC 2024
Session 8
Power Management
A 96.9%-Peak-Efficiency Bilaterally-Symmetrical Hybrid Buck-Boost Converter Featuring Seamless Single-Mode
use batteries. It works by regulating the output voltage (VO = 3.4V) with a specific voltage conversion ratio (M = VO/VIN), given a supplied voltage (VIN = 2.7 ~ 4.2V) that fluctuates based on the battery’s state-of-charge
ISSCC 2024
Session 8
Power Management
A 48V-to-5V Buck Converter with Triple EMI Suppression Circuit Meeting CISPR 25 Automotive Standards existing at VSW can be largely suppressed, which reduces high-frequency EMI amplitude (bottom right of Fig. 8.11.2).
Rong-Bin Guo1, Hsing-Yen Tsai1, Ke-Horng Chen1, Kuo-Lin Zeng1,2, Ying-Hsi Lin3, Shian-Ru Lin3, Tsung-Yen Tsai3 1 1 1 1 National Yang Ming Chiao Tung University, Hsinchu, Taiwan Chip-GaN Power Semiconductor, Hsinchu, Taiw
ISSCC 2024
Session 8
Power Management
A 5V-to-150V Input-Parallel Output-Series Hybrid DC-DC Boost Converter Achieving 76.4mW/mg Power Density and 80% Peak Efficiency
essential for biomedical, optics, sensing and diagnostics applications. For realizing an ultrahigh VCR, the conventional boost converter would result in a large duty ratio D, a large inductor current IL and thus a signifi
ISSCC 2024
Session 8
Power Management
A 94.5%-Peak-Efficiency 3.99W/mm2-Power-Density Single-Inductor Bipolar-Output Converter with a Concise PWM Control for AMOLED Displays
Hefei CLT Microelectronics, Hefei, China *Equally Credited Authors (ECAs) 1 2 DC-DC converters with bipolar outputs are widely used to drive AMOLED displays in battery-powered electronic devices. To prolong the battery l
ISSCC 2024
Session 7
Wireline I/O
An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process receiving injections. Further, the quadrature outputs from the 4-phase signals from the RO are edge-combined using an XOR gate to produce differential outputs with twice the RO frequency as shown in Fig. 7.9.2.
capacitor current based on the differential input clocks to generate differential ramp signals. The internal loop within the replica bias sets the DC level of the ramp signal. To ensure the ramp’s linearity across proces
ISSCC 2024
Session 7
Wireline I/O
A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise
Ahmed E. Abdelrahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu University of Illinois, Urbana, IL A low-jitter multi-phase clock generator is pivotal in high-speed serial link transceivers. With data rates surpas
ISSCC 2024
Session 7
Wireline I/O
A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS
serializer-deserializer (SerDes) transceivers for >100Gb/s data rates have been developed in recent years [1-4]. Differing from the medium-reach (MR) or long-reach (LR) applications, the XSR TRX targets <50mm traces for
ISSCC 2024
Session 7
Wireline I/O
A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS
computing and artificial intelligence applications pushes wireline transceivers to higher data rates. DSP-based transmitters (TX) and receivers (RX) have achieved 224Gb/s [1-2], but unfortunately consume substantial power
ISSCC 2024
Session 7
Wireline I/O
A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE
Taiyang Fan1, Hongchang Qiao1, Wentao Zhou1, Hongzhi Wu1, Liping Zhong1, Patrick Yin Chiang2, Quan Pan1 Southern University of Science and Technology, Shenzhen, China Fudan University, Shanghai, China 1 2 With the expone
ISSCC 2024
Session 7
Wireline I/O
A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and −74.2dBc Reference Spur
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 A ring oscillator (RO) based phase-locked loop (PLL) is a promising
ISSCC 2024
Session 7
Wireline I/O
A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS
Mohammad-Mahdi Mohsenpour1, Marc-Andre LaCroix1, Babak Zamanlooy3, Tom Eeckelaert1, Dmitry Petrov1, Mostafa Haroun1, Carson Dick2, Alif Zaman1, Haitao Mei1, Shahab Moazzeni1, Tahseen Shakir1, Carlos Carvalho1, Howard Hua
ISSCC 2024
Session 7
Wireline I/O
A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET
Dovid Gottesman1, Daljeet Kumar2, Zvi Marcus1, Yeshayahu Horwitz1, Sagi Zalcman1, Jihwan Kim3, Sandipan Kundu3, Ilia Radashkevich1, Yoav Segal1, Dror Lazar1, Udi Virobnik1, Mike Peng Li4, Ariel Cohen1 Intel, Jerusalem, I
ISSCC 2024
Session 7
Wireline I/O
A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET
C. Loi4, C. R. Ho1, D. Cartina5, J. Riani1, J. Casanova1, K. Raviprakash1, L. Patra1, L. Wang1, M. Bachu1, S. Ray1, S. Chong4, S. Dallaire3, T. Nguyen1, T.-F. Wu2, V. Giridharan1, V. Gurumoorthy1, X. Ding4, Y. Yin1, Z. S
ISSCC 2024
Session 6
AI / ML
A 0.35V 0.367TOPS/W Image Sensor with 3-Layer Optical-Electronic Hybrid Convolutional Neural Network
relies on image sensors coupled with cloud processing or on-chip Artificial Intelligence (AI) processors have encountered significant challenges in terms of power consumption, delays arising from data transmission, and/or
ISSCC 2024
Session 6
Image Sensors
A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR
Position/Width Converter, and Intensity/CNN-Guided 3D Inpainting Chaorui Zou1, Yaozhong Ou1, Yan Zhu1, R. P. Martins1,2, Chi-Hang Chan1, Minglei Zhang1 University of Macau, Macau, China Instituto Superior Tecnico/Univers
ISSCC 2024
Session 6
Image Sensors
A 160×120 Flash LiDAR Sensor with Fully Analog-Assisted InPixel Histogramming TDC Based on Self-Referenced SAR ADC
surrounding objects plays a crucial role in realizing the metaverse and spatial computing on mobile devices. A LiDAR sensor based on direct time-of-flight (dToF) technology is one of the strong candidates to provide depth
ISSCC 2024
Session 6
Image Sensors
Withdrawn by ISSCC 110 • 2024 IEEE International Solid-State Circuits Conference 979-8-3503-0620-0/24/$31.00 ©2024 IEEE ISSCC 2024 / February 19, 2024 / 3:35 PM 6 DIGEST OF TECHNICAL PAPERS • 111
ISSCC 2024
Session 6
Image Sensors
A 0.5°-Resolution Hybrid Dual-Band Ultrasound Imaging SoC for UAV Applications
rate (more pronounced for closer objects) and enhanced image clarity (Fig. 6.5.3(d)). Jiaqi Guo1, Junwei Feng1, Silin Chen1, Liuhao Wu1, Chne-Wuen Tsai1,2, Yingna Huang1, Bochi Lin1, Jerald Yoo1,2 To feed sufficient power
ISSCC 2024
Session 6
Image Sensors
A Resonant High-Voltage Pulser for Battery-Powered Ultrasound Devices
patch are promising for next-generation health monitoring. They have the potential to enable impactful applications such as blood-pressure, cardiac, bladder, and respiratory monitoring. Research in this area to date has
ISSCC 2024
Session 6
Image Sensors
Imager with In-Sensor Event Detection and Morphological Transformations with 2.9pJ/pixel×frame Object Segmentation FOM for Always-On Surveillance in 40nm
Relentless power reductions in always-on untethered imagers for distributed vision are required to fit the power budgets available from their tightly constrained energy sources. As an effective approach to reduce power, e
ISSCC 2024
Session 6
Image Sensors
An Ultrasound-Powering TX with a Global Charge-Redistribution Adiabatic Drive Achieving 69% Power Reduction and 53° Maximum Beam Steering Angle for Implantable Applications
Robert Ukropec3, Pieter Gijsenbergh3, Veronique Rochus3, Nick Van Helleputte3, Wouter Serdijn2, Yao-Hong Liu1,2 imec, Eindhoven, The Netherlands Delft University of Technology, Delft, The Netherlands 3 imec, Leuven, Belg
ISSCC 2024
Session 6
Image Sensors
A 320x240 CMOS LiDAR Sensor with 6-Transistor nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogram Memory
Credited Authors (ECAs) 1 2 Light detection and ranging (LiDAR) systems measure distance with high depth resolution while providing images with the shape of objects. For long-range detection, emitting a concentrated lase
ISSCC 2024
Session 6
Image Sensors
A 1/1.56-inch 50Mpixel CMOS Image Sensor with 0.5μm pitch Quad Photodiode Separated by Front Deep Trench Isolation
Taehoon Kim, Seungju Seo, Dongmo Im, You-Na Lee, Jinyong Choi, Sunghyun Yoon, Inho Noh, Jinhyung Kim, Khang June Lee, Hyesung Jung, Jongyoon Shin, Hyuk Hur, Kyoung eun Chang, Incheol Cho, Kieyoung Woo, Byung Seok Moon, J
ISSCC 2024
Session 6
Image Sensors
12Mb/s 4×4 Ultrasound MIMO Relay with Wireless Power and Communication for Neural Interfaces
Neural interfaces, including retinal and brain implants, require increasing postcompression uplink data rates >10Mb/s to send data from larger and denser recording arrays. In retinal implants, electrical recording data f
ISSCC 2024
Session 5
Wireless
A Stacking Mixer-First Receiver Achieving >20dBm Adjacent-Channel IIP3 Consuming less than 25mW
The sub-6GHz spectrum is used by many standards including 5G New Radio. In this crowded spectrum, an RX requires good linearity and flexibility to address different bands without separate SAW filters, whilst maintaining lo
ISSCC 2024
Session 5
Wireless
A 22.4-to-30.7GHz Phased-Array Receiver with Beam-Pattern Null-Steering and Beam-Tracking Techniques Achieving >30.2dB OTA-Tested Spatial Rejection
environments often suffer from spatially diversified interference, which leads to saturation and non-linear distortion in the RXs. One commonly used approach to mitigate this issue is the application of sidelobe suppressi
ISSCC 2024
Session 5
Wireless
A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS
Conventional wireless receivers employing a heterodyne/homodyne architecture or Npath filter often result in a significantly higher area and power overhead owing to the requirement of LO generation and distribution at high
ISSCC 2024
Session 5
Wireless
-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving +14/+16.5dBm 3rd/5th IB Harmonic B1dB
Widely tunable and reconfigurable receivers are heavily in demand both for highperformance and low-power applications such as 5G New Radio and IoT. One of the crucial features required for a widely tunable RX is the abili
ISSCC 2024
Session 5
Wireless
A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression
Agile multi-functional RF systems supporting multiple communication and radar protocols are of greater demand in modern wireless applications. The core of these systems is the transceiver IC that covers an ultra-wide fre
ISSCC 2024
Session 4
RF & Wireless
A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection
technologies, it is desirable to completely digitize the transmitter, which yields reduced die area, highly efficient operation and direct interface to digital baseband. However, the ever-increasing data demand with compl
ISSCC 2024
Session 4
RF & Wireless
A 43mm2 Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 4×4 MIMO with 1K-QAM
Kyunghyun Yoon, Taejong Kim, Jiyoung Lee, Myunghun Lee, Jaeseung Lee, Jongmin Jeong, Sungjun Lee, Taewan Kim, Sungjoo Kim, Gwangsik Cho, Duksoo Kim, Sangyun Lee, Pilsung Jang, Euibong Yang, Jeongmin Song, Gwangchun Park,
ISSCC 2024
Session 4
RF & Wireless
A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal
Beomyu Park, Jeongkyun Woo, Jaeeun Jang, Inhyo Ryu, Honggul Han, Jaeyoung Kim, Byoungjoong Kang, Minchul Kang, Hojung Kang, John Kang, Minseob Lee, Danbi Lee, Hyeonuk Son, Suhyeon Lee, Soyeon Kim, Hongjong Park, Sangsung
ISSCC 2024
Session 4
RF & Wireless
A 79.7µW Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS
Håkon A. Hjortland1, Lieuwe Leene1, Torleif Skår1, Espen Stenersen1, Dag T. Wisland1,2 Novelda, Oslo, Norway University of Oslo, Oslo, Norway 1 2 In recent years ultra-wideband (UWB) radios have found increasing use in a
ISSCC 2024
Session 34
AI / ML
A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process
Wang Ye1,2, Hongyang Hu1, Jing Liu1, Jinshan Yue1, Jianguo Yang1, Qing Luo1, Chunmeng Dou1,2, Qi Liu1,3, Ming Liu1,3 Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China University of Chinese
ISSCC 2024
Session 34
AI / ML
A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices
Zhao-En Ke1, Yu-Hsiang Chin1, Hua-Jin Wen1, Yu-Chen Chang1, Wei-Ting Hsu1, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Shih-Hsin Teng3, Chung-Cheng Chou3, Yu-Der Chih3, Tsung-Yung Jonathan Chang3,
ISSCC 2024
Session 34
AI / ML
A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing
Yaolei Li1, Zongle Huang1, Zhike Du1, Jinshan Yue2, Xueqing Li1, Huazhong Yang1, Hongyang Jia1, Yongpan Liu1 Tsinghua University, Beijing, China Chinese Academy of Sciences, Beijing, China 1 2 Digital computing-in-memory
ISSCC 2024
Session 34
AI / ML
A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC
Qirui Chen3, Meini Tang3, Xi Wei3, Zhixian Hou3, Jialiang Zhu1,2, Hao Wu1,2, Qirui Ren1,2, Guozhong Xing1, Pui-In Mak4, Feng Zhang1 Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China Univers
ISSCC 2024
Session 34
AI / ML
A 818-4094TOPS/W Capacitor-Reconfigured CIM Macro for Unified Acceleration of CNNs and Transformers Kentaro Yoshioka
In the rapidly evolving landscape of machine learning, workloads using diverse neuralnetwork architectures must be covered: including CNNs for image processing, transformers for natural language processing (NLP), and hyb
ISSCC 2024
Session 34
AI / ML
A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell
Cheng-En Lee1, Xiaochen Peng2, Vineet Joshi3, Chao-Kai Chuang1, Shu-Huan Hsu1, Takeshi Hashizume4, Toshiaki Naganuma4, Chen-Hung Tien1, Yao-Yi Liu1, Yen-Chien Lai1, Chia-Fu Lee1, Tan-Li Chou1, Kerem Akarvardar2, Saman Ad
ISSCC 2024
Session 34
AI / ML
A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs
Yuanpeng Zhang2, Jingmin Zhang1, Yuchen Tang1, Zhican Zhang1, Gang Chen3, Dawei Yang3, Zhaoyang Zhang1, Lizheng Ren1, Tianzhu Xiong1, Bo Wang1, Bo Liu1, Weiwei Shan1, Xinning Liu1, Hao Cai1, Guangyu Sun2, Jun Yang1, Xin
ISSCC 2024
Session 34
AI / ML
A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-CellComputing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices
Zhao-En Ke2, Ting-Chien Chiu2, Jun-Ming Hsu2, Chiao-Yen Cheng2, Yu-Chen Chen2, Chung-Chuan Lo2, Ren-Shuo Liu2, Chih-Cheng Hsieh2, Kea-Tiong Tang2, Meng-Fan Chang1,2 TSMC Corporate Research, Hsinchu, Taiwan National Tsing
ISSCC 2024
Session 34
AI / ML
A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications and denotes early 01 or 10 change. It uses XOR and a leading-one detector if RA/RB with different signs. BRPU reduces the regime processing energy by 68%.
Zhiheng Yue1, Huiming Han1, Shaojun Wei1, Yang Hu1, Shouyi Yin1,2 Figure 34.1.4 depicts the CPCS, increasing the CIM array utilization. The CPCS CIM core consists of an 8×48 CIM array, a load controller, a critical-bit c
ISSCC 2024
Session 33
AI / ML
A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend
Meta, Santa Clara, CA 3 Michigan State University, East Lansing, MI 1 2 Neural interface implants are revolutionizing neuroscience research, especially in brainmachine interfaces and neuromodulation therapies. Miniaturiz
ISSCC 2024
Session 33
AI / ML
A Two-Electrode Bio-Impedance Readout IC with ComplexDomain Noise-Correlated Baseline Cancellation Supporting Sinusoidal Excitation
As the demand for daily monitoring of physiological signals increases, the trend towards minimizing the size of devices through a two-electrode configuration has emerged as a new standard for wearable impedance monitoring
ISSCC 2024
Session 33
AI / ML
An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface with On-Chip Application Tunable Time-Domain Feature Extraction
Sanghyeon Cho, Yonggi Kim, Taejung Kim, Jong-Hyun Kwak, Geonjun Choi, Yoonsik Lee, Heungjoo Shin, Hoon Eui Jeong, Jae Joon Kim Ulsan National Institute of Science and Technology, Ulsan, Korea *Equally Credited Authors (E
ISSCC 2024
Session 33
AI / ML
A Millimetric Batteryless Biosensing and Stimulating Implant with Magnetoelectric Power Transfer and 0.9pJ/b PWM Backscatter
Joshua Woods, Wei Wang, Jacob T. Robinson, Kaiyuan Yang Rice University, Houston, TX *Equally Credited Authors (ECAs) Bioelectronic implants transform clinical therapies by offering unprecedented tools for precise sensin