全部论文

Papers 2008–2026

共 3875 篇 ISSCC 论文，按年份倒序排列

年份 Year
2026 2472025 2422024 2222023 2002022 1672021 1952020 2022019 1812018 2052017 2082016 2002015 1912014 2032013 2102012 1882011 1962010 2102009 1802008 228
领域 Topic
RF & Wireless 362Power Management 302Wireline I/O 300Wireless 293Data Converters 279Digital Processors 268Memory 266AI / ML 231Digital Circuits 220Medical & Bio 211Image Sensors 184Analog Circuits 169mm-Wave 138Clocking & PLLs 127Sensors 100Plenary 63Hardware Security 36Quantum & Photonics 29Industry Highlights 7
顶级机构
University of California 101Delft University of Technology 73University of Macau 58KAIST 51Massachusetts Institute of Tec 48Tsinghua University 39National Taiwan University 38University of Michigan 37Georgia Institute of Technolog 35Columbia University 28Hong Kong University of Scienc 24MediaTek 23
ISSCC 2021 Session 32 Clocking & PLLs
A 14nm Analog Sampling Fractional-N PLL with a Digital-toTime Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels
Wanghua Wu1, Chih-Wei Yao1, Chengkai Guo1, Pei-Yuan Chiang1,
requires sub-100fs rms jitter to support 64-QAM and 2×2 MIMO under non-ideal channel conditions [1]. Although fractional-N phaselocked loops (PLLs) employing digital-to-time converters (DTCs) and sampling phase detectors
Pak-Kim Lau1, Lei Chen1, Sang Won Son1, Thomas Byunghak Cho2 Samsung S
ISSCC 2021 Session 32 Clocking & PLLs
A 365fsrms-Jitter and −63dBc-Fractional Spur 5.3GHz-RingDCO-Based Fractional-N DPLL Using a DTC Second/ThirdOrder Nonlinearity Cancelation and a Probability-DensityShaping ΔΣM
Hangi Park*1, Chanwoong Hwang*1, Taeho Seong*1,2, Yongsun Lee3, Jaehyouk Choi1
data-rates by combining more carrier components, 5G RF transceivers require many carrier frequencies, resulting in the situation of many LC PLLs occupying a large silicon area. Ring-oscillator-based digital PLLs (RO-DPLL
KAIST, Daejeon, Korea Ulsan National Institute of Science and Technolo
ISSCC 2021 Session 31 Analog Circuits
A Chopper-Stabilized Amplifier with -107dB IMD and 28dB Suppression of Chopper-Induced IMD
Thije Rooijers1, Shoubhik Karmakar1, Yoshinori Kusuda2, Johan H. Huijsing1, Kofi A. A. Makinwa1
low-frequency noise. However, the interaction between the input signal and the chopper clock can cause chopper-induced intermodulation distortion (IMD) [1-5]. This is especially problematic for input frequencies (Fin) ne
Delft University of Technology, Delft, The Netherlands Analog Devices,
ISSCC 2021 Session 31 Analog Circuits
A 0.14mm2 16MHz CMOS RC Frequency Reference with a 1-Point Trimmed Inaccuracy of ±400ppm from −45°C to 85°C
Hui Jiang, Sining Pan, Çağrı Gürleyük, Kofi A. A. Makinwa
Recently, rapid strides have been made in improving the accuracy of RC-based frequency references [1-3]. Inaccuracies better than ±500ppm from -45°C to 85°C have been achieved, but typically at the expense of a costly an
Delft University of Technology, Delft, The Netherlands
ISSCC 2021 Session 31 Analog Circuits
A 0.9V 28MHz Dual-RC Frequency Reference with 5pJ/Cycle and ±200ppm Inaccuracy from -40°C to 85°C
Woojun Choi1, Jan A. Angevare2, Injun Park1, Kofi A. A. Makinwa2, Youngcheol Chae1
applications require a stable on-chip frequency reference with low energy (<10pJ/cycle) and high frequency stability (below ±300ppm). CMOS RC frequency references are promising due to their low-cost integration and high
Yonsei University, Seoul, Korea Delft University of Technology, Delft,
ISSCC 2021 Session 31 Analog Circuits
An 82mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% Efficiency
Atsushi Matamura1, Naoaki Nishimura1, Preston Birdsong2,
(ANC) headphones require low-latency digital-input headphone drivers that consume the lowest possible power to maximize battery life while providing high-fidelity audio playback. Typical headphone drivers use Class-A/AB
Abhishek Bandyopadhyay2, Adam Spirer2, Mariana Markova2, Shaolong Liu2
ISSCC 2021 Session 30 Memory
A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology
Tsutomu Higuchi1, Takuyo Kodama1, Koji Kato1, Ryo Fukuda1, Naoya Tokiwa1,
Mitsuhiro Abe1, Teruo Takagiwa1, Yuki Shimizu1, Junji Musha1, Katsuaki Sakurai1, Jumpei Sato1, Tetsuaki Utsumi1, Kazuhide Yoneya1, Yasuhiro Suematsu1, Toshifumi Hashimoto1, Takeshi Hioka1, Kosuke Yanagidaira1, Masatsugu
ISSCC 2021 Session 30 Memory
A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface
Jiho Cho, D. Chris Kang, Jongyeol Park, Sang-Wan Nam, Jung-Ho Song,
Bong-Kil Jung, Jaedoeg Lyu, Hogil Lee, Won-Tae Kim, Hongsoo Jeon, Sunghoon Kim, In-Mo Kim, Jae-Ick Son, Kyoungtae Kang, Sang-Won Shim, JongChul Park, Eungsuk Lee, Kyung-Min Kang, Sang-Won Park, Jaeyun Lee, Seung Hyun Moo
ISSCC 2021 Session 30 Memory
A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density
Ali Khakifirooz1, Sriram Balasubrahmanyam2, Richard Fastow1,
Kristopher H. Gaewsky2, Chang Wan Ha1, Rezaul Haque2, Owen W. Jungroth2, Steven Law1, Aliasgar S. Madraswala2, Binh Ngo2, Naveen Prabhu V2, Shantanu Rajwade1, Karthikeyan Ramamurthi2, Rohit S. Shenoy1, Jacqueline Snyder2
ISSCC 2021 Session 30 Memory
A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture
Jae-Woo Park, Doogon Kim, Sunghwa Ok, Jaebeom Park, Taeheui Kwon,
Hyunsoo Lee, Sungmook Lim, Sun-Young Jung, Hyeongjin Choi, Taikyu Kang, Gwan Park, Chul-Woo Yang, Jeong-Gil Choi, Gwihan Ko, Jaehyeon Shin, Ingon Yang, Junghoon Nam, Hyeokchan Sohn, Seok-In Hong, Yohan Jeong, Sung-Wook C
ISSCC 2021 Session 3 Digital Processors
Kunlun: A 14nm High-Performance AI Processor for Diversified Workloads
Jian Ouyang, Xueliang Du, Yin Ma, Jiaqiang Liu
In order to be able to handle a wide range of AI applications, such as for speech, image, language and autonomous driving, it is necessary that an AI accelerator be flexible enough to handle diversified workloads. Baidu
Baidu, Beijing, China
ISSCC 2021 Session 3 Digital Processors
The A100 Datacenter GPU and Ampere Architecture
Jack Choquette, Edward Lee, Ronny Krashinsky, Vishnu Balan, Brucek Khailany
Nvidia, Santa Clara, CA The diversity of compute-intensive applications in modern cloud data centers has driven the explosion of GPU-accelerated cloud computing. Such applications include AI deep learning training and in
ISSCC 2021 Session 3 Digital Processors
XBOX Series X: A Next-Generation Gaming Console SoC
Paul Paternoster1, Andy Maki2, Andres Hernandez2, Mark Grossman1,
improvement over the prior generation with up to 2× GPU performance, 3× CPU performance, 2.4× GPU performance/W, 1.7× memory bandwidth and 2× IO bandwidth to feed the additional processing capability and features shown i
Michael Lau1, David Sutherland2, Aditya Mathad3 Microsoft, Sunnyvale,
ISSCC 2021 Session 29 Digital Circuits
115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU
Xiaomin Li1, Yibo Xu1,2, Lizheng Ren1, Weiwei Ge1,2, Jianlong Cai1, Xinning Liu1,2,
applications require ultra-low power consumption. In a conventional design, most modules except the crystal oscillator (XO32), real-time clock (RTC), and retention memory are turned off to reduce the current in sleep sta
Jun Yang1,2 Nanjing Low Power IC Technology Institute, Nanjing, China
ISSCC 2021 Session 29 Digital Circuits
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS
Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe
University of Washington, Seattle, WA Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (Vdd) domains in SoCs. With efficiencies approaching those o
ISSCC 2021 Session 29 Digital Circuits
A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS
Dong-Hoon Jung, Tae-Hwang Kong, Jun-Hyeok Yang, SangHo Kim,
microprocessors for applications such as HPC and AI, the available power is strictly limited by the thermal power budget. To overcome this limitation, recently, each core has been implemented with a dedicated integrated
Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin Samsung Electr
ISSCC 2021 Session 29 Digital Circuits
A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration
Chun-Yu Lin, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin
A compact, low-power, low-jitter clock system supporting multiple output frequencies is required in many applications. Using several PLLs to generate multiple frequencies consumes large power and chip area [1]. Alternati
National Taiwan University, Taipei, Taiwan
ISSCC 2021 Session 29 Digital Circuits
A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur
Qiaochu Zhang1, Shiyu Su1, Cheng-Ru Ho2, Mike Shuo-Wei Chen1
Inphi, Santa Clara, CA 1 2 Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scalingfriendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has bee
University of Southern California, Los Angeles, CA
ISSCC 2021 Session 29 Digital Circuits
80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with SelfReferenced Asynchronous Adaptive Droop Mitigation
Praveen Mosalikanti, Qi Wang, Kuan-Yueh James Shen, Mark Neidengard,
4-to-6.5GHz Frequency Locked Loop (FLL) implemented in 10nm CMOS, targeting high performance SoCs that require uninterrupted, overshoot-free clocks for Dynamic Voltage and Frequency Scaling (DVFS). The FLL supports gradu
Syed Feruz Syed Farooq, Vaughn Grossnickle, Nasser Kurd Intel, Portlan
ISSCC 2021 Session 29 Digital Circuits
A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method
Junjie Mu1, Bongjin Kim1,2
now with University of California, Santa Barbara, CA 1 2 Partial differential equations (PDEs) are ubiquitous in physics and engineering and used for understanding various physical phenomena, including heat, diffusion, f
Nanyang Technological University, Singapore, Singapore
ISSCC 2021 Session 29 Digital Circuits
A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Computein-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification
Jong-Hyeok Yoon1, Muya Chang1, Win-San Khwa2, Yu-Der Chih3,
memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) h
Meng-Fan Chang2, Arijit Raychowdhury1 Georgia Institute of Technology,
ISSCC 2021 Session 28 Medical & Bio
Multi-Modal Peripheral Nerve Active Probe and Microstimulator with On-Chip Dual-Coil Power/Data Transmission and 64 2nd-Order Opamp-Less ΔΣ ADCs
Maged ElAnsary, Jianxiong Xu, José Sales Filho, Gairik Dutta, Liam Long,
Aly Shoukry, Camilo Tejeiro, Chenxi Tang, Enver Kilinc, Jaimin Joshi, Parisa Sabetian, Samantha Unger, José Zariffa, Paul Yoo, Roman Genov University of Toronto, Toronto, Canada The peripheral nervous system (PNS) enable
ISSCC 2021 Session 28 Medical & Bio
A 0.00378mm2 Scalable Neural Recording Front-End for Fully Immersible Neural Probes Based on a Two-Step Incremental Delta-Sigma Converter with Extended Counting and Hardware Reuse
Daniel Wendler1, Daniel De Dorigo1, Mohammad Amayreh2, Alexander Bleitner1,
of electronics into tissue-penetrating probes improves the signal quality and reduces parasitic effects for high-density recording of in vivo neural activity. In contrast to passive neural probes or devices implementing
Maximilian Marx1, Yiannos Manoli1,2 University of Freiburg - IMTEK, Fr
ISSCC 2021 Session 28 Medical & Bio
A 22.6µW Biopotential Amplifier with Adaptive Common-Mode Interference Cancelation Achieving Total-CMRR of 104dB and CMI Tolerance of 15Vpp in 0.18µm CMOS
Nahmil Koo1, Hyojun Kim2, SeongHwan Cho1
Korea Aerospace Research Institute, Daejeon, Korea 1 2 Improving robustness to common-mode interference (CMI) is imperative for reliable two-electrode ECG recording. CMI degrades the signal quality in two ways. First, it
KAIST, Daejeon, Korea
ISSCC 2021 Session 28 Medical & Bio
A 0.6V/0.9V 26.6-to-119.3µW ΔΣ-Based Bio-Impedance Readout IC with 101.9dB SNR and <0.1Hz 1/f Corner
Tantan Zhang*1, Hyunwoo Son*1, Yuan Gao1, Jingjing Lan1, Chun-Huat Heng2
National University of Singapore, Singapore 1 2 *Equally-Credited Authors (ECAs) Bio-impedance (BioZ) is an important physiological parameter in wearable healthcare sensing. Besides the inherent cardiac and respiratory i
Institute of Microelectronics, A*STAR, Singapore
ISSCC 2021 Session 28 Medical & Bio
A 400mVpp 92.3dB-SNDR 1kHz-BW 2nd-Order VCO-Based ExG-to-Digital Front-End Using a Multiphase Gated-Inverted Ring-Oscillator Quantizer
Corentin Pochet, Jiannan Huang, Patrick P. Mercier, Drew A. Hall
Next-generation wearable devices will enable clinical-grade, continuous ExG (ECG, EEG, EMG, etc.) biopotential monitoring, providing medical professionals with valuable longitudinal data outside of hospital settings. The
University of California, San Diego, CA
ISSCC 2021 Session 28 Medical & Bio
A 28µW 134dB DR 2nd-Order Noise-Shaping Slope Light-to-Digital Converter for Chest PPG Monitoring 200µA. Since the DC-compensation information is available in the digital domain, the full-range signal can easily be reconstructed to derive the PI and blood oxygenation levels.
Qiuyang Lin1,2, Shuang Song1, Roland Van Wegberg3, Mario Konijnenburg3,
Dwaipayan Biswas1, Chris Van Hoof1,2, Filip Tavernier2, Nick Van Helleputte1 Figure 28.3.3 (right) shows the circuit implementation of the capacitor bank and the 3-T comparator within the NS loop. Since the input is a 10
ISSCC 2021 Session 28 Medical & Bio
A 400-to-1000nm 24µW Monolithic PPG Sensor with 0.3A/W Spectral Responsivity for Miniature Wearables
Sung-jin Jung, Jeil Ryu, Wanghyun Kim, Seunghoon Lee, Jongboo Kim,
Hyelim Park, Taeyoul Jang, Haedo Jeong, Juhwa Kim, Jeongho Park, Raeyoung Kim, Jeonghoon Park, HeeJae Jo, Whee Jin Kim, Jangbeom Yang, Bongjin Sohn, Yuncheol Han, Inchun Lim, Seoungjae Yoo, Changsoon Park, Dae-geun Jang,
ISSCC 2021 Session 28 Medical & Bio
A Distortion-Free VCO-Based Sensor-to-Digital Front-End Achieving 178.9dB FoM and 128dB SFDR with a CalibrationFree Differential Pulse-Code Modulation Technique
Jiannan Huang, Patrick P. Mercier
Motion and stimulation artifacts encountered in wearable sensors present difficult dynamic range (DR) and linearity challenges: AFEs need to be able to resolve μV-level signals in the presence of artifacts up to 100s of
University of California, San Diego, CA
ISSCC 2021 Session 27 Data Converters
A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR Figure 27.7.3 shows the NS-SAR schematic and timing diagram. The LPF tracking and the SAR conversion take up 1/8 and 3/8 of a clock period, respectively. The rest is allocated for the residue amplification and integration.
Linxiao Shen1,2, Zijie Gao3, Xiangxing Yang2, Wei Shi2, Nan Sun2,3
For simplicity of design, this work uses top-plate sampling. To improve its linearity, 2 switches are used to disconnect CDAC from the nonlinear input capacitance of the comparator and the dynamic amplifier (DA) during t
ISSCC 2021 Session 27 Data Converters
A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration
Hongshuai Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 To suppress the gain error from dynamic-power amplifiers, recently presented approaches including gain-error shaping (GES) [1], digital amplifiers [2]
University of Macau, Macau, China
ISSCC 2021 Session 27 Data Converters
An 80MHz-BW 640MS/s Time-Interleaved Passive NoiseShaping SAR ADC in 22nm FDSOI Process
Chin-Yu Lin*, Ying-Zu Lin*, Chih-Hou Tsai, Chao-Hsin Lu
*Equally-Credited Authors (ECAs) Recently, both the number of smart devices and the amount of data transfered to and from these devices have grown at unprecedented rates. To provide users with a highquality experience, w
MediaTek, Hsinchu, Taiwan
ISSCC 2021 Session 27 Data Converters
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
Xiyuan Tang1, Xiangxing Yang1, Jiaxin Liu2, Wei Shi1, David Z. Pan1, Nan Sun1,2
Tsinghua University, Beijing, China 1 2 Many applications, such as multi-standard wireless and event-driven IoT devices, demand high-resolution ADCs with scalable sampling rate and power consumption. The conventional pip
University of Texas, Austin, TX
ISSCC 2021 Session 27 Data Converters
A 13.8-ENOB 0.4pF-CIN 3rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation
Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Shaolan Li
Noise-shaping SAR (NS-SAR) ADCs are attracting rising attention for their low-power high-resolution capability. In most recent arts, a substantial focus is placed on improving the loop filter design by using techniques s
Georgia Institute of Technology, Atlanta, GA
ISSCC 2021 Session 27 Data Converters
-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC
Kyojin Choo, Hyochan An, Dennis Sylvester, David Blaauw
IoT sensors are in rising demand and they often require low power, yet high precision measurements. Under constrained energy, Nyquist-rate SAR ADCs are typically used for readout as they are energy efficient and easy to
University of Michigan, Ann Arbor, MI
ISSCC 2021 Session 27 Data Converters
A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering
Jiaxin Liu1, Dengquan Li2, Yi Zhong1, Xiyuan Tang3, Nan Sun1,3
Xidian University, Xi’an, China 3 University of Texas, Austin, TX 1 2 The noise-shaping (NS) SAR is an emerging hybrid architecture that aims to combine the benefits of both SAR and ∆Σ ADCs [1-8]. The key in an NS SAR is
Tsinghua University, Beijing, China
ISSCC 2021 Session 26 RF & Wireless
An Impedance-Transforming N-Path Filter Offering Passive Voltage Gain
Mohammad Khorshidian, Harish Krishnaswamy
The four main passive circuit elements include the resistor, capacitor, inductor, and transformer. Inductors and transformers have been notoriously challenging to integrate in silicon, and they occupy a significant chip
Columbia University, New York, NY
ISSCC 2021 Session 26 RF & Wireless
A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency
Aoyang Zhang, Ce Yang, Mostafa Ayesh, Mike Shuo-Wei Chen
Enhancing PA efficiency in the power back-off (PBO) region has become an important design objective due to the high peak-to-average power-ratio (PAPR) modulation in modern communications. Recently, a voltage-mode subharm
University of Southern California, Los Angeles, CA
ISSCC 2021 Session 26 AI / ML
A Watt-Level Quadrature Switched/Floated-Capacitor Power Amplifier with Back-Off Efficiency Enhancement in Complex Domain Using Reconfigurable Self-Coupling Canceling Transformer
Bingzheng Yang, Huizhen Jenny Qian, Xun Luo
Modern wireless communication systems in portable devices require transmitters (TXs) with watt-level output power (Pout), high data-rate, and high efficiency, especially at power back-off (PBO) for enhanced average effic
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2021 Session 26 RF & Wireless
A Reflection-Coefficient Sensor for 28GHz Beamforming Transmitters in 22nm FD-SOI CMOS
Yang Zhang, Giovanni Mangraviti, Johan Nguyen, Zhiwei Zong, Piet Wambacq
Millimeter-wave beamforming transmitters use antenna arrays to increase the EIRP by focusing the radiation pattern into a direction chosen by programming the TX phase shifters. However, under sharp scanning angles, the a
imec, Heverlee, Belgium
ISSCC 2021 Session 26 RF & Wireless
A mm-Wave Power Amplifier for 5G Communication Using a Dual-Drive Topology Exhibiting a Maximum PAE of 50% and Maximum DE of 60% at 30GHz
Edgar Felipe Garay, David Joseph Munzer, Hua Wang
The mm-wave spectrum is opening a new opportunity for TRx systems to operate at high-Gb/s data-rates. However, this opportunity is also imposing stringent requirements for power amplifiers (PAs) in terms of efficiency an
Georgia Institute of Technology, Atlanta, GA
ISSCC 2021 Session 26 RF & Wireless
A Doherty-Like Load-Modulated Balanced Power Amplifier Achieving 15.5dBm Average Pout and 20% Average PAE at a Data Rate of 18Gb/s in 28nm CMOS
Valdrin Qunaj, Patrick Reynaert
The continuous growth in demand for high-speed wireless connectivity is one of the main driving forces in the standardization and development of mm-wave systems. 5G new radio (NR) and also satellite communication with re
KU Leuven - MICAS, Leuven, Belgium
ISSCC 2021 Session 26 RF & Wireless
A 26-to-60GHz Continuous Coupler-Doherty Linear Power Amplifier for Over-An-Octave Back-Off Efficiency Enhancement
Tzu-Yuan Huang, Naga Sasikanth Mannem, Sensen Li, Doohwan Jung,
key enablers for 5G and beyond-5G wireless revolutions. To maximize the channel capacity, throughput, and frequency diversity, mm-wave wireless standards often mandate channels with GHz bandwidth (BW) over multiple non-c
Min-Yu Huang, Hua Wang Georgia Institute of Technology, Atlanta, GA It
ISSCC 2021 Session 25 Memory
An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling
Timothy M. Hollis1, Ronny Schneider2, Martin Brox2, Thomas Hein2,
Wolfgang Spirkl2, Martin Bach2, Mani Balakrishnan2, Stefan Dietrich2, Fabien Funfrock2, Milena Ivanov2, Natalija Jovanovic2, Maksim Kuzmenka2, Daniel Lauber2, Juan Ocon-Garrido2, David Ovard1, Karl Pfefferl2, Sven Piatko
ISSCC 2021 Session 25 Memory
A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a
Mosaic Architecture with a Short-Feedback 1-Tap DFE, an, FSS Bus with Low-Level Swing and an Adaptively Controlled
Body Biasing in a 3rd-Generation 10nm DRAM Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung-Hyun Cho, Dong-Yeon Park, Young-Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-
ISSCC 2021 Session 25 Memory
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation
Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gangsik Lee,
Sangyeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park , Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sa
ISSCC 2021 Session 24 Memory
A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-CellBased Two-Port Register File with a 16T Bitcell with No Half-Selection Issue
Hidehiro Fujiwara, Yi-Hsin Nien, Chih-Yu Lin, Hsien-Yu Pan, Hao-Wen Hsu,
the minimum operating voltage (VMIN). Furthermore, fin formation differences between the SRAM bitcells, the peripheral circuits and the standard logic degrade area efficiency due to the empty spaces at fin-to-fin boundar
Shin-Rung Wu, Yao-Yi Liu, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang
ISSCC 2021 Session 24 Memory
A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit
Taejoong Song, Woojin Rim, Hoonki Kim, Keun Hwi Cho, Taeyeong Kim,
TaeJung Lee, Geumjong Bae, Dong-Won Kim, SD Kwon, Sanghoon Baek, Jonghoon Jung, Jongwook Kye, Hakchul Jung, Hyungtae Kim, Soon-Moon Jung, Jaehong Park Samsung Electronics, Hwaseong, Korea Advanced technologies help to im
ISSCC 2021 Session 24 Memory
A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µm2 Cell Size Using Self-Adaptive Delayed Termination and MultiCell Reference
Jianguo Yang1,2, Xiaoyong Xue3, Xiaoxin Xu1, Qiao Wang1, Haijun Jiang2,
Lab, Hangzhou, China 3 Fudan University, Shanghai, China 1 2 High-density embedded nonvolatile memory (eNVM) at advanced technology nodes is still in great demand for SOC chips used in consumer electronics, self-driving
Jie Yu1, Danian Dong1, Feng Zhang1, Hangbing Lv1, Ming Liu1 Institute
ISSCC 2021 Session 24 Memory
A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology
Alexander Fritsch1, Rajiv Joshi2, Sudipto Chakraborty2, Holger Wetter1,
Uma Srinivasan1, Matthew Hyde3, Otto Torreiter1, Michael Kugel1, Dan Radko3, Hyong Kim3, Daniel Friedman2 IBM, Boeblingen, Germany IBM Research, Yorktown Heights, NY 3 IBM, Poughkeepsie, NY 1 2 8T SRAM, using domino read