ISSCC 2021
Session 7
Image Sensors
A 189×600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR Systems
Kenichi Tayu1, Keitaro Amagawa2, Tomohiro Matsukawa1, Osamu Ozawa1, Daisuke Hirono1, Yasuhiro Shinozuka1, Ryutaro Homma1, Kumiko Mahara2, Toshio Ohyama1, Yousuke Morita1, Shohei Shimada1, Takahisa Ueno3, Akira Matsumoto1
ISSCC 2021
Session 7
Image Sensors
A 48×40 13.5mm Depth Resolution Flash LiDAR Sensor with In-Pixel Zoom Histogramming Time-to-Digital Converter
diverse applications such as user identification, interactive user interfaces with AR/VR devices, and self-driving cars. Direct time-of-flight (D-ToF) systems, LiDAR sensors, are desirable for long-distance measurements
ISSCC 2021
Session 7
Image Sensors
A 4-tap 3.5µm 1.2Mpixel Indirect Time-of-Flight CMOS Image Sensor with Peak Current Mitigation and Multi-User Interference Cancellation
Bumsik Chung, Sooho Son, Hoyong Lee, Heeyoung Jo, Seung-Chul Shin, Sunjoo Hong, Jaeil An, Yonghun Kwon, Sungyoung Seo, Sunghyuck Cho, Youngchan Kim, Young-Gu Jin, Youngsun Oh, Yitae Kim, JungChak Ahn, Kyoungmin Koh, Yong
ISSCC 2021
Session 6
AI / ML
A 1.75dB-NF 25mW 5GHz Transformer-Based NoiseCancelling CMOS Receiver Front-End
Massachusetts Institute of Technology, Cambridge, MA 1 2 With continuous exploitation of sub-6GHz wireless communication standards and the advent of 5G and 6G, the demand for faster speed and wider coverage keeps evolvin
ISSCC 2021
Session 6
RF & Wireless
Full-Duplex Receiver with Wideband Multi-Domain FIR
Aravind Nagulu*1, Sasank Garikapati*1, Mostafa Essawy2, Igor Kadota1, Tingjun Chen1, Arun Natarajan2, Gil Zussman1, Harish Krishnaswamy1 Columbia University, New York, NY Oregon State University, Corvallis, OR 1 2 *Equal
ISSCC 2021
Session 6
RF & Wireless
A 3dB-NF 160MHz-RF-BW Blocker-Tolerant Receiver with Third-Order Filtering for 5G NR Applications
imposed several challenges in the design of sub-6GHz receivers (RX). Firstly, the maximum channel bandwidth (2BW) increases to 100MHz, while a -15dBm continuous-wave (CW) blocker can be located only Δf=85MHz away from th
ISSCC 2021
Session 6
RF & Wireless
A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <−81dBm LO Leakage Supporting Intra- and Inter-Band Carrier Aggregation
Programmable receivers have drawn a lot of attention in recent years, especially those exploiting periodically time-varying (PTV) circuits. N-path filters and mixer-first receivers [1$3] achieve sharp filtering and good
ISSCC 2021
Session 6
RF & Wireless
A 4-Way Doherty Digital Transmitter Featuring 50%-LO Signed IQ Interleave Upconversion with more than 27dBm Peak Power and 40% Drain Efficiency at 10dB Power BackOff Operating in the 5GHz Band
Mohsen Hashemi1,4, Dieuwert Mul1, Leo C.N. de Vreede1, Morteza S. Alavi1 Delft University of Technology, Delft, The Netherlands now with imec-Netherlands, Eindhoven, The Netherlands 3 now with Broadcom-Netherlands, Bunni
ISSCC 2021
Session 6
RF & Wireless
A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1
Seunghoon Kang, Ikkyun Jo, Suseop Ahn, Jaeseung Lee, Jeongyeol Bae, Won Ko, Wonjun Jung, Sangho Lee, Sangsung Lee, Euiyoung Park, Sungjun Lee, Jeongkyun Woo, Jaehoon Lee, Yanghoon Lee, Kyungmin Lee, Jongwoo Lee, Thomas B
ISSCC 2021
Session 5
Analog Circuits
A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique
One of the most key analog blocks in VLSI is probably the buffer amplifier dedicated to driving large off-chip loads. However, achieving fast settling-time and high output current drivability over a wide input voltage ra
ISSCC 2021
Session 5
Analog Circuits
A MEMS Coriolis Mass Flow Sensor with 300µg/h/√Hz Resolution and ±0.8mg/h Zero Stability
in the pharmaceutical, food, and semiconductor industries to measure small amounts (<1gram/hour) of liquids and gases. MEMS thermal flow sensors currently achieve state-of-the-art performance in terms of resolution, size
ISSCC 2021
Session 5
Analog Circuits
A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing
Instruments, Freising, Germany 4 Kilby Labs, Texas Instruments, Santa Clara, CA 1 2 Electric vehicle battery chargers, solar-panel inverters, industrial power monitoring, and many other high voltage applications rely on
ISSCC 2021
Session 5
Analog Circuits
A Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor with a Self-Calibrated Inaccuracy of ±0.25°C (3σ) from −55°C to 125°C
Resistor-based temperature sensors can achieve higher resolution and energy-efficiency than traditional BJT-based sensors. To reach similar accuracy, however, they typically require 2-point (2-pt) calibration, compared t
ISSCC 2021
Session 5
Analog Circuits
A Highly Digital 2210µm2 Resistor-Based Temperature Sensor with a 1-Point Trimmed Inaccuracy of ±1.3°C (3σ) from -55°C to 125°C in 65nm CMOS
Yonsei University, Seoul, Korea 1 2 Microprocessors and SoCs employ multiple temperature sensors to prevent overheating and ensure reliable operation. Such sensors should be small (<10,000µm)) to monitor local hot-spots
ISSCC 2021
Session 5
Analog Circuits
Capacitance-to-Digital Converter for Operation Under
capacitive sensing via capacitance-to-digital conversion (CDC) needs to operate with minimal or no support from additional circuitry such as voltage regulation, voltage/current references or digital post-processing as sh
ISSCC 2021
Session 5
Analog Circuits
A 1.5µW 0.135pJ∙%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array
China in the DSM is ~200fF, and an LSB of the SAR DAC is ~50fF. Hence, the differential input range of the DSM can be calculated as 2%200fF/50fF = 8LSBs of the SAR, and 0.5LSB error is equal to 6.25% of the range. When A
ISSCC 2021
Session 4
Digital Processors
An Area and Energy Efficient 0.12nJ/Pixel 8K 30fps AV1 Video Decoder in 5nm CMOS Process
SeungSick Jun, YongMi Lee, Seungyong Lee, Homin Kang, Changhyun Yim, Yohan Lim, Eikyung Moon, Sukhwan Lim, Kyungah Jeong, Inyup Kang Samsung Electronics, Hwaseong, Korea Major content providers such as YouTube and Netfli
ISSCC 2021
Session 4
Digital Processors
A 91mW 90fps Super-Resolution Processor for Full HD Images
Super resolution is the process of reconstructing a high-resolution (HR) image from a low-resolution (LR) one. Super-resolution technology enables high-resolution video streaming, image zoom-in, and far object recognitio
ISSCC 2021
Session 4
Digital Processors
A 144Kb Annealing System Composed of 9×16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems
Service, Sapporo, Japan 1 2 Substantial progress has been made on a new computer architecture, known as an annealing processor (AP) [1–4]. The AP can effectively solve NP-hard combinatorial optimization problems by provi
ISSCC 2021
Session 4
Digital Processors
BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring
health monitoring devices automatically detect abnormalities in users’ biomedical signals (e.g. arrhythmia from an ECG signal or a seizure from an EEG signal) through signal classification. Compared to conventional machi
ISSCC 2021
Session 4
Digital Processors
A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7µW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Alfio Di Mauro2, Marco Guermandi1,3, Giuseppe Tagliavini1, Antonio Pullini2,3, Igor Loi3, Jie Chen1,3, Eric Flamand2,3, Luca Benini1,2 University of Bologna, Bologna, Italy ETH Zurich, Zurich, Switzerland 3 Greenwaves Te
ISSCC 2021
Session 4
Digital Processors
An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET
such as deep neural networks (DNNs), increasingly rely on dense arithmetic compute patterns that are ill-suited for general-purpose processors, leading to a rise in domain-specific compute accelerators [1]. Many of these
ISSCC 2021
Session 4
Digital Processors
A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem
Gokulakrishnan Manoharan1, Ericbill Wang2, Gordon Gammie1, Efron Ho1, Anand Rajagopalan1, Lee-Kee Yong1, Ramu Madhavaram1, Madhur Jagota1, Chi-Jui Chung1, Sudhakar Maruthi1, Jenny Wiedemeier1, Tao Chen1, Henry Hsieh2, Da
ISSCC 2021
Session 36
Hardware Security
An Automatic Self-Checking and Healing Physically Unclonable Function (PUF) with <3×10-8 Bit Error Rate
*Equally Credited Authors (ECAs) Physically unclonable functions (PUF) have emerged as a promising solution for secure and low-cost key storage and hardware authentication. A key challenge in PUF designs is ensuring the
ISSCC 2021
Session 36
Hardware Security
A Physically Unclonable Function Combining a Process Mismatch Amplifier in an Oscillator Collapse Topology
Physically unclonable functions (PUFs) have been actively investigated as a promising solution for low-cost secure authentication in Internet of Things (IoT) applications. A PUF should generate unique challenge-response
ISSCC 2021
Session 36
Hardware Security
A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In
lowenergy and low-latency authentication requirements of IoT applications, owing to their exponential number of challenge-response pairs (CRPs). However, Strong PUFs suffer from vulnerability to modeling attacks and a hi
ISSCC 2021
Session 36
Hardware Security
An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control
side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical sidechannel analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include current equali
ISSCC 2021
Session 36
Hardware Security
Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security including PUF responses lying at bin boundaries (affecting masking only marginally, see BER below).
In Fig. 36.1.4, the TRNG was confirmed to have consistent measured output quality across very different data patterns (all 0’s for minimum jitter vs. random data), 0.8-to-1V supply and -10 to 75°C temperature. The min-en
ISSCC 2021
Session 35
Digital Circuits
Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm HexagonTM Processor
Qualcomm, Raleigh, NC 1 2 The Hexagon™ compute DSP (CDSP) integrates a master VLIW scalar processor and a slave vector coprocessor to enable high-performance and energy-efficient computing for multimedia, voice, audio, v
ISSCC 2021
Session 35
Digital Circuits
A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology
Sébastien Genevey1, Lionel Pierrefeu1, Emmanuel Grand1, Joerg Winkler3, Jonathan Park4, Gaël Pillonnet2, Vincent Huard1, Andrea Bonzo1, Philippe Flatresse1 Dolphin Design, Meylan, France CEA-Léti, Grenoble, France 3 Glob
ISSCC 2021
Session 35
Digital Circuits
An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC
Chi-Hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, YS Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang MediaTek, Hs
ISSCC 2021
Session 34
Image Sensors
An Energy-Replenishing Ultrasound Pulser with 0.25CV2f Dynamic Power Consumption
Daegu Catholic University Medical Center, Daegu, Korea 4 Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea 5 New York University Abu Dhabi, Abu Dhabi, United Arab Emirates leads to the end of Φ1 by turnin
ISSCC 2021
Session 34
Image Sensors
A 32×32 Pixel 0.46-to-0.75THz Light-Field Camera SoC in 0.13µm CMOS
Robin Zatta, Ullrich R. Pfeiffer University of Wuppertal, Wuppertal, Germany Light-field (LF) refers to the spatio-directional light flow in space. In LF imaging, light rays are recorded along different positions and dir
ISSCC 2021
Session 34
Image Sensors
A 21pJ/frame/pixel Imager and 34pJ/frame/pixel Image Processor for a Low-Vision Augmented-Reality Smart Contact Lens the duration of Φ1 in 4- and 6-bit modes while still meeting the PGA settling accuracy. The ADC sampling capacitor array embeds an analog offset subtraction technique to calibrate accumulated offset errors and adjust the pixel black level prior to signal quantization.
Figure 34.2.3 shows the imager characterization results. The core imager energy consumption per frame remains relatively flat across a wide range of frame rates. This is achieved by powering down the imager during idle p
ISSCC 2021
Session 34
Image Sensors
An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound
Sewook Hwang1, Joseph Lutsky1, Jungwook Yang1, Liewei Bao1, Leung Kin Chiu1, Graham Peyton1, Hamid Soleimani1, Bob Ryan1, J. R. Petrus1, Youn-Jae Kook1, Tyler S. Ralston2, Keith G. Fife2, Jonathan M. Rothberg2 Butterfly
ISSCC 2021
Session 33
Wireless
A Hybrid Switching Supply Modulator Achieving 130MHz Envelope-Tracking Bandwidth and 10W Output Power for 2G/3G/LTE/NR RF Power Amplifiers
Young-Ho Jung, Jaeyeol Han, Ik-Hwan Kim, Sung-Youb Jung, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho Samsung Electronics, Hwasung, Korea Envelope tracking (ET) is a key technology improving efficien
ISSCC 2021
Session 33
Wireless
A Decentralized Daisy-Chain-Controlled Switched-Capacitor Driver for Microrobotic Actuators with 10× Power-Reduction Factor and Over 300V Drive Voltage
Electrostatic and piezoelectric actuators are used in a number of mm- and cm-scale robotic applications due to their relatively high energy-density at small size and weight [1-3]. Such transducers typically require high
ISSCC 2021
Session 33
Wireless
A Frequency-Splitting-Based Wireless Power and Data Transfer IC for Neural Prostheses with Simultaneous 115mW Power and 2.5Mb/s Forward Data Delivery
electrical cochlear implants (CIs) have given >500,000 patients worldwide a better life to date. However, the electrical neural stimulation has limited spatial resolution due to the spread of stimulation current, which r
ISSCC 2021
Session 33
Wireless
A Wireless Power Transfer System with Up-to-20% LightLoad Efficiency Enhancement and Instant Dynamic Response by Fully Integrated Wireless Hysteretic Control for Bioimplants
Wireless power transfer (WPT) systems are becoming increasingly popular for sub100mW biomedical applications [1-5]. Because the received power is sensitive to coupling and loading conditions, power/voltage regulations ar
ISSCC 2021
Session 33
AI / ML
A 1.25W 46.5%-Peak-Efficiency Transformer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Wafer-Level Packaging Achieving 50mW/mm2 Power Density polyimide layers with a dielectric breakdown strength of >400V/μm are laminated among 3 RDLs to form isolation barriers, providing better than 5kV isolation rating. Consequently, the transformer achieves a coupling coefficient of 0.8, enabling over 1W power delivery.
Daquan Yu2, Ming Liu3, Lin Cheng1 Figure 33.5.3 shows the simplified schematic of the power stage. In the Tx, an LC tank oscillator with an AC-coupled structure is adopted. To handle a wide supply voltage (VDD) range of
ISSCC 2021
Session 33
Wireless
An 8A 998A/inch3 90.2% Peak Efficiency 48V-to-1V DC-DC Converter Adopting On-Chip Switch and GaN Hybrid Power Conversion
intelligent and power hungry. The 48V-to-1V converter, which offers a promising solution to the highpower density data center and automotive applications, is quickly gaining the interest of researchers [1-4]. The prior s
ISSCC 2021
Session 33
Wireless
An Automotive-Use 2MHz 100VOUT Flicker-Free FrequencyModulated GaN-Based Buck-Boost LED Driver Achieving Bootstrap Charge Balancing and 16.8dBµV Radiated EMI Noise Reduction
(up to 30 LEDs in series) for sequential turn signal light. As the LEDs are turned on/off sequentially, the output voltage across the LED string (VOUT) can be below, equal to, or above the input battery voltage (VIN) whi
ISSCC 2021
Session 33
Wireless
A 600V GaN Active Gate Driver with Dynamic Feedback Delay Compensation Technique Achieving 22.5% Turn-On Energy Saving are shown in Fig. 33.2.3. The detection branch current Isen is copied to the AMPD proportionally through current mirror pairs of MP5 and MP6. For large dv/dt value, the gate voltage of MP0 is higher, realizing lower gate overdrive voltage. Otherwise the gate overdrive voltage will increase to enable a larger driving current.
The phase modulation circuit and its waveforms are depicted in Fig. 33.2.3. The phase difference between SRstart and VFBD is detected by the phase-detect circuit (PD) and then converted to voltage domain through the char
ISSCC 2021
Session 33
Wireless
A Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch with Temperature-compensated Fast Turn-on Technique for Improving Reliability
Gallium-Nitride (GaN) high-electron-mobility transistors (HEMTs) have the advantages of low parasitic capacitance, low on-resistance (RON), and no reverse recovery charge loss [1-5]. Thus, using GaN HEMTs one can optimiz
ISSCC 2021
Session 32
Clocking & PLLs
A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
Francesco Buccoleri1, Luca Avallone2, Angelo Parisi1, Dmytro Cherniak3, Andrea L. Lacaita1, Michael Peter Kennedy2, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milano, Italy University College Dublin, Dubl
ISSCC 2021
Session 32
Clocking & PLLs
A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth
independent crystal oscillators (XOs): a 32.768kHz XO for the real-time clock (RTC) and a tens of MHz XO for low-jitter clock and carrier synthesis. To reduce the number of XOs, 32kHz-reference phase-locked loops (PLLs)
ISSCC 2021
Session 32
Clocking & PLLs
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS
Sergey Bershansky2, Nir Geron2, Ashoke Ravi3, Rotem Banin2, Jasmin Kadry2, Gil Horovitz2, Christian Krassnitzer1, Christoph Duller1, Patrick Torta1, Mark Elzinga4, Kamran Azadet5 Intel, Villach, Austria Intel, Israel, Is
ISSCC 2021
Session 32
Clocking & PLLs
A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/µs Slope
for millimeter-wave (mm-wave) frequency-modulated continuous-wave (FMCW) radars. Large-chirp-bandwidth (BWchirp) sawtooth waveforms are required to be synthesized with fast slope and high-frequency linearity for accurate
ISSCC 2021
Session 32
Clocking & PLLs
A 104fsrms-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique
2 *Equally Credited Authors (ECAs) Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, KSH. However, this highgain op
ISSCC 2021
Session 32
Clocking & PLLs
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
Francesco Buccoleri1, Luca Avallone2, Angelo Parisi1, Andrea Leonardo Lacaita1, Michael Peter Kennedy2, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy University College Dublin, Dublin, Ireland f