ISSCC 2022
Session 14
Wireless
A Monolithic GaN-Based Driver and GaN Power HEMT with Diode-Emulated GaN Technique for 50MHz Operation and Sub-0.2ns Deadtime Control
Taiwan 1 2 Monolithic gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) have become popular due to their low parasitic capacitance, low on-resistance (RON), and no reverse recovery charge loss for high-fre
ISSCC 2022
Session 13
Digital Circuits
A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for
Xinjian Liu, Sumanth Kamineni, Jacob Breiholz, Benton H. Calhoun, Shuo Li University of Virginia, Charlottesville, VA A self-powered IoT system-on-chip (SoC) reduces power to sub-µW and employs multiple power-management
ISSCC 2022
Session 13
Digital Circuits
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains
and wearable applications are aggressively duty-cycled to minimize leakage energy losses. Such systems operate predominantly in Sleep mode, regularly marked by brief intervals of Active operation to perform sensing or co
ISSCC 2022
Session 13
Digital Circuits
A 0.65V 1316µm2 Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving 0.16nJ·%2-Accuracy FoM in 5nm FinFET CMOS
performance of SoCs, which is rapidly increasing overall chip temperature. As a result, dynamic thermal management (DTM) using a number of temperature sensors is essential. For accurate temperature measurement, the senso
ISSCC 2022
Session 13
Digital Circuits
Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor
Essex Junction, VT 1 2 Shrinking transistor sizes allow increased logic complexity in modern processors, but smaller dimensions increase power density and require reduced maximum voltage (VDDMAX) for reliability; this ca
ISSCC 2022
Session 13
Digital Circuits
Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC
In mobile SoC, clock sources such as PLLs, are expensive resources both in terms of area and power, and they are commonly shared by multiple clock consumers. To that end, the latest SoCs hold tens of PLLs and hundreds of
ISSCC 2022
Session 13
Digital Circuits
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency
University of Washington, Seattle, WA 1 2 The digital injection-locked clock multiplier (ILCM) using ring oscillators (ROs) is a superior choice for clock generation due to its ease of scaling, compact area, and prominen
ISSCC 2022
Session 13
Digital Circuits
Clock Generator with ISO26262 ASIL-D Grade Safety Mechanism for SoC Clocking Application
advanced integrated circuits for automotive applications have become stricter than at any other time. ISO26262 (Road Vehicle Functional Safety Standard) determines the risk level associated with systematic and random fai
ISSCC 2022
Session 12
Medical & Bio
1024 3D-Stacked Monolithic NEMS Array with 375µm2 0.5mW 0.28ppm Frequency Deviation Pixel-level Readout for Zeptogram Gravimetric Sensing
Christophe Plantier, Emmanuel Rolland, Marc Gely, Giulia Usai, Claude Tabone, Gaël Pillonnet, Stéphanie Robinet, Sébastien Hentz CEA-Léti, Grenoble, France NanoElectroMechanical System (NEMS)-based resonator sensors are
ISSCC 2022
Session 12
Medical & Bio
A CMOS Molecular Electronics Chip for Single-Molecule Biosensing
Roswell Biotechnology, San Diego, CA metal are exposed by etching away a sacrificial 23µm×15µm “bond pad” to expose a common staging area for the electrodes of 4 adjacent pixels. The 50nm wide electrodes are patterned, t
ISSCC 2022
Session 12
Medical & Bio
A CMOS Cellular Interface Array for Digital Physiology Featuring High-Density Multi-Modal Pixels and Reconfigurable Sampling Rate
Jongseok Park4, Dongwon Lee1, Mian Wang2, Sushila Maharjan2, Sagar Kumashi1, Jin Hao2, Yu Shrike Zhang2, Kevin Eggan5, Hua Wang1,6 Georgia Institute of Technology, Atlanta, GA Brigham and Women’s Hospital, Harvard Univer
ISSCC 2022
Session 12
Medical & Bio
A 256-Channel Actively-Multiplexed µECoG Implant with Column-Parallel Incremental ∆Σ ADCs Employing Bulk-DACs in 22-nm FDSOI Technology
Chris Van Hoof1,2, Jan Genoe1,2, Sebastian Haesler1,2,3,5, Georges Gielen1,2, Nick Van Helleputte1, Carolina Mora Lopez1 imec, Leuven, Belgium KU Leuven, Leuven, Belgium 3 Neuroelectronics Research Flanders, Leuven, Belg
ISSCC 2022
Session 12
Medical & Bio
A Self-powering Wireless Soil-pH and Electrical Conductance Monitoring IC with Hybrid Microbial Electrochemical and Photovoltaic Energy Harvesting
Ting-Heng Lu1, Ling-Chia Chen1, I-Che Ou1, Sook-Kuan Lee2, Yen-Chi Chen2, Po-Hung Chen1, Chi-Te Liu2, Ying-Chih Liao2, Yu-Te Liao1 National Yang Ming Chiao Tung University, Hsinchu, Taiwan National Taiwan University, Tai
ISSCC 2022
Session 12
Medical & Bio
A 200 x 256 Image Sensor Heterogeneously Integrating a 2D Nanomaterial-Based Photo-FET Array and CMOS Time-to-Digital Converters
voltage VINT. Upon light illumination, the photocurrent through the drain of the MoS2 photo-FET in a given pixel discharges CP, and a counter records the total number of clock cycles (nCLK), until the voltage across CP r
ISSCC 2022
Session 12
Medical & Bio
A 210 × 340 × 50µm Integrated CMOS System for
Processing, Communication and Actuation Li Xu1, Maya Lassiter2, Xiao Wu1, Yejoong Kim1, Jungho Lee1, Makoto Yasuda3, Masaru Kawaminami4, Marc Miskin2, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, M
ISSCC 2022
Session 11
AI / ML
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices
Jin-Sheng Ren1, Fu-Chun Chang1, Yuan Wu1, Ho-Yu Chen1, Chen-Hsun Lin1, Hsu-Ming Hsiao2, Sih-Han Li2, Shyh-Shyuan Sheu2, Shih-Chieh Chang2, Wei-Chung Lo2, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1
ISSCC 2022
Session 11
AI / ML
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-LogicBased ADC-less SRAM Compute-In-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
China 4 Duke University, Durham, NC 1 2 Advanced intelligent embedded systems perform cognitive tasks with highly-efficient vector-processing units for deep neural network (DNN) inference and other vector-based signal pr
ISSCC 2022
Session 11
AI / ML
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computingin-Memory Macro Supporting Wide-Range Dynamic-VoltageFrequency Scaling and Simultaneous MAC and Write Operations
Rawan Naous2, Chao-Kai Chuang1, Takeshi Hashizume3, Dar Sun1, Chia-Fu Lee1, Kerem Akarvardar2, Saman Adham4, Tan-Li Chou1, Mahmut Ersin Sinangil2, Yih Wang1, Yu-Der Chih1, Yen-Huei Chen1, Hung-Jen Liao1, Tsung-Yung Jonat
ISSCC 2022
Session 11
AI / ML
Single-Mode CMOS 6T-SRAM Macros with Keeper-LoadingFree Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms
Advanced Institute of Information Technology of Peking University, Hangzhou, China 1 2 Miniaturized wireless IoT sensor nodes stay mostly in their standby mode and wake up periodically to sense and store a small amount o
ISSCC 2022
Session 11
AI / ML
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-SpaceReadout with 1286.4 - 21.6TOPS/W for Edge-AI Devices
Tai-Hao Wen1, Chin-I Su2, Win-San Khwa2, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Yu-Der Chih2, Tsung-Yung Jonathan Chang2, Meng-Fan Chang1,2 National Tsing Hua University, Hsinchu, Taiwan TSMC
ISSCC 2022
Session 11
AI / ML
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations
Fu-Chun Chang1, Yuan Wu1, Yu-An Chien1, Fang-Ling Hsieh1, Chung-Yuan Li1, Guan-Yi Lin1, Po-Jung Chen1, Tsen-Hsiang Pan1, Chung-Chuan Lo1, Win-San Khwa2, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Chieh-Pu Lo2, Yu
ISSCC 2022
Session 10
Data Converters
A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR
Peking University, Beijing, China 1 2 High-resolution (>100dB SNDR), kHz-BW ADCs are required by emerging IoT and smart sensing applications. These ADCs are desired for their high efficiency, but low cost and ease of int
ISSCC 2022
Session 10
Data Converters
A 4.96µW 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC
applications, such as smart sensors and event-driven IoT devices, which need ADCs with high resolution, high power efficiency, and can be multiplexed between multiple inputs. Despite these advantages, they usually need a
ISSCC 2022
Session 10
Data Converters
A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOS
for low-to-medium speed applications. The ADC function accommodates a wide range of use, including Nyquistrate data acquisition and oversampled signal applications. The noise spectral density (NSD) is uniform from 0Hz to
ISSCC 2022
Session 10
Data Converters
A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment
The pipelined SAR ADC is a promising architecture to achieve high sample rate with high resolution. Residue amplifiers are normally required between pipelined stages to provide sufficient gain for relaxing the noise requ
ISSCC 2022
Session 10
Data Converters
A 0.004mm2 200MS/s Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp
Peking University, Beijing, China 1 2 Pipelined ADCs are widely used for high-speed high-resolution applications, but there are two challenges. First, limited by the kT/C noise requirement, its 1st-stage sampling capacit
ISSCC 2022
Session 10
Data Converters
A 0.82mW 14b 130MS/s Pipelined-SAR ADC with a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend
To fulfill upcoming communication specifications, it has become popular recently to employ pipelined-SAR architectures, incorporating residue amplifiers (RA) to achieve high resolution, wide bandwidth, and low-power ADCs
ISSCC 2022
Session 10
Data Converters
A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology
High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-do
ISSCC 2021
Session 9
Digital Processors
A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain DivisiveEnergy Normalization for an Always-On Keyword Spotting Device
In mobile and edge devices, always-on keyword spotting (KWS) is an essential function to detect wake-up words. Recent works achieved extremely low power dissipation down to ~500nW [1]. However, most of them adopt noise-d
ISSCC 2021
Session 9
Digital Processors
A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET
Marco Donato2, Paul N. Whatmough1,3, Alexander M. Rush4, David Brooks1, Gu-Yeon Wei1 Harvard University, Cambridge, MA Tufts University, Medford, MA 3 ARM, Boston, MA 4 Cornell University, New York, NY 1 2 Automatic spee
ISSCC 2021
Session 9
Digital Processors
A 184µW Real-Time Hand-Gesture Recognition System with Hybrid Tiny Classifiers for Smart Wearable Devices
Nations Innovation Technologies, Singapore, Singapore 1 2 Recently, vision-based hand gesture recognition (HGR) has emerged as a natural and flexible human-computer interaction (HCI) approach. Users can control smart dev
ISSCC 2021
Session 9
AI / ML
A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image Sensor
Hareesh Gowtham2, Hidetomo Nakanishi2, Edan Almog3, Yoel Livne3, Gadi Yuval3, Eli Zyss3, Takashi Izawa2 Sony Semiconductor Solutions, Tokyo, Japan Sony Semiconductor Solutions, Atsugi, Japan 3 Sony Semiconductor Israel,
ISSCC 2021
Session 9
AI / ML
A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoC
Hanwoong Jung2, Seungwon Lee2, Suknam Kwon1, Kyungah Jeong1, Joon-Ho Song2, SukHwan Lim1, Inyup Kang1 Samsung Electronics, Hwaseong, Korea Samsung Advanced Institute of Technology, Suwon, Korea 1 2 On-device machine lear
ISSCC 2021
Session 9
Digital Processors
PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm
devices, their usage is also criticized due to lack of explainability, inability to include domain knowledge, and a need for large volumes of training data. To overcome this, researchers are increasingly using probabilis
ISSCC 2021
Session 9
AI / ML
A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree
*Equally Credited Authors (ECAs) Recent works on mobile deep-learning processors have presented designs that exploit sparsity [2, 3], which is commonly found in various neural networks. However, due to the shift in the m
ISSCC 2021
Session 9
AI / ML
A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction
edge devices efficiently, most existing CNN processors were built on quantized CNNs to optimize the inference operations. However, three issues (Fig. 9.2.1) have not been well addressed: 1) Duplicate weights in each kern
ISSCC 2021
Session 8
Wireline I/O
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver
equalization (e.g. extensive FFE and DFE) of wireline channels. FFE and canonical DFE sizes scale linearly with the number of taps, however the computational complexity of an FFE is much greater than that of a DFE. The c
ISSCC 2021
Session 8
Wireline I/O
A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET peaking inductor is leveraged to resonate out the parasitic & transistor gate capacitances. A flipped voltage follower buffer is used to isolate the CTLE from the 16 TAHs. The DCgain normalized frequency response at the output of the AFE for various CTLE settings is shown in the Fig. 8.7.3.
K. Raviprakash1, L. Tse1, M. Davoodi4, M. Takefman3, N. Fan4, P. Prabha4, Q. Liu2, Q. Wang1, R. Nagulapalli5, S. Cyrusian4, S. Jantzi4, S. Scouten3, T. Dusatko6, T. Setya3, V. Giridharan1, V. Gurumoorthy1, V. Karam3, W.
ISSCC 2021
Session 8
Wireline I/O
A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET
E. Olsen1, F. Ahmad1, G. Hatcher1, J. Chana3, L. Biolato2, L. Tse4, L. Wang1, L. Wang4, M. Azarmnia1, M. Davoodi1, N. Campos2, N. Fan1, P. Prabha1, Q. Lu1, S. Cyrusian1, S. Dallaire5, S. Ho3, S. Jantzi1, T. Dusatko3, W.
ISSCC 2021
Session 8
Wireline I/O
A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm
Larry Moser1, Yang Zhang1, Xiaolong Liu1, Man Pio Lam1, Haikun Jia2,3, Quan Pan2,4, Wing Hong Szeto2, Chi Fai Tang2, Ka Fai Mak2, Khawar Sarfraz2, Tairan Zhu1, Ming Kwan1, Emily Yim Lee Au1, Cormac Conroy1, Kai Keung Cha
ISSCC 2021
Session 8
Wireline I/O
A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2
Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Hu
ISSCC 2021
Session 8
Wireline I/O
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7nm CMOS
Thomas Morf1, Serdar A. Yonar1, Mridula Prathapan1, Eric J. Lukes2, Raymond A. Richetta2, Carrie Cox3 IBM Research, Rüschlikon, Switzerland IBM Systems and Technology, Rochester, MN 3 IBM Systems and Technology, Durham,
ISSCC 2021
Session 8
Wireline I/O
An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1-4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by mini
ISSCC 2021
Session 8
Wireline I/O
A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS
Bong Chan Kim1, Stephen Kim1, Yutao Liu1, Savyassachi Keshava Murthy1, Priya Wali1, Kai Yu1, Hyung Seok Kim1, Chuan-chang Liu1, Dongseok Shin1, Ariel Cohen3, Yongping Fan1, Frank O’Mahony1 Intel, Hillsboro, OR Foundation
ISSCC 2021
Session 7
Image Sensors
1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64µm Unit Pixels Separated by Full-Depth Deep-Trench Isolation
DongHyun Kim, Beomsuk Lee, SungIn Kim, Ho-Chul Ji, DongMo Im, Haeyong Park, Jinyoung Kim, JungHo Cha, Taehoon Kim, In-Sung Joe, Soojin Hong, Chongkwang Chang, Jingyun Kim, WooGwan Shim, Taehee Kim, Jamie Lee, Donghyuk Pa
ISSCC 2021
Session 7
Image Sensors
A 1-inch 17Mpixel 1000fps Block-Controlled Coded-Exposure Back-Illuminated Stacked CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range Control
In recent developments, image sensors are no longer simply a means for collecting optical signals, but rather, are increasingly expected to serve as intelligent systems with surrounding configurations. Coded exposure (CE
ISSCC 2021
Session 7
Image Sensors
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection
Mixed-signal vision chips are becoming increasingly popular for low-power embedded computer vision applications on smartphones, wearables and IoT nodes, as they meet stringent power and area constraints while maintaining
ISSCC 2021
Session 7
Image Sensors
A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADC
Takashi Moue1, Daisuke Yamazaki1, Kazutoshi Kodama1, Masafumi Okano1, Takafumi Morikawa1, Kazuyoshi Yamashita1, Osamu Oka2, Itai Shvartz3, Golan Zeituni3, Ariel Benshem3, Noam Eshel3, Yoshiaki Inada1 Sony Semiconductor S
ISSCC 2021
Session 7
Image Sensors
A 250fps 124dB Dynamic-Range SPAD Image Sensor Stacked with Pixel-Parallel Photon Counter Employing Sub-Frame Extrapolating Architecture for Motion Artifact Suppression
Yasuhisa Tochigi1, Yoshiaki Tashiro1, Fumiaki Sano1, Yusuke Murakawa2, Makoto Nakamura2, Yusuke Oike1 Sony Semiconductor Solutions, Kanagawa, Japan Sony Semiconductor Manufacturing, Nagasaki, Japan 1 2 Photon-count imagi
ISSCC 2021
Session 7
Image Sensors
A 256×128 3D-Stacked (45nm) SPAD FLASH LiDAR with 7-Level Coincidence Detection and Progressive Gating for 100m Range and 10klux Background Light
Augusto R. Ximenes4, Myung-Jae Lee5, Edoardo Charbon1 EPFL, Neuchâtel, Switzerland ADAPS Photonics, Shenzhen, China 3 Intuitive Surgical, Aubonne, Switzerland 4 Facebook, Redmond, WA 5 Korea Institute of Science and Tech