ISSCC 2022
Session 20
RF & Wireless
A 0.5mΩ/√Hz 106dB SNR 0.45cm2 Dry-Electrode Bioimpedance Interface with Current Mismatch Cancellation and Boosted Input Impedance of 100MΩ at 50kHz
Bioimpedance (BioZ) analysis has been recognized as a new paradigm to derive a number of body composition and hemodynamic measures in a non-invasive manner. Measuring the changes in electrical resistance of the thorax du
ISSCC 2022
Session 2
Digital Processors
Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core
Michael McCabe1, Timothy Johnson1, James Vinh1, Thomas Yiu1, Mark Wasio1, Hon-Hin Wong1, Daryl Lieu1, Jonathan White2, Benjamin Munger2, Joshua Lindner2, Javin Olson2, Steven Bakke2, Jeshuah Sniderman2, Carson Henrion3,
ISSCC 2022
Session 2
Digital Processors
A 16nm 785GMACs/J 784-Core Digital Signal Processor Array
amount of dark silicon area in power-limited SoCs makes it attractive to consider reconfigurable architectures that could intelligently repurpose dark silicon. FPGAs are more efficient than CPUs, but lack temporal dynami
ISSCC 2022
Session 2
Digital Processors
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC
Anand Rajagopalan1, Gordon Gammie1, Ramu Madhavaram1, Madhur Jagota1, CJ Chung1, Jenny Wiedemeier1, Bala Meera1, Chao-Yang Yeh2, Maverick Lin2, Curtis Lin2, Vincent Lin2, Jiun Lin2, YS Chen2, Barry Chen2, Cheng-Yuh Wu2,
ISSCC 2022
Session 2
Digital Processors
POWER10TM: A 16-Core SMT8 Server Processor with 2TB/s Off-Chip Bandwidth in 7nm Technology
Andrew Bianchi3, Daniel Dreps3, David Wolpert4, Eric Lai3, Gerald Strevig3, Glen Wiedemeier3, Philipp Salz5, Ryan Kruse3 IBM, Bengaluru, India; 2IBM, Yorktown Heights, NY; 3IBM, Austin, TX IBM, Poughkeepsie, NY; 5IBM, Bo
ISSCC 2022
Session 2
Digital Processors
IBM Telum: A 16-Core 5+ GHz DCM
Thomas Strach2, Di Phan1, Cedric Lichtenau2, Alper Buyuktosunoglu3, Hubert Harrer2, Jeffrey Zitz1, Chad Marquart1, Douglas Malone1, Tobias Webel2, Adam Jatkowski1, John Isakson4, Dina Hamid1, Mark Cichanowski4, Michael R
ISSCC 2022
Session 2
Digital Processors
Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor
Sitaraman V. Iyer2, Zibing Yang1, Oscar Mendoza1, Mark Huddart1, Srikrishnan Venkataraman3, Sireesha Kandula1, Rafi Marom4, Alexandra M. Kern1, Bill Bowhill1, David R. Mulvihill5, Srikanth Nimmagadda3, Varma Kalidindi1,
ISSCC 2022
Session 2
Digital Processors
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing
Srikrishnan Venkataraman4, Chris Pelto1, Tejas Shah5, Amreesh Rao2, Frank O’Mahony1, Eric Karl1, Lance Cheney2, Iqbal Rajwani2, Hemant Jain4, Ryan Cortez2, Arun Chandrasekhar4, Basavaraj Kanthi4, Raja Koduri6 Intel, Port
ISSCC 2022
Session 19
Power Management
A 1-to-18GHz Distributed-Stacked-Complementary TripleBalanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOI
transceiver systems, shown in Fig. 19.7.1, offer flexibility for multiband, multi-user, and joint communication-and-sensing platforms. However, wideband MIMO applications increase the number of desired or interfering sig
ISSCC 2022
Session 19
Power Management
A Broadband Mm-Wave VSWR-Resilient Joint True-Power Detector and Impedance Sensor Supporting Single-Ended Antenna Interfaces
ETH Zurich, Zurich, Switzerland 1 2 Mm-wave 5G communication seeks to support multi-Gb/s data-rates over its large available spectrum, particularly in the K/Ka bands (24 to 40GHz). To ensure sufficient link budget under
ISSCC 2022
Session 19
Power Management
A 26-to-39GHz Broadband Ultra-Compact High-Linearity Switchless Hybrid N/PMOS Bi-Directional PA/LNA Front-End for Multi-Band 5G Large-Scaled MIMO System
ETH Zurich, Zurich, Switzerland 1 2 The continuous growth of data-rates has stimulated the rapid development of 5G New Radio (NR) in the mm-wave FR2 bands (above 24GHz). Consequently, to compensate for the mm-wave high p
ISSCC 2022
Session 19
AI / ML
A 28GHz Compact 3-Way Transformer-Based Parallel-Series Doherty Power Amplifier with 20.4%/14.2% PAE at 6-/12-dB Power Back-Off and 25.5dBm PSAT in 55nm Bulk CMOS
University of Electronic Science and Technology of China, Chengdu, China 1 2 The 28GHz band for fifth-generation (5G) millimeter-wave wireless communication supporting high-order QAM, OFDM, and carrier aggregation (CA) r
ISSCC 2022
Session 19
Power Management
A 1V 32.1dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process
increase of the speed and data-rate achieved by 5G. A major challenge in 6G is to provide a large transmitter output power (Pout) with high energy efficiency and linearity from a limited supply voltage to overcome high p
ISSCC 2022
Session 19
Power Management
A 110-to-130GHz SiGe BiCMOS Doherty Power Amplifier with Slotline-Based Power-Combining Technique Achieving >22dBm Saturated Output Power and >10% Power Back-Off Efficiency
data-rates in wireless communications has driven the rapid development of silicon-based transceivers in the mm-wave and sub-THz bands. The broad available spectrum in D-band (110 to 170GHz) is attracting interest for sho
ISSCC 2022
Session 18
Power Management
A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3A/mm2 Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS
University of Lisboa, Lisbon, Portugal 1 2 The profile of portable and wearable devices keeps shrinking, demanding high current density power management integrated circuits. Switched-capacitor (SC) converters and buck co
ISSCC 2022
Session 18
Power Management
A 2−5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achieving 91% Efficiency at a Conversion Ratio of 12
High conversion-ratio (CR) DC-DC boost converters are essential for LED backlighting in smartphone and tablet displays. For realizing a high CR, a conventional boost (CB) converter [1] shown in Fig. 18.7.1 would use a la
ISSCC 2022
Session 18
Power Management
A 5V Input 98.4% Peak Efficiency Reconfigurable CapacitiveSigma Converter with Greater than 90% Peak Efficiency for the Entire 0.4~1.2V Output Range
computing cores with a wide-range sub-volt rail, the energy-efficient high and wide voltageconversion-ratio (VCR) converters are crucially important. In addition, low form factor and decent transient responses are also f
ISSCC 2022
Session 18
Power Management
A Monolithic 3:1 Resonant Dickson Converter with Variable Regulation and Magnetic-Based Zero-Current Detection and Autotuning
In the last decade, hybrid and resonant switched-capacitor (SC) converters have gone from a relatively unexplored concept to one that is gaining widespread adoption in a range of applications [1]. However, despite capabi
ISSCC 2022
Session 18
Power Management
A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2× Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD
University of Lisboa, Lisbon, Portugal 1 2 Automotive and industrial applications require a high-efficiency DC-DC converter to directly convert power from the 12V intermediate bus to a low-voltage point-of-load (PoL). Th
ISSCC 2022
Session 18
Power Management
A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9µs 1% Settling Time for a 3A/20ns Load Transient
12V/24V-to-1V power converters with high efficiency and fast transient responses are highly desirable in industrial and automotive applications. Double step-down (DSD, also known as series-capacitor) converters are among
ISSCC 2022
Session 18
Power Management
A 1.23W/mm2 83.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns
processors, a high-frequency and multi-phase (MP) integrated voltage regulator (IVR) using multiple inductors would be an ideal solution to deliver optimized power with rapid dynamic voltage scaling (DVS) [1-5]. Neverthe
ISSCC 2022
Session 17
Wireline I/O
A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process
MaxLinear, Carlsbad, CA 1 2 Increased data-rates and multi-lane SerDes implementations impose stringent conditions for CDRs to produce low-jitter clocking that is capable of managing frequency and phase offsets. Conseque
ISSCC 2022
Session 17
Wireline I/O
A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1dB FoM Using a Proportionally Divided Charge Pump
Beyond-10GHz frequency synthesizers are ubiquitous building blocks for today’s evergrowing wireless and wireline communication systems. To meet the stringent requirements on data-rate and modulation schemes, the phase no
ISSCC 2022
Session 17
Wireline I/O
A 56GHz 23mW Fractional-N PLL with 110fs Jitter
PAM-4 wireline transmitters operating at 224Gb/s can employ a 56GHz PLL for multiplexing. Such an environment poses several constraints on the design. First, the PLL rms jitter must be no more than a few percent of the s
ISSCC 2022
Session 17
Wireline I/O
A 10Gb/s Digital Isolator Using Coupled Split-Ring Resonators with 24kVpk Surge Capability and 100kV/µS Common-Mode Transient Immunity
High speed data links play a key role in industrial and medical systems. Galvanic isolation in high-speed links ensures the safety of human operators and instruments. Optoisolators generally achieve high voltage ratings
ISSCC 2022
Session 17
Wireline I/O
A 2.4pJ/b 100Gb/s 3D-Integrated PAM-4 Optical Transmitter with Segmented SiP MOSCAP Modulators and a 2-Channel 28nm CMOS Driver
David J. Thomson2, Martin Ebert2, Li Ke2, Graham T. Reed2, Azita Emami1 California Institute of Technology, Pasadena, CA University of Southampton, Southampton, United Kingdom 1 2 Data centers continue to require interco
ISSCC 2022
Session 17
Wireline I/O
A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS
cloud computing, have significantly driven the requirement for high transmission data rates. Polarization diversity coherent detection is an indispensable technique for realizing high-capacity transmission owing to its e
ISSCC 2022
Session 16
Digital Circuits
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS
University of Washington, Seattle, WA Ever-increasing global demand for communication bandwidth is incentivizing broader use of the millimeter wave (mm-Wave) frequency band which operates with carrier frequencies exceedi
ISSCC 2022
Session 16
Digital Circuits
A 65nm 63.3µW 15Mbps Transceiver with SwitchedCapacitor Adiabatic Signaling and Combinatorial-PulsePosition Modulation for Body-Worn Video-Sensing AR Nodes
virtual reality (VR) demands 1) high speed (>10Mbps) data transfer among wearable devices around the human body with 2) low transceiver (TRX) power consumption for longer lifetime, especially as communication energy/b is
ISSCC 2022
Session 16
Digital Circuits
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems
University of California, Santa Barbara, CA 1 2 cycle of operation, the stored spin value is distributed to the four directions based on the lattice graph hardware topology. Note that a spin input can be bypassed to the
ISSCC 2022
Session 16
Digital Circuits
Flex6502: A Flexible 8b Microprocessor in 0.8µm MetalOxide Thin-Film Transistor Technology Implemented with a Complete Digital Design Flow Running Complex Assembly Code
PragmatIC Semiconductor, Cambridge, United Kingdom 1 3 Integrated circuits based on thin-film transistors (TFTs) are attractive for use in many areas, including the Internet-of-Things (IoT), where ultra-thin circuits on
ISSCC 2022
Session 16
Digital Circuits
A 40nm 60.64TOPS/W ECC-Capable Compute-inMemory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems the sum-of-product error and correct the CIM error. As a result, we pay the penalty of serializing the read operation temporarily. (4) We localize the BL where the sum-ofproduct error has occurred by comparing the CIM result and the correct serial result.
Muya Chang1, Samuel D. Spetalnick1, Brian Crafton1, Win-San Khwa2, Yu-Der Chih3, Meng-Fan Chang2, Arijit Raychowdhury1 In Fig. 16.3.4, we illustrate physical design considerations, power plan, software programmability, a
ISSCC 2022
Session 16
AI / ML
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2 RRAM Binary/Compute-in-Memory Macro with 4.23× Improvement in Density and >75% Use of Sensing Dynamic Range
Compute-in-Memory (CIM) using emerging nonvolatile (eNVM) memory technologies, such as resistive random-access memory (RRAM), has been shown by several implemented macros to be an energy-efficient alternative to traditio
ISSCC 2022
Session 16
AI / ML
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware
Ram K. Krishnamurthy2, Mingoo Seok1 Columbia University, New York, NY Intel, Portland, OR 1 2 In-memory-computing (IMC) SRAM architecture has gained significant attention as it achieves high energy efficiency for computi
ISSCC 2022
Session 15
AI / ML
A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification
artificial intelligence (AI) for applications requiring image classification are in growing demand. However, the imager plus dedicated AI accelerator solution [1] suffers from the burdens of power and latency caused by t
ISSCC 2022
Session 15
Digital Processors
Analog Matrix Processor for Edge AI Real-Time Video Analytics
Mythic, Austin, TX Mythic, Redwood City, CA 1 2 One of the!salient!hurdles for wide adoption of!machine learning!(ML)!has been!efficient and high-performance!edge compute.!ML developers!use very large, expensive, and pow
ISSCC 2022
Session 15
AI / ML
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory
One of the notable trends in convolutional neural network (CNN) processor architecture is to embrace analog hardware to improve energy efficiency in performing multiply-andaccumulate (MAC). Prior works investigated charg
ISSCC 2022
Session 15
AI / ML
DIANA: An End-to-End Energy-Efficient DIgital and ANAlog Hybrid Neural Network SoC
Giuseppe M. Sarda1,2, Vikram Jain1, Man Shi1, Qilin Zheng1, Sebastian Giraldo1, Peter Vrancx2, Jonas Doevenspeck2, Debjyoti Bhattacharjee2, Stefan Cosemans2, Arindam Mallik2, Peter Debacker2, Diederik Verkest2, Marian Ve
ISSCC 2022
Session 15
AI / ML
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration
have been proposed for edge deep learning (DL) acceleration. They usually rely on analog CIM techniques to achieve highefficiency NN inference with low-precision INT multiply-accumulation (MAC) support
ISSCC 2022
Session 15
Digital Processors
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura Tokyo Institute of Technology, Yokohama, Japan *Equally Credited Authors (ECAs) Since the advent of the Lottery Ticket Hypothes
ISSCC 2022
Session 15
AI / ML
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning
Tianchan Guan2, Shengcheng Wang2, Dimin Niu2, Hongzhong Zheng2, Chixiao Chen1, Mingyu Wang1, Lihua Zhang1, Xiaoyang Zeng1, Qi Liu1, Yuan Xie2, Ming Liu1 Fudan University, Shanghai, China Alibaba DAMO Academy, Shanghai, C
ISSCC 2022
Session 15
AI / ML
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE
network (DNN) accelerators, few works have targeted improving the end-to-end performance of deeplearning tasks, where inter-layer pre/post-processing, data alignment and data movement across memory and processing units o
ISSCC 2022
Session 15
AI / ML
A Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC
Taeho Jeon1, Yesung Kang1, Heonsoo Lee1, Dongwoo Lee1, James Kim1, YoungJong Lee1, Sangkyu Park 1, Jun-Woo Jang2, SangHyuck Ha1, MinSeong Kim1, Jihoon Bang1, Suk Hwan Lim1, Inyup Kang1 Samsung Electronics, Hwaseong, Kore
ISSCC 2022
Session 14
Wireless
A 68.3% Efficiency Reconfigurable 400-/800-mW Capacitive Isolated DC-DC Converter with Common-Mode Transient Immunity and Fast Dynamic Response by Through-PowerLink Hysteretic Control
Galvanically isolated voltage regulators (GIVRs) are widely used in industrial automation, electric vehicles, and medical devices to deliver power to low-voltage circuits across isolated domains and ensure human safety a
ISSCC 2022
Session 14
Wireless
A 1.2W 51%-Peak-Efficiency Isolated DC-DC Converter with a Cross-Coupled Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI Standard
interference (EMI) is essential for isolated DC-DC converters that are used in the harsh industrial environments. To pass the CISPR 32 Class-B EMI standard, a 4-layer PCB with a stitching capacitor implemented by the int
ISSCC 2022
Session 14
Wireless
A 27W D2D Wireless Power Transfer System with Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control
University of Macau, Macau, China 1 2 Compact and high-power bidirectional wireless power transfer (WPT) systems are desirable for mobile device-to-device (D2D) wireless fast charging. Prior WPT solutions [1-3] with inte
ISSCC 2022
Session 14
Wireless
2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Channel Bandwidth and 93.6% Efficiency for 2G/3G/LTE/NR RF Power Amplifiers
Younghwan Choo, Seungchan Park, Young-Ho Jung, Jae-Young Ko, Takahiro Nomiyama, Jongbeom Baek, Jaeyeol Han, Sang-Han Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho Samsung Electronics, Hwaseong, Korea *
ISSCC 2022
Session 14
Wireless
A 2.5−5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with CapacitorAssisted Dual-Inductor Filtering
With the rapid developments in big data analytics, non-isolated 48V-to-1V converters offer a competitive choice to support the increased power consumptions in CPUs and memories. For realizing a small output-to-input conv
ISSCC 2022
Session 14
Wireless
A Monolithic GaN Direct 48V/1V AHB Switching Power IC with
Hybrid Gate Driving, and On-Die Temperature Sensing Dong Yan, D. Brian Ma University of Texas at Dallas, Richardson, TX With 10-to-100-fold lower switching figure of merit (QGate$RON), GaN transistors present tremendous
ISSCC 2022
Session 14
Wireless
A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-IntervalBased Dual-Mode Control
This paper presents an efficient and compact offline chip-scale power supply in 0.18µm high-voltage (HV) silicon-on-insulator (SOI) technology, suitable to supply IoT nodes, sensors, RF transceivers, LED strings, etc. fr