全部论文

Papers 2008–2026

共 3875 篇 ISSCC 论文,按年份倒序排列

ISSCC 2022 Session 29 AI / ML
A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing
Yang Wang1, Yubin Qin1, Dazheng Deng1, Jingchuan Wei1, Yang Zhou1,
code generator performs cascaded OR (AND) for positive (negative) data via 6b MSBs to generate a 6b signal with more 0-bits for small values to disable compressors. For exact mode, it modifies 2 BVs to “0” to make approx
ISSCC 2022 Session 29 Other
184QPS/W 64Mb/mm2 3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System
Dimin Niu1, Shuangchen Li1, Yuhao Wang1, Wei Han1, Zhe Zhang2, Yijin Guan2,
Tianchan Guan3, Fei Sun1, Fei Xue1, Lide Duan1, Yuanwei Fang1, Hongzhong Zheng1, Xiping Jiang4, Song Wang4, Fengguo Zuo4, Yubing Wang4, Bing Yu4, Qiwei Ren4, Yuan Xie1 Alibaba DAMO Academy, Sunnyvale, CA; 2Alibaba DAMO A
ISSCC 2022 Session 28 Memory
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter
Yeonwook Jung*1, Seongseop Lee*2, Hyojun Kim3, SeongHwan Cho4
SK hynix, Icheon, Korea 3 Korea Aerospace Research Institute, Daejeon, Korea 4 KAIST, Daejeon, Korea 1 2 *Equally Credited Authors (ECAs) With the increasing demand for low-power, high-speed DRAMs, LPDDR5 featuring a spe
ISSCC 2022 Session 28 Memory
A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces
Jaeyoung Seo1, Sooeun Lee2, Myungguk Lee1, Changjae Moon1, Byungsub Kim1
Samsung Electronics, Hwaseong, Korea SSC DECS input, the resulting clock and data paths are equally matched and the impact of the RX SN on the RX performance is minimized. In a conventional RX the sampling clock is gener
ISSCC 2022 Session 28 Memory
A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS
Sangyoon Lee, Jaekwang Yun, Suhwan Kim
Advances in virtual reality, artificial intelligence, and big data have increased demand for high-bandwidth memory. Accordingly, pre-fetch sizes have also increased with DRAM generations, meaning an increased number of g
ISSCC 2022 Session 28 Memory
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver
with Edge-Delayed Equalization, ECC, and Mismatch, Calibration for HBM Interfaces
Hyunsu Park1, Yoonjae Choi1, Jincheol Sim1, Jonghyuck Choi1, Youngwook Kwon1, Junyoung Song2, Chulwoo Kim1 Korea University, Seoul, Korea Incheon National University, Incheon, Korea 1 2 The bandwidth of parallel DRAM I/O
ISSCC 2022 Session 28 Memory
A 20 Gb/s/pin 1.18pJ/b 1149µm2 Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS
Changjae Moon, Jaeyoung Seo, Myungguk Lee, Iksu Jang, Byungsub Kim
matching method [3], the signal integrity problems are resolved by matching the farend terminal to 50Ω. This technique can improve the voltage swing of the inverters. The half-rate digital inputs are serialized by the re
ISSCC 2022 Session 28 Memory
A 16Gb 9.5Gb/s/pin LPDDR5X SDRAM with Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
Dae-Hyun Kim, Byungkyu Song, Hyun-a Ahn, Woongjoon Ko, Sunggeun Do,
Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Mi
ISSCC 2022 Session 28 Memory
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with
Merged-MUX TX, Optimized WCK Operation, and, Alternative-Data-Bus
frequency. When LF_ON is low (LF_ONB is high), the CML resistance and its current changes in the opposite direction and the center frequency is close to 12GHz (24Gb/s). As a result, the proposed frequency divider covers
ISSCC 2022 Session 28 Memory
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV AutoCalibration Scheme and Machine-Learning-Based Layout Optimization
Myeong-Jae Park, Ho Sung Cho, Tae-Sik Yun, Sangjin Byeon, Young Jun Koo,
Sangsic Yoon, Dong Uk Lee, Seokwoo Choi, Jihwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, Byung-Kuk Yoon, Young-Jun Park, Sang-muk Oh, Chang Kwon Lee, Tae-Kyun Kim, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun
ISSCC 2022 Session 27 mm-Wave
A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET
Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang,
Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sungjun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee, Byunghak Cho, Inyup Kang Samsung Elec
ISSCC 2022 Session 27 mm-Wave
A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm In-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode
Kaituo Yang, Chirn Chye Boon, Zhe Liu, Jiaming Piao, Ting Guo, Yangtao Dong,
out-of-band(OOB) linearity for sub-6GHz applications [1-3]. To achieve high linearity, one solution is to utilize current-mode direct conversion [1]. In this architecture, the low-noise amplifier (LNA) acts as a transcon
ISSCC 2022 Session 27 mm-Wave
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array
with Fast Beam-Switching Support for >30,000 Beams
Bodhisatwa Sadhu1, Arun Paidimarri1, Wooram Lee1, Mark Yeck1, Caglar Ozdag1, Yujiro Tojo2, Jean-Olivier Plouchart1, Xiaoxiong Gu1, Yusuke Uemichi2, Sudipto Chakraborty1, Yo Yamaguchi2, Ning Guan2, Alberto Valdes-Garcia1
ISSCC 2022 Session 27 mm-Wave
A Power-Efficient 24-to-71GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR
Jian Pang, Yi Zhang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila,
Multi-band receivers have been developed to realize reception over multiple 5G FR2 bands with minimized system size [1-3]. The conventional multi-band receiver achieves 20-to-44GHz frequency coverage with wide-band RF re
ISSCC 2022 Session 26 Quantum & Photonics
3D V-Cache: The Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU
John Wuu1, Rahul Agarwal2, Michael Ciraula1, Carl Dietz1, Brett Johnson1,
3D stacked product that attaches additional cache onto a high-performance processor through hybrid bonding, a technology that offers significant bandwidth and power benefits over state-of-the-art uBump based approaches.
ISSCC 2022 Session 26 Quantum & Photonics
Augmented Reality – The Next Frontier of Image Sensors and Compute Systems
Chiao Liu, Song Chen, Tsung-Hsun Tsai, Barbara De Salvo, Jorge Gomez
Augmented Reality (AR) will be the next great wave of human-oriented computing, dominating our relationship with the digital world for the next 50 years, much as personal computing has dominated the last 50 [1]. AR glass
ISSCC 2022 Session 26 Quantum & Photonics
Design Considerations for Superconducting Quantum Systems
George Zettles1,*, Scott Willenborg1,*, Blake R. Johnson2, Andrew Wack2, Brian Allison1
J. Watson Research Center, Yorktown Heights, NY 1 2 *Equally Credited Authors (ECAs) A distinguishing feature of quantum system engineering is that it must contend with the nature of “quantum processors” as extended obje
ISSCC 2022 Session 26 Quantum & Photonics
Beyond-Classical Computing Using Superconducting Quantum Processors Joseph Bardin
Google Quantum AI, Goleta, CA; University of Massachusetts, Amherst, MA, The Google Quantum AI team’s long-term goal is
quantum computer. Of the technologies available to implement the quantum processor at the core of such a system, solid-state superconducting circuits based on Josephson junctions (JJs) are among the strongest contenders.
ISSCC 2022 Session 25 Data Converters
An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
Tzuhan Wang*, Tian Xie*, Zhe Liu, Shaolan Li
*Equally Credited Authors (ECAs) With the combined merits of SAR and ∆Σ ADCs, the noise-shaping (NS) SAR architecture can achieve high resolution with a mild OSR, making it versatile for a wide range of applications. Non
ISSCC 2022 Session 25 Data Converters
A 28nm 6GHz 2b Continuous-Time ∆Σ ADC with -101dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction
Muhammed Bolatkale1, Robert Rutten1, Hans Brekelmans1, Shagun Bajoria1,
continuous-time ∆Σ modulators with a (theoretically) linear 1b DAC, have demonstrated better than -100dBc THD in a bandwidth range from tens of kHz for audio to tens of MHz for broadband AM/FM radio [1]. To achieve both
ISSCC 2022 Session 25 Data Converters
A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ∆Σ ADC in 40nm CMOS
Qilong Liu1,2, Lucien Breems1,2, Chenming Zhang1,2, Shagun Bajoria1,2,
University of Technology, Delft, The Netherlands 1 2 In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hu
ISSCC 2022 Session 25 Data Converters
A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS
Calvin Yoji Lee, Un-Ku Moon
Demands for battery-powered consumer electronics have driven the evolution of powerefficient high-resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to increasing battery
ISSCC 2022 Session 25 Data Converters
A 2.87µW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC using FIA with Dynamic-Body-Biasing Assisted CLS Technique
Yaopeng Hu1, Yibo Zhao1, Wanyuan Qu1, Le Ye2, Menglian Zhao1, Zhichao Tan1
Peking University, Beijing, China 1 2 Micro-power ∆Σ modulators are suitable for low-bandwidth, high-precision applications, such as smart sensors, biomedical signal processing and battery-powered IoT devices. They achie
ISSCC 2022 Session 25 Data Converters
A 4.4µW 2.5kHz-BW 92.1dB-SNDR 3rd-Order VCO-Based ADC with Pseudo Virtual Ground Feedforward Linearization
Corentin Pochet, Drew A. Hall
The rise of the internet-of-things and distributed sensor nodes with machine-learning and edge processing are driving the need for low-power, high-precision ADCs. These highly digital systems are best implemented in adva
ISSCC 2022 Session 24 RF & Wireless
An LPWAN Radio with a Reconfigurable Data/Duty-CycledWake-Up Receiver
Keun-Mok Kim1, Kyung-Sik Choi1, Hyunki Jung1,2, Byeonghun Yun1, Subin Kim2,
Demands for the low-power wide-area network (LPWAN) are increasing along with a growing market for low data-rate, long-range internet of things (IoT) applications. Although many radios have been released for various LPWA
ISSCC 2022 Session 24 RF & Wireless
A 110µW 2.5kb/s -103dBm-Sensitivity Dual-Chirp Modulated ULP Receiver Achieving -41dB SIR
Milad Moosavifar*, Jaeho Im*, Trevor Odelberg, David Wentzloff
*Equally-Credited Authors (ECAs) As the number of devices connected to the IoT has increased rapidly in recent years, stricter requirements have been placed on IoT radio receivers (RX) that can operate in an increasingly
ISSCC 2022 Session 24 RF & Wireless
A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dB
Haijun Shao1, Pui-In Mak1, Gengzhen Qi2, Rui P. Martins1,3
University of Lisboa, Lisbon, Portugal 1 3 Ultra-low-power short-range radios are the cornerstone of building a world with the Internet-of-Everything connectivity. To secure a high sensitivity at a sub-mW power budget, s
ISSCC 2022 Session 24 RF & Wireless
A 22nm 0.84mm2 BLE Transceiver with Self IQ-Phase Correction Achieving 39dB Image Rejection and On-Chip Antenna Impedance Tuning
reduce area and power consumption. In order to make 50%-duty LO signals for the TXPA and the PLL, we use NORs with latch
Figure 24.4.4 shows the proposed AIT providing optimum impedance matching for RX Kenichi Shibata, Hiroaki Matsui, Hironori Asano, Yuichi Kusaka, Keisuke Ueda, and TX independently with a wide impedance tunability. In TX
ISSCC 2022 Session 24 RF & Wireless
A 6.5-to-10GHz IEEE 802.15.4/4z-Compliant 1T3R UWB Transceiver
Run Chen, Yuzhong Xiao, Yonggang Chen, Hua Xu, Peng Yu, Qi Peng, Xian Li,
Xiaofeng Guo, Jianlong Huang, Nansong Li, Xueqing Hu, Rongde Ou, Wenzhe Liu, Bei Chen, Wen Zhang, Xiaofeng Xin, Bingcai Zhao, ZhenQi Chen Newradio Technology, Shenzhen, China Ultra-wideband (UWB) technology differentiate
ISSCC 2022 Session 24 RF & Wireless
A 1.66Gb/s and 5.8pJ/b Transcutaneous IR-UWB Telemetry System with Hybrid Impulse Modulation for Intracortical Brain-Computer Interfaces
Minyoung Song1, Yu Huang1,2, Yiyu Shen1, Chengyao Shi1,3, Arjan Breeschoten1,
Mario Konijnenburg1, Huib Visser1, Jac Romme1, Barundeb Dutta4, Morteza S. Alavi2, Christian Bachmann1, Yao-Hong Liu1 imec-Netherlands, Eindhoven, The Netherlands Delft University of Technology, Delft, The Netherlands 3
ISSCC 2022 Session 24 RF & Wireless
A Long-Range Narrowband RF Localization System with a Crystal-Less Frequency-Hopping Receiver
Chien-Wei Tseng1, Demba Komma1, Kuan-Yu Chen1, Rohit Rothe1, Zhen Feng1,
Semiconductor Japan, Yokohama, Japan 1 2 Emerging IoT applications, such as asset tracking and first-responder rescue operation, require a new localization solution that achieves decimeter-level accuracy for long range (
ISSCC 2022 Session 23 Clocking & PLLs
A 68.6fsrms-Total-Integrated-Jitter and 1.56µs-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
Simone Mattia Dartizio*1, Francesco Buccoleri*1, Francesco Tesolin1,
Luca Avallone2, Alessio Santiccioli1, Agata Iesurum3, Giovanni Steffan2, Dmytro Cherniak2, Luca Bertulessi1, Andrea Bevilacqua3, Carlo Samori1, Andrea Leonardo Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan,
ISSCC 2022 Session 23 Clocking & PLLs
A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoM
Dihang Yang1, David Murphy1, Hooman Darabi1, Arya Behzad1, Asad Abidi2,
>25GHz inevitably faces the problems of a large closed-loop gain fvco/fref = N. Phase noise and spurs on the reference input and from other sources in the loop referred to its input are amplified by N. A narrow loop band
ISSCC 2022 Session 23 Clocking & PLLs
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a TimeMode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs
Zhong Gao1, Jingchu He1, Martin Fritz2, Jiang Gong1, Yiyu Shen1, Zhirui Zong1,
Peng Chen3, Gerd Spalink2, Ben Eitel2, Ken Yamamoto4, Robert Bogdan Staszewski1,3, Morteza S. Alavi1, Masoud Babaie1 Delft University of Technology, Delft, The Netherlands Sony Europe, Stuttgart, Germany 3 University Col
ISSCC 2022 Session 23 Clocking & PLLs
A 188fsrms-Jitter and –243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
Chanwoong Hwang*, Hangi Park*, Taeho Seong, Jaehyouk Choi
*Equally Credited Authors (ECAs) Modern SoCs for advanced wireless/wired applications integrate an increasing number of PLLs. 5G TRXs require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Mu
ISSCC 2022 Session 23 Clocking & PLLs
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur
Tsung-Hsien Tsai1, Ruey-Bin Sheen1, Sheng-Yun Hsu1, Ya-Tin Chang1,
communications, require deep-subpicosecond integrated phase jitter [1]. Their in-band phase noise (PN) can be adversely affected by flicker noise and a large feedback frequency-division ratio, N. Cascaded PLLs are a rece
ISSCC 2022 Session 22 AI / ML
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AIoT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique
Ying Liu*1, Zhixuan Wang*1,2, Wei He1, Linxiao Shen1, Yihan Zhang1,
Peiyu Chen1, Meng Wu1, Hao Zhang1, Peng Zhou3, Jinguang Liu3, Guangyu Sun1, Jiayoon Ru1, Le Ye1,2, Ru Huang1 Peking University, Beijing, China Advanced Institute of Information Technology of Peking University, Hangzhou,
ISSCC 2022 Session 22 Power Management
A 23µW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction
Kwantae Kim*1, Chang Gao*1, Rui Graça1, Ilya Kiselev1, Hoi-Jun Yoo2,
interfaces on acoustic Internet-of-Things (IoT) sensor nodes and mobile devices require integrated low-power always-on wake-up functions such as Voice Activity Detection (VAD) and Keyword Spotting (KWS) to ensure longer
ISSCC 2022 Session 22 AI / ML
A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS
Feifei Chen1, Ka-Fai Un1, Wei-Han Yu1, Pui-In Mak1, Rui P. Martins1,2
University of Lisboa, Lisbon, Portugal 1 2 An ultra-low-power always-on voice activity detector (VAD) is the key enabler of acoustic sensing in wearables. The VAD listens to the environment and wakes up the main system o
ISSCC 2022 Session 22 Power Management
A WiFi and Bluetooth Backscattering Combo Chip Featuring Beam Steering via a Fully-Reflective Phased-Controlled Multi-Antenna Termination Technique Enabling Operation Over 56 Meters
Shih-Kai Kuo*, Manideep Dunna*, Dinesh Bharadia, Patrick P. Mercier
*Equally-Credited Authors (ECAs) Many envisioned IoT applications are not realizable today due to the mW-level power burden of wireless communication circuits for the most popular consumer standards: WiFi and BLE. To hel
ISSCC 2022 Session 22 Power Management
A Cryogenic SiGe BiCMOS Hybrid Class B/C Mode-Switching VCO Achieving 201dBc/Hz Figure-of-Merit and 4.2GHz Frequency Tuning Range
Yatao Peng1,2, Andrea Ruffino1, Jad Benserhir1, Edoardo Charbon1
Southern University of Science and Technology, Shenzhen, China 1 2 The interconnects between a quantum processor and control electronics can be made more compact and reliable by placing classical circuits at cryogenic te
ISSCC 2022 Session 22 Power Management
A Cryo-CMOS Controller IC with Fully Integrated Frequency Generators for Superconducting Qubits
Kiseo Kang*, Donggyu Minn*, Seunghun Bae, Jaeho Lee, Seongun Bae,
Extensive research on quantum mechanics in past decades has successfully paved the way towards the disruptive technology of quantum computing. A further step to the realization of a fault-tolerant scalable quantum comput
ISSCC 2022 Session 22 Power Management
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology
David J. Frank1, Sudipto Chakraborty1, Kevin Tien1, Pat Rosno2, Thomas Fox1,
Mark Yeck1, Joseph A. Glick1, Raphael Robertazzi1, Ray Richetta2, John F. Bulzacchelli1, Daniel Ramirez2, Dereje Yilma2, Andrew Davies2, Rajiv V. Joshi1, Shawn D. Chambers2, Scott Lekuch1, Ken Inoue1, Devin Underwood1, D
ISSCC 2022 Session 20 RF & Wireless
A 145.2dB-DR Baseline-Tracking Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring
Chan Sam Park1, Hyunjoong Kim1, Kwangmuk Lee1, Dae Sik Keum2,
separate I/Q channels. A bio-impedance input phase (φpst) varies depending on its electrode conditions such as configuration (2E or 4E) and environment (dry or wet). However, once the conditions are set and maintained, t
ISSCC 2022 Session 20 RF & Wireless
An SpO2 Sensor Using Reconstruction-Free Sparse Sampling for 70% System Power Reduction
Sina Faraji Alamouti1, Cem Yalcin1, Jasmine Jan1, Jonathan Ting1, Ana C. Arias1,
oxygenation (SpO2) is a measure of hypoxemia and a sign of problems relating to breathing and circulation. Progressive drop in arterial SpO2 can be an early indicator of severe disease in COVID-19 patients [1]. A hypoxic
ISSCC 2022 Session 20 RF & Wireless
A Reconfigurable Sub-Array Multiplexing Microelectrode
Array System with 24,320 Electrodes and 380 Readout, Channels for Investigating Neural Communication
Ji-Hyoung Cha1, Jee-Ho Park1, Yongjae Park1, Hyogeun Shin2, Kyeong Seob Hwang2, Il-Joo Cho2, Seong-Jin Kim1 Ulsan National Institute of Science and Technology, Ulsan, Korea Korea Institute of Science and Technology, Seou
ISSCC 2022 Session 20 RF & Wireless
A Miniaturized Wireless Neural Implant with Body-Coupled Data Transmission and Power Delivery for Freely Behaving Animals
Changuk Lee*1, Byeongseol Kim*2, Jejung Kim1, Sangwon Lee3,4, Taejune Jeon1,
University, Incheon, Korea, 4gBrain, Incheon, Korea *Equally Credited Authors (ECAs) 1 3 Miniaturized neural implants for monitoring neurological disorders have been investigated as a promising alternative to the neural
ISSCC 2022 Session 20 RF & Wireless
A 256-Channel 0.227µJ/class Versatile Brain Activity Classification and Closed-Loop Neuromodulation SoC with 0.004mm2-1.51µW/channel Fast-Settling Highly Multiplexed Mixed-Signal Front-End
Uisub Shin1,2, Laxmeesha Somappa1, Cong Ding1, Bingzhao Zhu1,2,
Yashwanth Vyza1, Alix Trouillet1, Stéphanie P. Lacour1,3, Mahsa Shoaran1,3 EPFL, Lausanne, Switzerland Cornell University, Ithaca, NY 3 Center for Neuroprosthetics, Geneva, Switzerland 1 2 Closed-loop neuromodulation can
ISSCC 2022 Session 20 RF & Wireless
A 0.7V 17fJ/step-FOMW 178.1dB-FOMSNDR 10kHz-BW 560mVPP True-ExG Biopotential Acquisition System with Parasitic-Insensitive 421MΩ Input Impedance in 0.18µm CMOS
Sehwan Lee1, Yoonsung Choi1, Geunha Kim1, Seungyeob Baik1,
Taeryoung Seol1, Homin Jang1, Doyoung Lee1, Minkyu Je2, Ji-Woong Choi1, Arup K. George1, Junghyup Lee1 Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea KAIST, Daejeon, Korea 1 2 Insights derived from epi
ISSCC 2022 Session 20 RF & Wireless
A Time-Division Multiplexed 8-Channel Non-Contact ECG Recording IC with a Common-Mode Interference Tolerance of 20VPP
Kyu-Jin Choi, Jae-Yoon Sim
There has been increasing demand for a low-power wearable device to perform longterm ambulatory monitoring of electrocardiogram (ECG). However, for a wearable device to be a convenient continuous recording system in one’