ISSCC 2023
Session 10
Data Converters
A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping
Chi-hang Chan*1, R. P. Martins1,3 University of Macau, Macau, China Xidian University, Xi’an, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal *Equally Credited Authors (ECAs) 1 2 Emerging wirele
ISSCC 2023
Session 10
Data Converters
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer
good energy efficiency. Lately, the incremental ADC is drawing rising attention by favoring system integration with its easy multiplexing and simple digital filtering. By combining a low-power SAR with a low-distortion ∆
ISSCC 2023
Session 10
Data Converters
A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-PredictionUnrolled Scheme
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Shaping the interstage gain error in two-step oversampling ADCs has demonstrated a decent error suppression with a variety of mechanisms. The intersta
ISSCC 2023
Session 10
Data Converters
A Rail-to-Rail 12MS/s 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting
utilizing the power-efficient SAR topology at medium speed (1-20MSps) [1-4]. However, highresolution discrete-time Nyquist ADCs are difficult to drive, especially at high sampling frequencies, due to their large input sa
ISSCC 2023
Session 10
Data Converters
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 High-speed pipelined ADCs rely on fast and accurate residue amplification which often necessitates calibration, thus suffering from potential converge
ISSCC 2023
Session 10
Data Converters
A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness
Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,3 University of Macau, Macau, China Xidian University, Xi’an, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 A highly integrated wireline receiver w
ISSCC 2023
Session 10
Data Converters
A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations
Direct RF sampling reduces complexity for receiver design. However, SNDR and speed specifications of its ADCs are stringent, which makes the time-interleaved (TI) ADC attractive for the required sampling rate. There is a
ISSCC 2023
Session 1
Plenary
5G Drives Exponential Increase in Processing Needs Across all Industries Erik Ekudden
The extreme development of semiconductor-based compute technologies has not escaped anyone but the fact that mobile communications has followed a similar trajectory may be less obvious to most. Over five generations of m
ISSCC 2023
Session 1
Plenary
EU Chips Act Drives Pan-European Full-Stack Innovation Partnerships Jo De Boeck
Germany 1. The Impact of Semiconductors and the European Chips Act In every aspect of our life and society, semiconductors play a major role and that impact is set to increase even further. The pandemic in conjunction wi
ISSCC 2023
Session 1
Plenary
Shape the World with Mixed-Signal Integrated
Introduction The last 50 years has been an era where analog equipment has been replaced by digital devices. LP records have been replaced by Compact Discs, NTSC and PAL TV systems have been replaced by digital TVs, VHS v
ISSCC 2023
Session 1
Plenary
Innovation For the Next Decade of Compute Efficiency
AMD, Fort Collins, CO2 1.1 Introduction With high-performance computing becoming an increasingly essential part of modern life, efficiently delivering improvements in compute performance is the defining challenge for our
ISSCC 2022
Session 9
mm-Wave
A Highly Power Efficient 2×3 PIN-Diode-Based Intercoupled THz Radiating Array at 425GHz with 18.1dBm EIRP in 90nm SiGe BiCMOS
Efficient THz generation in silicon technologies has been of great interest over the recent years, as it enables an integrated low-cost solution for sensing, radar, communication, and spectroscopy [1]. Due to the limited
ISSCC 2022
Session 9
mm-Wave
A 53.6-to-60.2GHz Many-Core Fundamental Oscillator with Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS
The millimeter-wave (mm-wave) high-speed wireless communication has placed stringent requirements on the phase-noise performance of the local oscillators (LO), especially when a high-order modulation such as 1024-QAM is
ISSCC 2022
Session 9
mm-Wave
A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoMA in 22nm FinFET
and an octave frequency-tuning range (FTR) are required for multistandard communication devices, software-defined radios, and wireline data links. A viable popular approach is to exploit multicore mode-switching VCOs for
ISSCC 2022
Session 9
mm-Wave
Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM
The phase noise of oscillators limits the modulation Error Vector Magnitude (EVM) in wireless communications and the SNR in high-speed data converters. The issue is particularly critical in the wireless infrastructure fo
ISSCC 2022
Session 8
RF & Wireless
A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS
Spain 1 2 At the center of autonomous driving and range and motion sensing in industrial and healthcare applications are FMCW RADARs, which provide the means for object range and velocity estimation. With future widespre
ISSCC 2022
Session 8
RF & Wireless
A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup
Sarah Shahraini, Thao Xiong, Dan Lake, Stefano Pellerano, Jason Mix, Nasser Kurd, Mohamed Abdel-moneum, Brent Carlton Intel, Hillsboro, OR A high-performance clock generator with extremely low jitter, area, and power con
ISSCC 2022
Session 8
RF & Wireless
A 0.0078mm2 3.4mW Wideband Positive-Feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting Gm Boosting
γ/(gm2+gm3)RS. Accordingly, the noise factor of the LNA, F can be given by Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo Nanyang Technological University, Singapore, Singapore The noise figur
ISSCC 2022
Session 7
Memory
A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices
Bo-Rong Lin1, Huai-Mu Wang1, Yen-Po Lin1, Yu-Chao Lin1, Chih-Chang Hsieh1, Chia-Ming Hu1, Yi-Ting Lai1, Han-Sung Chen1, Yuan-Hao Chang4, Hsiang-Pang Li1, Tei-Wei Kuo3,5, Keh-Chung Wang1, Meng-Fan Chang2, Chun-Hsiung Hung
ISSCC 2022
Session 7
Memory
A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface
Yeong Seon Kim, Daehoon Na, Sara Choi, Youngsun Song, Jonghoon Lee, Hyunjun Yoon, Kangbin Lee, Byunghoon Jeong, Sanglok Kim, Junhong Park, Cheon An Lee, Jaeyun Lee, Jisang Lee, Jin Young Chun, Joonsuc Jang, Younghwi Yang
ISSCC 2022
Session 7
Memory
A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array
Jonathan Pabustan1, Joe Xu1, Srinivas Deshmukh1, Kim-Fung Chan1, Michael Piccardi1, Kevin Xu1, Guan Wang1, Kaveh Shakeri1, Vipul Patel1, Tomoko Iwasaki1, Tongji Wang1, Padma Musunuri1, Carl Gu1, Ali Mohammadzadeh1, Ali G
ISSCC 2022
Session 7
Memory
A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory with a 2.4-Gb/s I/O Speed Interface
Pradeep Anantula1, Stanley Jeong1, Anirudh Amarnath1, Siddhesh Darne1, Sneha Bhatia2, Tianyu Tang1, Aditya Arya1, Naman Rastogi1, Naoki Ookuma1, Hiroyuki Mizukoshi1, Alex Yap1, Demin Wang1, Steve Kim1, Yonggang Wu1, Min
ISSCC 2022
Session 6
Wireline I/O
A 50Gb/s PAM-4 Bi-Directional Plastic Waveguide Link with Carrier Synchronization Using PI-Based Costas Loop
Huxian Jin1, Tai young Kim1, Woohyun Kwon2, Kyoohyun Lim1, Konan Kwon1, Chang-Ahn Kim1, Taeho Kim1, Jun Gi Jo1, Jake Eu1, Sean Park1, Hyeon-Min Bae2 Point2 technology, Seoul, Korea KAIST, Daejeon, Korea of the I-DCM conv
ISSCC 2022
Session 6
Wireline I/O
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS
M. Sorna1, M. Wielgos1, P. B. Ramakrishna2, S. Shi3, S. Parker1, U. K. Shukla2, W. Kelly1, W. Su3, Z. Yu4 Marvell, Hopewell Junction, NY Marvell, Bangalore, India 3 Marvell, Shanghai, China 4 Marvell, Santa Clara, CA bet
ISSCC 2022
Session 6
Wireline I/O
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology
Kumar Thasari1, Saurabh Surana1, Jun Won Jung1, Jaehun Jeong1, Heng Zhang1, Anand Vasani1, Yonghyun Shim1, Zhi Huang1, Adesh Garg1, Hsiang-bin Lee1, Bo Wu2, Feifei Liu1, Ray Wang1, Matthew Loh2, Alex Wang2, Mario Caresos
ISSCC 2022
Session 6
Wireline I/O
A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS
entertainment has never been fulfilled. Mixed-signal PAM-4 transceivers prevail over their ADC-DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high-loss links. Typically, a
ISSCC 2022
Session 6
Wireline I/O
A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET
D. Zhou1, D. Visani1, E. Hsiao1, F. Chu1, F. Lu1, G. Cui1, H. Zhang1, H. Wang1, H. Zhao1, J. Lin1, J. Gu1, L. Luo2, L. Jiang1, M. Singh1, M. Gambhir1, M. Hasan1, M. Wu1, M. J. Yoo1, P. Liu1, S. Kollu1, T. Ye2, X. Zhao2,
ISSCC 2022
Session 6
Wireline I/O
A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation
Itamar Levin1, Ari Gordon1, Yaniv Sabag1, Vitali Rahinski1, Gadi Ori1, Noam Familia1, Stas Litski1, Tali Warshavsky1, Udi Virobnik1, Yeshayahu Horwitz1, Ajay Balankutty2, Shiva Kiran2, Samuel Palermo3, Peng Mike Li4, Ari
ISSCC 2022
Session 34
Hardware Security
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/DualCore/Blind-Bulk AES Engine in Intel 4 CMOS
Amit Agarwal, Vivek K. De, Sanu K. Mathew Intel, Hillsboro, OR Power and electromagnetic (EM) side-channel attacks (SCA) exploit data-dependent power consumption from cryptographic engines to extract embedded secret keys
ISSCC 2022
Session 34
Hardware Security
A Threshold-Implementation-Based Neural-Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks
Indian Institute of Science, Bengaluru, India 3 Analog Devices, Wilmington, MA 1 2 Neural network (NN) hardware accelerators are being widely deployed on low-power IoT nodes for energy-efficient decision making. Embedded
ISSCC 2022
Session 34
AI / ML
Side-Channel Attack Counteraction via Machine LearningTargeted Power Compensation for Post-Silicon HW Security Patching
Southern University of Science and Technology, Shenzhen, China 1 2 *Equally Credited Authors (ECAs) Counteracting side-channel attacks has become a basic requirement in secure integrated circuits handling physical or sen
ISSCC 2022
Session 34
Hardware Security
A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems
era, post-quantum cryptography (PQC) processors are required to ensure quantum-secure communication and e-commerce with high throughput, while maintaining adequate flexibility to execute different crypto-primitives, such
ISSCC 2022
Session 33
AI / ML
DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms
RGBD data and 3D bounding-box (BB) information for accurate navigation and seamless interaction with the surrounding environment. Specifically, the extraction of RGB-D data and 3D BB needs to be done in real-time (> 30fp
ISSCC 2022
Session 33
Digital Processors
A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display
provides a fullparallax glasses-free 3D viewing experience. Compared to other autostereoscopic techniques, factored displays provide greater depth of field, larger field of view, and smoother perspective switching withou
ISSCC 2022
Session 33
Digital Processors
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction
Epilepsy is a common neurodegenerative disease that affects more than 50 million people worldwide. Closed-loop neuromodulation is a promising solution to epileptic seizure control through an implantable device that deliv
ISSCC 2022
Session 33
Digital Processors
A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication
Gi-Jin Kang, Junho Kim, Shin-Wuk Kang, Uijong Song, Chang-Yeon Cho, Junseo Lee, Kyungduck Seo, Seongwook Song, Sung Ung Kwak Samsung Electronics, Hwaseong, Korea Biometric authentication is a proven and practical way to
ISSCC 2022
Session 32
Other
A Multimode 157µW 4-Channel 80dBA-SNDR Speech-Recognition Frontend with Self-DOA Correction Adaptive Beamformer
Mohammad R. Haghighat2, Michael P. Flynn1 *Equally-Credited Authors (ECAs) 1 University of Michigan, Ann Arbor, MI; 2Intel, Santa Clara, CA Beamforming with multiple microphones is essential for Automatic Speech Recognit
ISSCC 2022
Session 32
Other
An Electronically Tunable Multi-Frequency Air-Coupled CMUT Receiver Array with sub-100µPa Minimum Detectable Pressure Achieving a 28kb/s Wireless Uplink Across a Water-Air Interface
Oceans play a critical role in our ecosystem – they regulate weather and global temperature, serve as the largest carbon sink and the greatest source of oxygen. Maintaining ocean health is of paramount importance and has
ISSCC 2022
Session 32
Other
A 1.2mW/channel 100µm-Pitch-Matched Transceiver ASIC with Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3D Ultrasound Imaging
Johan G. Bosch2, Martin D. Verweij1,2, Nico de Jong1,2, Michiel A. P. Pertijs1 Delft University of Technology, Delft, The Netherlands 2 Erasmus MC, Rotterdam, The Netherlands 1 The integration of 2D ultrasonic transducer
ISSCC 2022
Session 32
Other
A Pitch-Matched ASIC with Integrated 65V TX and Shared Hybrid Beamforming ADC for Catheter-Based High-FrameRate 3D Ultrasound Probes
Zu-Yao Chang1, Chao Chen1, Hendrik Vos1,2, Hans Bosch2, Martin Verweij1,2, Nico de Jong1,2, Michiel Pertijs1 Delft University of Technology, Delft, The Netherlands Erasmus MC, Rotterdam, The Netherlands 1 2 Intra-cardiac
ISSCC 2022
Session 32
Other
BatDrone: A 9.83M-focal-points/s 7.76µs-Latency Ultrasound Imaging System with On-Chip Per-Voxel RX Beamfocusing for 7m-Range Drone Applications
Yilong#Dong1, Miaolin#Zhang1, Zhuoyue#Li1, Kian#Ann#Ng3, Chne-Wuen#Tsai1, Lian#Zhang1, Longyang#Lin4, Liwei#Lin2, Jerald#Yoo1,5 National University of Singapore, Singapore, Singapore University of California, Berkeley, C
ISSCC 2022
Session 31
Other
A -91dB THD+N Resistor-Less Class-D Piezoelectric Speaker Driver Using a Dual Voltage/ Current Feedback for LC Resonance Damping
Goodix Technology, Nijmegen, The Netherlands 1 2 Piezoelectric speakers are gaining popularity on account of their improving form-factor and audio quality, making them a good fit for many audio applications such as in te
ISSCC 2022
Session 31
Other
A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-VoltageScaling Volume Control and Series-Connected DSM
Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power (POUT) are desired. However, in mobile devices, the POUT i
ISSCC 2022
Session 31
Other
A -117dBc THD (-132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors
inter-symbol interference (ISI) [1,2]; 2) 3rd-order harmonic distortion (HD3) due to the 2nd-order nonlinearity of poly resistors; and 3) Cross-over distortion (COD) arising from limited amplifier inner-loop gain due to
ISSCC 2022
Session 30
Power Management
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer
compute/memory and analog/mixed-signal circuits such as SerDes transceivers, RF/wireless front-end, PLLs, sensors, etc. On-chip low-dropout regulators (LDOs) isolate the input Vin noise from switching DC-DC converters po
ISSCC 2022
Session 30
Power Management
A Reconfigurable Series-Parallel Charger for Dual-Battery Applications with 89W 97.7% Efficiency in Direct Charging Mode
foldable phones, the number of smart phones that use two batteries are gradually increasing [1]. In ultra-fast charging applications, two batteries are connected in series as shown in Fig. 30.3.1. The output voltage of t
ISSCC 2022
Session 30
Power Management
A 130V Triboelectric Energy-Harvesting Interface in 0.18µm BCD with Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Technique
vibration energy have gained popularity as a next-generation energy source owing to their numerous advantages including flexibility, high conversion efficiency, and low cost. However, ultrahigh instantaneous open-circuit
ISSCC 2022
Session 30
Power Management
A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy-Harvesting and Power-Management
Shuo Li, Xinjian Liu, Benton H. Calhoun University of Virginia, Charlottesville, VA Energy harvesting and power management units (EHPMUs) are gaining popularity for self-powered Internet-of-Things (IoT) applications due
ISSCC 2022
Session 29
AI / ML
ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales
The robustness of autonomous inference-only devices deployed in the real world is limited by data distribution changes induced by different users, environments, and task requirements. This challenge calls for the develop
ISSCC 2022
Session 29
AI / ML
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes
state-of-the-art results in many fields, like natural language processing and computer vision, but their large number of matrix multiplications (MM) result in substantial data movement and computation, causing high laten