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ISSCC 2023 Session 2 Digital Processors

“Zen 4”: The AMD 5nm 5.7GHz x86-64 Microprocessor Core

Benjamin Munger1, Kathy Wilcox1, Jeshuah Sniderman1, Chuck Tung1,

Brett Johnson2, Russell Schreiber3, Carson Henrion2, Kevin Gillespie1, Tom Burd4, Harry Fair1, David Johnson2, Jonathan White1, Scott McLelland1, Steven Bakke1, Javin Olson1, Ryan McCracken1, Matthew Pickett2, Aaron Hori

ISSCC 2023 Session 19 Other

A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler

Dongwon You , Xi Fu , Xiaolin Wang , Yuan Gao , Wenqian Wang ,

Jun Sakamaki1, Hans Herdian1, Sena Kato1, Michihiro Ide1, Yuncheng Zhang1, Ashbir Aviat Fadila1, Zheng Li1, Chun Wang1, Yun Wang1, Jumpei Sudo2, Makoto Higaki2, Nahoka Kawaguchi2, Masaya Nitta2, Soichiro Inoue2, Takashi

ISSCC 2023 Session 19 Other

A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation

Xi Fu1, Dongwon You1, Xiaolin Wang1, Michihiro Ide1, Yuncheng Zhang1,

Jun Sakamaki1, Ashibir Aviat Fadila1, Zheng Li1, Yun Wang1, Jumpei Sudo2, Makoto Higaki2, Soichiro Inoue2, Takashi Eishima2, Takashi Tomura1, Jian Pang1, Hiroyuki Sakai1, Kenichi Okada1, Atsushi Shirane1 Tokyo Institute

ISSCC 2023 Session 19 Other

An Interferer-Tolerant Harmonic-Resilient Receiver with >+10dBm 3rd-Harmonic Blocker P1dB for 5G NR Applications

Soroush Araei, Shahabeddin Mohin, Negar Reiskarimian

The sub-6GHz spectrum is heavily utilized by 5G New Radio (NR), as well as traditional cellular and WiFi technologies. A major challenge in designing SAW-less wideband radio receivers (especially targeting the sub-2GHz r

Massachusetts Institute of Technology, Cambridge, MA

ISSCC 2023 Session 18 Wireless

A 4×4 607GHz Harmonic Injection-Locked Receiver Array Achieving 4.4pW/√Hz NEP in 28nm CMOS is beneficial for THz applications as they typically have limited available illumination power.

Ariane De Vroede, Patrick Reynaert

As illustrated in Fig. 18.4.4, the angular resolution of the optical setup depends on two properties: the pixel-beam-separation (PBS) angle φPBS and the half-power beamwidth (HPBW) θHPWB. For the optical setup in Fig. 18

ISSCC 2023 Session 18 Wireless

71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency

Bingzheng Yang, Zhixian Deng, Huizhen Jenny Qian, Xun Luo

The growing demand of millimeter-wave (mm-wave) wireless transmission leads to the requirement of low-cost, high-efficiency, and multi-Gb/s data-rate wireless systems. Allocated by the Federal Communications Commission (

University of Electronic Science and Technology of China, Chengdu, Chi

ISSCC 2023 Session 18 Wireless

A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET

Abhishek Agrawal1, Amy Whitcombe2, Woorim Shin3, Ritesh Bhat1,

Somnath Kundu1, Peter Sagazio1, Hariprasad Chandrakumar1, Thomas Brown1, Brent Carlton1, Christopher Hull4, Steven Callender1, Stefano Pellerano1 Intel, Hillsboro, OR, 2Intel, Santa Clara, CA, 3now with Apple, Sunnyvale,

ISSCC 2023 Session 18 Wireless

A W-Band Transceiver Array with 2.4GHz LO Synchronization Enabling Full Scalability for FMCW Radar

Jingzhi Zhang, Ajay Singhvi, Sherif S. Ahmed, Amin Arbabian

Closing the angular resolution gap between CMOS radar and optical imaging systems can enable an entirely new cost-effective radar-centric perception solution, but requires extremely large transceiver (TRX) arrays to achi

Stanford University, Stanford, CA

ISSCC 2023 Session 17 Data Converters

A Single-Channel 10GS/s 8b >36.4dB SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS

Qian Chen1, Yuan Liang*1, Chirn Chye Boon1, Qing Liu2

Kun Gao Xinxin Technologies, Singapore, Singapore *Equally Credited Authors (ECAs) 1 2 High data throughput and wideband network communications demand high-speed (several to tens of GS/s), moderate-resolution (6-10b) ADC

Nanyang Technological University, Singapore, Singapore

ISSCC 2023 Session 17 Data Converters

A 3mW 2.7GS/s 8b Subranging ADC with Multiple-ReferenceEmbedded Comparators

Jia-Ching Wang, Tai-Haur Kuo

A subranging ADC is a good choice for wideband applications since the numerous comparators for a flash ADC can be avoided [1-5]. However, despite the reduced number of comparators that a subranging ADC requires, these co

National Cheng Kung University, Tainan, Taiwan

ISSCC 2023 Session 17 Data Converters

A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration

Yi-Hu Wang, Soon-Jyh Chang

With the development of broadband wireless communication and DSP-based wireline communication, there is a rising demand for medium-resolution (6~8bit) ADCs with multi-gigahertz sampling rates and low power consumption. T

National Cheng Kung University, Tainan, Taiwan

ISSCC 2023 Session 17 Data Converters

A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor

Mingtao Zhan, Lu Jie, Nan Sun

Next-generation wireless standards (e.g., WiFi-7) advancing towards wider bandwidth and higher order modulation require ADCs with GHz sampling rates and over 12b resolution. Although conventional pipelined ADCs can satis

Tsinghua University, Beijing, China

ISSCC 2023 Session 17 Data Converters

A 750mW 24GS/s 12b Time-Interleaved ADC for Direct RF Sampling in Modern Wireless Systems

Sandeep Santhosh Kumar1, Masahiro Kudo1, Vlad Cretu1, Antoine Morineau1,

Atsushi Matsuda2, Minori Yoshida2, Masazumi Marutani2, Aadil Hussain Maniyar1, Jay Kumar1 Socionext Europe, Maidenhead, United Kingdom Socionext, Yokohama, Japan 1 2 An ADC with a sampling rate of tens of GS/s and a high

ISSCC 2023 Session 17 Data Converters

A 14b 16GS/s Time-Interleaving Direct-RF Synthesis DAC with T-DEM Achieving -70dBc IM3 up to 7.8GHz in 7nm

Wei-Hsin Tseng*1, Willy Lin*1, Chung-Wei Hsu1, Chang-Yang Huang1,

Yu-Sian Lin1, Hung-Yi Huang1, HsinWei Chen1, Sheng-Hui Liao1, Kuan-Dar Chen1, Jon Strange2, Gabriele Manganaro3 MediaTek, HsinChu, Taiwan, 2MediaTek, Kent, United Kingdom, 3MediaTek, Woburn, MA *Equally Credited Authors

ISSCC 2023 Session 17 Data Converters

An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches

Abdullah Serdar Yonar1,2, Pier Andrea Francese1, Matthias Brändli1,

2 Circuit innovations in medium-low resolution ADCs are among the key enablers to achieving higher data rates, currently at 224Gb/s [1], in the next-generation datacommunication links based on sophisticated DSP technique

Marcel Kossel1, Mridula Prathapan1, Thomas Morf1, Andrea Ruffino1, Tae

ISSCC 2023 Session 17 Data Converters

A 2×-Interleaved 9b 2.8GS/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input

Hongzhi Zhao1, Minglei Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2

Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 By increasing the number of bits in each conversion cycle, the sampling rate of SAR ADCs can be considerably extended while maintaining superior energ

University of Macau, Macao, China

ISSCC 2023 Session 16 AI / ML

A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications

Giuseppe Desoli*1, Nitin Chawla*2, Thomas Boesch*3, Manuj Ayodhyawasi*2,

Harsh Rawat2, Hitesh Chawla2, Abhijith VS2, Paolo Zambotti4, Akhilesh Sharma2, Carmine Cappetta1, Michele Rossi1, Antonio De Vita1, Francesca Girardi1 STMicroelectronics, Cornaredo, Italy STMicroelectronics, Noida, India

ISSCC 2023 Session 16 AI / ML

A Nonvolatile AI-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W

Wei-Hsing Huang*1, Tai-Hao Wen*1,2, Je-Min Hung*1, Win-San Khwa*2,

Yun-Chen Lo1, Chuan-Jia Jhang1,2, Hung-Hsi Hsu1, Yu-Hsiang Chin1, Yu-Chiao Chen1, Chung-Chuan Lo1, Ren-Shuo Liu1, Kea-Tiong Tang1, Chih-Cheng Hsieh1, Yu-Der Chih3, Tsung-Yung Chang3, Meng-Fan Chang1,2 National Tsing Hua

ISSCC 2023 Session 16 Digital Processors

DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching

Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha,

and area efficiency for deep neural network (DNN) processing [1-3]. As shown in Fig. 16.5.1, despite promising macro-level efficiency and throughput, there remain three main challenges to extending gains to system perfor

Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo Korea Advanced

ISSCC 2023 Session 16 Digital Processors

TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration

Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu,

Recommendation Models (DLRMs) have computational and data-movement requirements beyond those seen in typical NN processing. Such beyond-NN applications typically consist of Sparse Gathering (SpG) and Sparse Algebra (SpA)

Shaojun Wei, Shouyi Yin Tsinghua University, Beijing, China Applicatio

ISSCC 2023 Session 16 Digital Processors

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture

Jinshan Yue1, Chaojie He1, Zi Wang1, Zhaori Cong1, Yifan He2, Mufeng Zhou2,

University, Beijing, China 1 2 Computing-in-memory (CIM) has shown high energy efficiency on low-precision integer multiply-accumulate (MAC) [1-3]. However, implementing floating-point (FP) operations using CIM has not b

Wenyu Sun2, Xueqing Li2, Chunmeng Dou1, Feng Zhang1, Huazhong Yang2, Y

ISSCC 2023 Session 16 AI / ML

A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine

Shiwei Liu1, Peizhe Li1, Jinshan Zhang1, Yunzhengmao Wang1, Haozhe Zhu1,

Transformer networks, from BERT, GPT to Alphafold, have demonstrated unprecedented advances in a variety of AI tasks. Fig. 16.2.1 shows the computing flow of self-attention – the fundamental operation in transformers. Qu

Wenning Jiang1, Shan Tang2, Chixiao Chen1,3, Qi Liu1, Ming Liu1 Fudan

ISSCC 2023 Session 16 AI / ML

MulTCIM: A 28nm 2.24µJ/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers

Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu,

natural language, speech, etc. Multimodal Transformer (MulT, Fig. 16.1.1) models introduce a cross-modal attention mechanism to vanilla transformers to learn from different modalities, achieving excellent results on mult

Shaojun Wei, Shouyi Yin Tsinghua University, Beijing, China Human perc

ISSCC 2023 Session 15 Hardware Security

A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS

Raghavan Kumar1, Avinash Varna2, Carlos Tokunaga1, Sachin Taneja1,

from cryptographic engines to extract secret keys. A single fault injected into the penultimate AES round using directed laser pulses or voltage/clock glitches corrupts 4 output bytes (Fig. 15.5.1), reducing key search s

Vivek De1, Sanu Mathew1 Intel, Hillsboro, OR Intel, Chandler, AZ 1 2 F

ISSCC 2023 Session 15 Hardware Security

A 28nm 68MOPS 0.18µJ/Op Paillier Homomorphic Encryption Processor with Bit-Serial Sparse Ciphertext Computing

Guiming Shi1, Zhanhong Tan1, Dapeng Cao2, Jingwei Cai1, Wuke Zhang3,

of tremendous emerging information applications, providing various reliable and high-performance services based on vast amounts of individual and organizational data. Paillier homomorphic encryption (PHE)

Yifu Wu3, Kaisheng Ma1 Tsinghua University, Beijing, China Xi’an JiaoT

ISSCC 2023 Session 15 Hardware Security

A 33kDMIPS 6.4W Vehicle Communication Gateway Processor

Achieving 10Gbps/W Network Routing, 40ms CAN Bus, Start-Up and 1.4mW Standby Power

in the Control domain can start the CAN service in parallel with booting for other (nonCAN) services. Moreover, decryption by a secure CPU and data loading from external memory can be performed in parallel by double buff

ISSCC 2023 Session 15 Hardware Security

A 2.19µW Self-Powered SoC with Integrated Multimodal

Energy Harvesting, Dual-Channel up to -92dBm WRX and, Energy-Aware Subsystem

Everactive, Charlottesville, VA, 2Everactive, Santa Clara, CA, 3Everactive, Ann Arbor, MI preserved. The SoC is designed to operate near-threshold to achieve its low power floor. Thus, an AVFS block is included to improv

ISSCC 2023 Session 15 Hardware Security

A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber

Xinjian Liu1, Daniel S. Truesdell1, Omar Faruqe1, Lalitha Parameswaran2,

Michael Rickley2, Andrew Kopanski2, Lauren Cantley2, Austin Coon2, Matthew Bernasconi2, Tairan Wang2, Benton H. Calhoun1 University of Virginia, Charlottesville, VA MIT Lincoln Laboratory, Lexington, MA 1 2 Rapid reducti

ISSCC 2023 Session 14 Digital Circuits

A Digital Low-Dropout (LDO) Linear Regulator with Adaptive Transfer Function Featuring 125A/mm2 Power Density and Autonomous Bypass Mode

Michael Zelikson, Kosta Luria, Lior Gil, Yuval Brown, Vadim Goldenbeg,

grouped and share a common power supply per group. A combination of a common supply with per-domain DVFS implies a need for local voltage regulation, which in some SOCs is based on LDOs. Operation conditions feature dyna

Dor Kasif, Elias Hlees, Alex Vinichuk Intel, Haifa, Israel Modern CPUs

ISSCC 2023 Session 14 Digital Circuits

A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration

Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong,

generators to satisfy diverse specifications for different modules, such as microprocessors, memories, I/O interfaces, and power management. Conventionally, multiple PLLs are used in SoCs to provide various frequency out

Zhihua Wang, Baoyong Chi Tsinghua University, Beijing, China Modern sy

ISSCC 2023 Session 14 Digital Circuits

A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur

Qiaochu Zhang1, Hsiang-Chun Cheng1, Shiyu Su1,2, Mike Shuo-Wei Chen1

University of Waterloo, Waterloo, Canada 1 2 Ring-oscillator (RO)-based injection-locked phase-locked loops (IL-PLLs) and multiplying delay-locked loops (MDLLs) are promising candidates for low-cost, highperformance cloc

University of Southern California, Los Angeles, CA

ISSCC 2023 Session 13 Other

A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4x4 Optical Mesh

Md Jubayer Shawon, Vishal Saxena

As we envision post-Moore solid-state circuits, there is a growing impetus for leveraging emerging device technologies outside the traditional CMOS fold. Silicon photonics (SiP) fabrication in CMOS-compatible foundries h

University of Delaware, Newark, DE

ISSCC 2023 Session 13 Other

Subtractive Photonic Waveguide-Coupled Photodetectors in 180nm Bulk CMOS

Craig Ives, Ali Hajimiri

The integration of electronics and photonics into a single silicon CMOS process can serve wide-ranging applications, e.g. complex imaging and projection photonic systems, onchip optical interconnects, or self-correcting

California Institute of Technology, Pasadena, CA

ISSCC 2023 Session 13 Other

A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication

Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura

Ambient energy harvesting exploits existing energy for powering ICs and has been expanding operation space and application field of IC electronics. If an existing high energy source yet unexploited by ICs could be found,

Osaka University, Suita, Japan

ISSCC 2023 Session 13 Other

A Triturated Sensing System

Noriyuki Miura1, Kotaro Naruse1, Jun Shiomi1, Yoshihiro Midoh1,

evolution of our information society today, where compact high-performance computers exist everywhere to provide us easy and immediate access to powerful information technologies and services. To further advance our info

Tetsuya Hirose1, Takaaki Okidono2, Takuji Miki2, Makoto Nagata2 Osaka

ISSCC 2023 Session 13 Other

A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring

a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature, Extractor and an RNN Classifier

Jinhai Lin1, Ka-Fai Un1, Wei-Han Yu1, Pui-In Mak1, Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Real-time speech recognizers and translators re

ISSCC 2023 Session 13 AI / ML

Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating the maximum frequency. Energy for inference (MNIST) using only the CPU memory and the core is 1681.97µJ, whereas energy for inference using the ACC is 0.19µJ. The inference time is reduced from 3.55s to 485µs. Therefore, our ACC enables inference according to the frame rate of imaging data (e.g., 60fps and 16ms).

Yuto Yakubo1, Kazuma Furutani1, Kouhei Toyotaka1, Haruki Katagiri1,

Masashi Fujita1, Munehiro Kozuma1, Yoshinori Ando1, Yoshiyuki Kurokawa1, Toru Nakura2, Shunpei Yamazaki1 The effect of power reduction when performing context switching and PG is compared between an OS/Si chip and a Si (

ISSCC 2023 Session 12 RF & Wireless

A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver

Ahmed E. Abdelrahman1, Mostafa G. Ahmed1,2, Mahmoud A. Khalil1,

increasing intra-datacenter traffic is pushing the demand for ultra-high-speed optical interconnect that maximizes both power efficiency and data rate per wavelength. Intensity modulation-direct detection (IM-DD) links a

Mohamed Badr Younis1, Kyu-Sang Park1, Pavan Kumar Hanumolu1 University

ISSCC 2023 Session 12 RF & Wireless

A 7 pA/√Hz Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS

Kadaba Lakshmikumar*1, Alexander Kurylak*1, Romesh Kumar Nandwana*1,

amplifier (TIA) is a critical building block that impacts the noise, bandwidth, and power consumption of intensity modulation and direct detection (IMDD) optical links used in data centers. CMOS TIAs using the shunt-feed

Bibhu Das1, Joe Pampanin1, Mike Brubaker1, Pavan Kumar Hanumolu2 CISCO

ISSCC 2023 Session 12 RF & Wireless

A 0.96pJ/b 7×50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies

Mayank Raj1, Chuan Xie1, Ade Bekele1, Adam Chou1, Wenfeng Zhang1,

Ying Cao1, Jae Wook Kim1, Nakul Narang2, Hongyuan Zhao2, Yipeng Wang2, Kee Hian Tan2, Winson Lin1, Jay Im1, David Mahashin1, Santiago Asuncion1, Parag Upadhyaya1, Yohan Frans1 AMD, San Jose, CA AMD, Singapore, Singapore