ISSCC 2021
Session 13
Quantum & Photonics
A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS
Italy 4 EPFL, Neuchatel, Switzerland 1 2 Quantum computers (QCs) promise significant speedup for relevant computational problems that are intractable by classical computers. QCs process information stored in quantum bits
ISSCC 2021
Session 13
Quantum & Photonics
A 6-to-8GHz 0.17mW/Qubit Cryo-CMOS Receiver for Multiple Spin Qubit Readout in 40nm CMOS Technology
Patrick Harvey-Collard1,2, Jurgen Dijkema1,2, Amir Sammak4, Giordano Scappucci1,2, Edoardo Charbon1,2,5, Fabio Sebastiano1,2, Lieven M. K. Vandersypen1,2, Masoud Babaie1,2 Delft University of Technology, Delft, The Nethe
ISSCC 2021
Session 13
Quantum & Photonics
A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-onChip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots
Quantum Motion Technologies, Leeds, United Kingdom differential-to-single-ended buffer for 50Ω output match. The LO signal for downconversion is generated on chip by an analog charge-pump integer-N PLL with a programmabl
ISSCC 2021
Session 13
Quantum & Photonics
A Fully Integrated Cryo-CMOS SoC for Qubit Control in
FFL FinFET Technology Jong-Seok Park1, Sushil Subramanian1, Lester Lampert1, Todor Mladenov1, Ilya Klotchkov1, Dileep J. Kurian2, Esdras Juarez-Hernandez3, Brando Perez-Esparza3, Sirisha Rani Kale1, Asma Beevi K. T. 4, S
ISSCC 2021
Session 12
Power Management
Exploring PUF-Controlled PA Spectral Regrowth for Physical-Layer Identification of IoT Nodes
*Equally-Credited Authors (ECAs) It is projected that 75 billion Internet-of-Things (IoT) devices will be deployed for applications such as wearable electronics and smart home by 2025. Securing IoT devices is one of the
ISSCC 2021
Session 12
Power Management
Improving the Range of WiFi Backscatter Via a Passive Retro-Reflective Single-Side-Band-Modulating MIMO Array and Non-Absorbing Termination
Dinesh Bharadia1, Patrick P. Mercier1 University of California San Diego, La Jolla, CA Broadcom, San Diego, CA 1 2 Wi-Fi is the most ubiquitous wireless networking technology for IoT in homes, offices, and businesses. Si
ISSCC 2021
Session 12
AI / ML
A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network
University, Hangzhou, China 4 XINYI Information Technology, Shanghai, China 1 2 Power is a major bottleneck in AIoT devices, which usually operate in random-sparseevent (RSE) scenarios [1] (Fig. 12.1.1, bottom). To proce
ISSCC 2021
Session 11
Wireline I/O
A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler
Raytheon, Tewksbury, MA 3 Intel, Chandler, AZ 1 The rapid surge of data transmission within computation, storage and communication infrastructures is pushing the speed boundary of traditional copper-based electrical link
ISSCC 2021
Session 11
Wireline I/O
An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS
Govert Geelen2, Corné Bastiaansen2, Narendra Rao1, Viswa Popuri1, Greg Shen1, Hamid Khatibi1, Saudas Dey3, Anirban Chatterjee3, David Shen1, Peter Zijlstra2, Harrie Gunnink2, Kebin Zhang1, Venkat Penumuchu1, Oliver Weiss
ISSCC 2021
Session 11
Wireline I/O
A 56Gb/s 50mW NRZ Receiver in 28nm CMOS
The power consumption of wireline transceivers has become increasingly critical as higher data rates and a larger numbers of lanes per chip are sought [1-6]. While attractive for lossy channels, PAM-4 signaling has mostl
ISSCC 2021
Session 11
Wireline I/O
A 100Gb/s -8.3dBm-Sensitivity PAM-4 Optical Receiver with
g. 400G-DR4/FR4) have been developed to address the rapid increase in interconnect BW demand created by data-centric computing [1]. Low-cost 100Gb/s PAM-4 optical transceivers are critical to spur their adoption in high
ISSCC 2021
Session 11
Wireline I/O
A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET
100Gb/s+ is rapidly increasing to accommodate the massive data traffic of data centric systems such as Internet-of-things, autonomous driving, cloud computing, etc. In recent publications, a 14GHz LC-PLL was successfully
ISSCC 2021
Session 11
Wireline I/O
A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links
*Equally-Credited Authors (ECAs) The ever-increasing Internet data demand imposes stringent requirements on wireline transceiver speed, jitter, and power. A low-noise, multi-phase clock generator (MPCG) is a crucial buil
ISSCC 2021
Session 11
Wireline I/O
A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die Applications
Chris Moscone, Qazi Omar Farooq Cadence, Cary, NC With recent AI and big data developments, quickly moving massive amounts of data is paramount to future technologies. Scalable solutions that can sustain higher performan
ISSCC 2021
Session 11
Wireline I/O
A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS
George Ng1, Nanyan Wang2, Javid Musayev1, Gairik Dutta1, Masumi Shibata1, Arash Moradi1, Haleh Vahedi1, Manavi Farzad1, Prabhnoor Kainth1, Matt Yu1, Nhat Nguyen2, Jennifer Pham1, Angus McLaren1 Rambus, Toronto, Canada Ra
ISSCC 2021
Session 11
Wireline I/O
A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology
Mohammad Elbadry1, Ahmed ElShater1, Tsz-Bin Liu2, Joonyeong Lee1, Dhinessh Ramachandran1, Kaiz Wang2, Chih-Hao Weng2, Mau-Lin Wu2, Tamer Ali1 MediaTek, Irvine, CA MediaTek, Hsinchu, Taiwan 1 2 *Equally-Credited Authors (
ISSCC 2021
Session 10
Data Converters
A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters
Yu-shan Wang4, Christian Lindholm2, Hundo Shin5, Ramon Sanchez3, Christoph Duller2, Patrick Torta2, Kamran Azadet1 Intel, Santa Clara, CA Intel, Villach, Austria 3 Intel, Madrid, Spain 4 Intel, Hillsboro, OR 5 now with A
ISSCC 2021
Session 10
Data Converters
A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET
*Equally-Credited Authors (ECAs) Future multi-band software-defined-radio base-stations for digital beamforming and massive MIMO applications depend heavily on the availability of highly linear and compact data converter
ISSCC 2021
Session 10
Data Converters
A 12b 600MS/s Pipelined SAR and 2×-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET chip-to chip gain variation of the residue signal path. Moreover, the area-consuming 7b CDAC can be used in calibrating inter-stage offset error by adding offset in the feedback signal. Therefore, the comparator without offset calibration enables the SAR to enhance conversion speed.
Youngjae Cho, Jongshin Shin Figure 10.5.3 shows the proposed adaptive speed-controlled (ASC) clock generation scheme. The ASC clock generator takes advantages from both the synchronous and asynchronous schemes by generat
ISSCC 2021
Session 10
Data Converters
A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR
design suffers from a few challenges. First, it requires a large number of OTAs [1]. This increases the design complexity and power. In addition, each OTA contributes extra phase delay, whose reduction requires increasin
ISSCC 2021
Session 10
Data Converters
A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer
Emerging communication and radar applications place enormous demands on ADC performance by requiring wide BW (100MHz) and high DR (70dB). Continuous-time delta-sigma modulators (CT-DSM) [1-2] are a mainstream solution as
ISSCC 2021
Session 10
Data Converters
A 139µW 104.8dB-DR 24kHz-BW CTΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs comparator non-idealities (e.g., signal-dependent delay) degrade the SQNR mostly in the main feedback path and not the auxiliary path. No extra fast path DAC or summing network is needed.
The first integrator, shown in Fig. 10.2.3, is realized by a 4-stage amplifier with feedforward compensation. Two versions of the OTA, a 1- and 3-stack, were designed for comparison. For the tailless 3-stack version, the
ISSCC 2021
Session 10
Data Converters
A 116µW 104.4dB-DR 100.6dB-SNDR CT ΔΣ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter
applications because of its high energy efficiency and driving-friendly front-end compared with its discrete time counterpart. A resistive DAC (R-DAC) is widely used for its intrinsic low flicker noise. However, the desi
ISSCC 2020
Session 9
Data Converters
A Low-Cost 4-Channel Reconfigurable Audio Interface for Car Entertainment Systems
multistandard radio, parallel-channel radio reception [1], noise cancellation, HD audio and more audio interfacing possibilities. This asks for more signal processing, and therefore, a move to more expensive deep-submicr
ISSCC 2020
Session 9
Data Converters
Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS
indispensable component for autonomous driving. A continuous-time (CT) ∆Σ ADC is expected to be suitable for this application due to its high precision and wide bandwidth as well as inherent anti-aliasing effect. However
ISSCC 2020
Session 9
Data Converters
A 2.56mW 40MHz-Bandwidth 75dB-SNDR PartialInterleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 The noise-shaping SAR (NS-SAR) hybrid architecture has shown its potential in achieving tens of MHz bandwidth (BW) together with high resolution [1-2]
ISSCC 2020
Session 9
Data Converters
A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
Linxiao Shen1, Abhishek Mukherjee1, Wei Shi1, David Z. Pan1, Nan Sun1 University of Texas, Austin, TX, 2Tsinghua University, Beijing, China 1 Noise shaping (NS) SAR ADCs combine the merits of SAR and ∆Σ ADCs, and can sim
ISSCC 2020
Session 9
Data Converters
A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth
High-resolution, sub-MHz-bandwidth data converters are essential for audio and sensor applications and are conventionally implemented as sigma-delta (SD) converters. The dependence of SD ADCs on op-amps inherently result
ISSCC 2020
Session 9
Data Converters
A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping
have drawn increasing attention due to their simplicity, low power, zero static current, and PVT robustness. However, prior works show limited resolution (ENOB(13b) due to two main challenges. The 1st one is thermal nois
ISSCC 2020
Session 9
Data Converters
A 134µW 24kHz-BW 103.5dB-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC
Audio applications require a high-resolution ADC with a dynamic range (DR) of more than 100dB. A continuous-time delta-sigma modulator (CTDSM) is widely used to realize such ADCs and requires high energy efficiency for b
ISSCC 2020
Session 9
Data Converters
A Current-Sensing Front-End Realized by A ContinuousTime Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s
are widely used in various applications, such as photoplethysmography (PPG) recording by biomedical sensors and molecular-concentration detection by electrochemical sensors. They usually require a low noise level down to
ISSCC 2020
Session 8
Industry Highlights
Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs
technology, the design of the Radeon RX 5700 series GPUs incorporate a 256b memory interface of GDDR6 memory operating at 14Gb/s for a total of 448GB/s bandwidth, a x16 PCIe® Gen4 link interface, and six 1.4 Display Port
ISSCC 2020
Session 8
Industry Highlights
A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications
Ketan Sawant3, Anitha Kona1, Rob Harrison3 ARM, Austin, TX ARM, Cambridge, United Kingdom 3 ARM, Sheffield, United Kingdom 4 ARM, Bangalore, India 1 2 The Neoverse family of Arm processors target a combination of high pe
ISSCC 2020
Session 8
Industry Highlights
A Versatile 7nm Adaptive Compute Acceleration Platform Processor
Fu-Hing Ho, Thomas To, Vamsi Nalluri, Mrinal Sarmah, Rajeev Patwari Xilinx, San Jose, CA As benefits from Moore’s Law diminish [1], general-purpose compute platforms like CPUs and GPUs continue to become increasingly pow
ISSCC 2020
Session 8
Industry Highlights
Lakefield and Mobility Compute: A 3D Stacked 10nm and
Wilfred Gomes1, Sanjeev Khushu2, Doug B. Ingerly1, Patrick N. Stover3, Nasirul I. Chowdhury1, Frank O'Mahony1, Ajay Balankutty1, Noam Dolev3, Martin G. Dixon1, Lei Jiang1, Surya Prekke4, Biswajit Patra4, Pavel V. Rott1,
ISSCC 2020
Session 7
AI / ML
GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation
image style transfer to synthetic voice generation [1]. GAN applications on mobile devices, such as face-to-Emoji conversion and super-resolution imaging, enable more engaging user interaction. As shown in Fig. 7.4.1, a
ISSCC 2020
Session 7
AI / ML
STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-SpinUpdates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
Masanao Yamaoka3, Hiroshi Teramoto2, Akira Sakai2, Shinya Takamaeda-Yamazaki4, Masato Motomura1 Tokyo Institute of Technology, Yokohama, Japan Hokkaido University, Sapporo, Japan, 3Hitachi, Sapporo, Japan 4 University of
ISSCC 2020
Session 7
AI / ML
A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS
Yun Li1, Long Chen1, Zhen Chen1, Lu Liu3, Zhuyu He3, Yu Yan3, Jun He3, Jun Mao3, Xiaotao Zai3, Xuejun Wu3, Yongquan Zhou3, Mingqiu Gu1, Guocai Zhu1, Rong Zhong1, Wenyuan Lee1, Ping Chen1, Yiping Chen1, Weiliang Li3, Deyu
ISSCC 2020
Session 7
AI / ML
A 3.4-to-13.3TOPS/W 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC
Yu-Ting Kuo, Perry H Wang, Pei-Kuei Tsung, Jeng-Yun Hsu, Wei-Chih Lai, Chia-Hung Liu, Shao-Yu Wang, Chin-Hua Kuo, Chih-Yu Chang, Ming-Hsien Lee, Tsung-Yao Lin, Chih-Cheng Chen MediaTek, Hsinchu, Taiwan Recent advancement
ISSCC 2020
Session 6
Wireline I/O
A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS
satisfy the continuously growing demands for wireline communications [1-5]. Although PAM-4 signaling performs two-fold bandwidth efficiency compared with the NRZ counterpart, the NRZ signal still has the advantage in low
ISSCC 2020
Session 6
Wireline I/O
An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels
a silicon interposer technology to increase the number of I/O pins. Interfaces with the silicon interposer provide a higher throughput (Gb/s/µm) than other packaging technologies due to the high channel density. To incre
ISSCC 2020
Session 6
Wireline I/O
Reference-Noise Compensation Scheme for SingleEnded Package-to-Package Links
Brian Zimmer1, Thomas H. Greer2, John W. Poulton2, Sanquan Song1, Walker J. Turner2, John M. Wilson2, C. Thomas Gray2 NVIDIA, Santa Clara, CA NVIDIA, Durham, NC 1 2 A recent trend in high-performance systems is distribut
ISSCC 2020
Session 6
Wireline I/O
A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS
Continuous-rate referenceless clock and data recovery (CDR) circuits are capable of operating over a wide range of data rates in multiple standards. To achieve wide-range operation without an external reference clock, se
ISSCC 2020
Session 6
Wireline I/O
A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier
Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin Samsung El
ISSCC 2020
Session 6
Wireline I/O
A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET
Socrates Vamvakos1, Haidang Lin1, Simon Li1, Marcus van Ierssel3, Prashant Choudhary1, Nanyan Wang1, Masumi Shibata3, Mohammad Hossein Taghavi3, Nhat Nguyen1,4, Shaishav Desai1 Rambus, Sunnyvale, CA, 2University of Alber
ISSCC 2020
Session 6
Wireline I/O
A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology
Yu-Ming Ying1, Mohammed Abdullatif1, Miguel Gandara1, Chun-Cheng Liu2, Po-Shuan Weng2, Huan-Sheng Chen2, Mohammad Elbadry1, Qaiser Nehal1, Kun-Hung Tsai2, Kevin Tan2, Yi-Chieh Huang2, Chung-Hsien Tsai2, Yuyun Chang2, Yua
ISSCC 2020
Session 6
Wireline I/O
A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET
Stanley Chen1, Yipeng Wang2, Hao-Wei Hung2, KeeHian Tan2, Winson Lin1, Arianne Roldan1, Declan Carey3, Ilias Chlis3, Ronan Casey3, Ade Bekele1, Ying Cao1, David Mahashin1, Hong Ahn1, Hongtao Zhang1, Yohan Frans1, Ken Cha
ISSCC 2020
Session 5
Image Sensors
A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel
Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh National Tsing Hua University, Hsinchu, Taiwan, *Equally-Credited Authors (ECAs) Ener
ISSCC 2020
Session 5
Image Sensors
A 0.50e-rms Noise 1.45µm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps
dark and bright conditions. In recent years, these features have been required for small pixel CMOS image sensors (CISs) to realize high S/N and resolutions while maintaining a high frame rate. An effective way to improv
ISSCC 2020
Session 5
Image Sensors
A 132dB Single-Exposure-Dynamic-Range CMOS Image Sensor with High Temperature Tolerance
Tomohiko Asatsuma1, Yuki Hattori1, Takayuki Yamanaka2, Ryoichi Yoshikawa2, Naoki Kawazu1, Tomohiro Matsuura1, Takahiro Iinuma1, Takahiro Toya1, Tomohiko Watanabe2, Atsushi Suzuki1, Yuichi Motohashi1, Junichiro Azami1, Ya