全部论文

Papers 2008–2026

共 3875 篇 ISSCC 论文，按年份倒序排列

年份 Year
2026 2472025 2422024 2222023 2002022 1672021 1952020 2022019 1812018 2052017 2082016 2002015 1912014 2032013 2102012 1882011 1962010 2102009 1802008 228
领域 Topic
RF & Wireless 362Power Management 302Wireline I/O 300Wireless 293Data Converters 279Digital Processors 268Memory 266AI / ML 231Digital Circuits 220Medical & Bio 211Image Sensors 184Analog Circuits 169mm-Wave 138Clocking & PLLs 127Sensors 100Plenary 63Hardware Security 36Quantum & Photonics 29Industry Highlights 7
顶级机构
University of California 101Delft University of Technology 73University of Macau 58KAIST 51Massachusetts Institute of Tec 48Tsinghua University 39National Taiwan University 38University of Michigan 37Georgia Institute of Technolog 35Columbia University 28Hong Kong University of Scienc 24MediaTek 23
ISSCC 2026 Session 27 Clocking & PLLs
A Dual-Mode DCO-PA with a Twisted 8-Shape Inductor for BLE Achieving 42% TX Efficiency at 1.6dBm and 0.29mW RX Clock
Jiawen Chen1,2, Kai Xu2, Luyi Guo1, Teerachot Siriburanon1, Jun Yin3, Bashir M. Al-Hashimi2, Robert Bogdan Staszewski1
Abstract This paper presents a 0.3V dual-mode (2.4/4.8GHz) DCO-PA for BLE, achieving 42% efficiency in the TX mode and 0.29mW power consumption in the RX clock mode. It features: 1) a twisted 8-shape inductor enabling oc
University College Dublin, Dublin, Ireland, 2King’s College London, Lo
ISSCC 2026 Session 27 Clocking & PLLs
A 77GHz 8-bit CMOS Phase Shifter Adopting a Nested-Vector-Based Error Correction with 0.33°/0.07dB RMS-Error for MIMO Radar Applications
Geonho Park, Byeong-Taek Moon, Kyunghwan Kim, Doyoon Kim, Goeun Baek, Byungho Yook, Hyun-Chul Park, Chan-Hong Park
Abstract In this paper, we present a 77GHz 8-bit nested vector-sum phase shifter in 28nm CMOS. The architecture performs vector modulation by splitting a single outer vector into two inner vectors generated by a two-stag
Samsung Electronics, Hwaseong, Korea
ISSCC 2026 Session 27 Clocking & PLLs
A 40.5-to-58.5GHz 36%-Fractional-Chirp-Bandwidth 18GHz-Absolute-Chirp-Bandwidth 2.2GHz/μs-Chirp-Rate 0.02%-Chirp-Error Post-Mixing Bandwidth-Extending Sawtooth-FMCW Frequency Synthesizer Employing a Chirp-Tracking ILFT and a Fractional-Bandwidth Doubler
Yi Liu*, Zixi Jing*, Wen Yang, Hanlin Yang, Bodong Zhang, Howard Cam Luong
*Equally Credited Authors (ECAs) Abstract An 18GHz-bandwidth (BW) sawtooth-FMCW synthesizer is presented. First, a chirp-tracking ILFT with feed-forward and frequency-tracking loop ensures robust and continuous tracking
HKUST, Hong Kong, China
ISSCC 2026 Session 27 Clocking & PLLs
A 9.7GHz Self-Linearized-VCO-Based FMCW Chirp Generator Achieving 1.56GHz/μs Slope and 0.57μs Duration with 0.094% rms Frequency Error
Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Michele Rossoni, Wenqian Wang, Ashbir Aviat Fadila, Duo Li, Minzhe
7GHz self-linearized-VCO-based Type-III FMCW synthesizer is presented. A CCal bank calibrates the nonlinearity of the CMod bank, and two LMS-based calibrations (gain and offset) reduce digital overhead and ensure stable
Carrel de Gomez, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi
ISSCC 2026 Session 27 AI / ML
A 17.9-to-22.4GHz 195.6±1.3dBc/Hz FoM Quad-Core Class-F-1 VCO Featuring Improved Synchronization Using a Circular Pentafilar Transformer-Based Tank
Yue Wu1, Yatao Peng1,2, Jiawei Li1, Fengen Yuan1, Jinge Li1, Jun Yin1, Rui P. Martins1, Pui-In Mak1
Abstract A 17.9-to-22.4GHz quad-core inverse-Class-F VCO achieving PN of −145.6 to −141dBc/Hz and an FoM of 194.3 to 196.9dBc/Hz is reported. The VCO features a circular pentafilar transformer tank that provides high Q1/
University of Macau, Macau, China, 2UM Hetao IC Research Institute, Sh
ISSCC 2026 Session 27 Clocking & PLLs
A 0.068mm2 8.5-to-12.7GHz Complementary Dual-Core VCO with Auto-2nd-Harmonic-Tracking Technique Achieving 202.7dBc/Hz Peak FoMT and 0.9dB-FoM Variation at a 1MHz Offset in a 39.6% Tuning Range
Xincheng Du1,2, Xiangxun Zhan1, Tincheng Ou1, Zaize Chen1, Jinge Li1, Haoran Li1, Zhizhan Yang3, Zhuo Xu1, Pui-In Mak1,
Abstract A complementary dual-core VCO with auto f2nd tracking is proposed to achieve consistently low PN and a high FoM over a wide tuning range (TR). Prototyped in 65nm CMOS, the proposed VCO achieves a peak FoM@1/10MH
University of Macau, Macau, China, 2UM Hetao IC Research Institute, Sh
ISSCC 2026 Session 27 Clocking & PLLs
A 14GHz Ring-Based 3rd-Order Fractional-N PLL with 164fsrms Jitter and a 100MHz Reference
Zhaochen Zhu, Qingxuan Lin, Zhiqiang Huang
Abstract This work presents a 14GHz ring-based 3rd-order fractional-N PLL with 164fsrms jitter and a 100MHz reference. A sub-sampling DLL is cascaded in the type-II PLL output for extra phase-noise and supply-noise suppr
Hong Kong University of Science and Technology, Guangzhou, China
ISSCC 2026 Session 27 Clocking & PLLs
÷ Nint AUX RO Non-overlapping Clock Generator + - + CBaux[2:0] + - + + - Vref Vb Vo V+ + Gm FFNC On: 157 fs Fractional-N Mode 60MHz × 52 ÷ 30 × 31 × 2 (c) Vctrlmain 60MHz × 52 ÷ (30+2-13) × (31+2-13) × 2 6.7GHz (d) fout 6.2~6.8GHz - α[k] MMD-based Q-Noise Cancellation FFNC On: 145 fs Integer-N Mode Feedforward RO Noise Cancellation UGB V- ÷ Nmain FFNC Off: 357 fs + - ÷ Naux α 6.4GHz FFNC Off: 358 fs L1: 382 pH L2: 421 pH Vctrlaux AUX Integer-N SPLL (fBW1 = 10MHz) faux 3.1~3.4GHz (b) Frac. Spur ×7 Main LCO Gm MASH 1-1-1 6.4GHz Vctrlaux + - + AUX/Main SPDs with identical design (a) OUT+ IN- CBaux[2:0] fref 60MHz OUT- IN+ Frac. Spur 6.7GHz QEC Off FFNC Off: 442 fs Vref fmain 100~160MHz Vin1 fdiv2 3.1~3.4GHz CBmain[4:0] Vout Vin2 Main Fractional-N SPLL (fBW2 = 1MHz) ÷2 Figure 27.2.3: Circuit implementation of the proposed PLL. (a) Fractional-N Mode 60MHz × 53 ÷ (20+2-11) × (21+2-11) × 2 fBW2 fBW1 Main PLL PN FFNC On Naux x 1 Naux x 1.5 Naux x 2 fref/2 (d) α=2-10 α=2-9 -84.7dBc (-72.7dBc) 203kHz 102kHz -84.8dBc (-72.8dBc) 60MHz × 53 ÷ 20 × (21+2-11) × 2 This Work H. Zhang ISSCC'25 D. Yang ISSCC'22 SPD/SPD D. Xu JSSC'25 Pulse Gen. +BBPD G. Jin JSSC'24 M. Mercandelli JSSC'22 W. Wu JSSC'21 SPD SPD SPD Phase Detector Noise Cancell./ Filter. Technique Calibration required? SPD/PFDCP SPD/XORPD MMD-QEC +FFNC MMD-QEC Harmonicmixing DTC-QEC DTC-QEC DTC-QEC DTC-QEC No No No Yes Yes Yes Yes VCO Type Ring+LC LC+LC LC+LC Ring+LC LC LC LC 60 82 74 50 100 500 76.8x2 6.2 to 6.8 4.7 to 5.7 25 to 28 6.5 to 8 3.3 to 4.5 11.9 to 14.1 5 to 7 157 (1k to 100M) 95.9 (1k to 100M) 88 (10k to 40M) 191 (10k to 10M) 203 (10k-100M) 58.2 (1k-100M) 80~95 (10k-100M) %72.7 %70.6 %70 %52.7 %57 %63.2 <%72 Reference Frequency [MHz] Output Frequency [GHz] (c) Fractional-N Mode Figure 27.2.4: Measured PN near 6.4GHz in (a) integer-N mode and (b) fractional-N mode with QEC on, FFNC on or off; measured PN near 6.7GHz in (c) fractional-N mode with QEC on, FFNC on or off and (d) fractional-N mode with FFNC on, QEC on or off. (b) RO, AUX PLL PN Normalized to Main PLL Freq. Main PLL PN FFNC Off FFNC On: 160 fs ×31 Non-overlapping Clock Generator Integrated Jitter [fs] In-band Fractional Spur [dBc] Power [mW] 17.2 21.2 12.9 14.2 2.4 18 14.2 FoM* [dB] %243.7 %247.1 %250 %242.9 %250.0 %252.1 %250.4 ~ %249.0 FoMREF** [dB] %235.9 %238.0 %241.3 %235.9 %240.0 %235.1 %241.5 ~ %240.1 CMOS Process [nm] Active 2 Area [mm ] 65 65 7 65 40 28 14 0.16 0.25 0.24 0.48 0.36 0.16 0.31 Figure 27.2.5: (a) FFNC robustness verification based on measurement results; (b) *FoM = 10log((Power/1mW)*(Jitter/1s)2) **FoMref = 10log((Power/1mW)*(Jitter/1s)2)+10log(fref/10MHz) measured fractional spur levels at near-integer channels; (c)(d) measured output Figure 27.2.6: Performance comparison of the proposed PLL with prior-art designs. spectra with fractional spurs. Power (mW) AUX 0.9 5% Loop RO 5.8 34% Main 1.7 10% Loop DSM 0.4 2% LCO 8.4 49% Total 17.2 100% 850μm 480μm LCO Main LF FFAMP AUX SPD/Div. AUX GM /LF AUX/Main MMDs DSM Main SPD/GM RO Area (mm2) AUX 0.010 6% Loop RO 0.006 4% Main 0.023 14% Loop DSM 0.003 2% LCO 0.119 74% Total 0.162 100% Figure 27.2.7: Die micrograph (left); measured power consumption and area (right). • 2026 IEEE International Solid-State Circuits Conference 979-8-3315-8936-3/26/$31.00 ©2026 IEEE
ISSCC 2026 Session 27 Clocking & PLLs
A 48-to-82.5GHz CMOS Split-Tail Gilbert-Cell Frequency Doubler Achieving 11% PAE at 8.5dBm Output Power
Jismal Jamal1, Lorenzo Piotto2, Federico Vecchi3, Mahmoud M. Pirbazari3, Andrea Mazzanti1
Abstract A 48-to-82.5GHz frequency doubler in 28nm FDSOI CMOS using a modified Gilbert cell is presented. The tail transconductors are split and the switching-quad transistors AC-shorted by capacitors. DC offset builds u
University of Pavia, Pavia, Italy, 2Fondazione Chips-IT, Pavia, Italy,
ISSCC 2026 Session 27 Clocking & PLLs
A 20GHz Frequency Synthesizer with Spur-Shaping Modulator Achieving 46.2fs Jitter and -76.5dBc Worst-Case Fractional Spur
Zonglin Ye, Yuxuan Sun, Longxiang Hou, Yuhan Ding, Yixuan Wen, Hongyang Zhang, Xinlin Geng, Qian Xie, Shiheng Yang, Zhen
Abstract In this paper, a frequency synthesizer is proposed with low fractional spur and low jitter, featuring a spur-shaping-modulator (SSM) technique that suppresses the nonlinearity arising from inter-slice mismatch.
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2026 Session 26 Power Management
A Compact Dual-Capacitor Relay SPT Supply Modulator with Overshoot-Free Adaptive On-Time Control for 5G FR2 CMOS PA
Zhewen Yu1,2, Zhiguo Tong2, Junwei Huang2, Jun Yin2, Yan Lu1
Abstract 5G new-radio frequency-range-2 CMOS PAs with high peak-to-average-power ratios suffer from low efficiency, calling for compact and fast symbol-power-tracking (SPT) supply modulators (SMs). Inductor-based SPT sho
Tsinghua University, Beijing, China, 2University of Macau, Macau, Chin
ISSCC 2026 Session 26 Power Management
A 1.2μs 1-to-12V Symbol Power Tracking Supply Modulator with Two-Step Subranging DVS Scheme and Boosted IL Slew Rate for 5G Mobile Devices
Changjin Chen, Minghao Shang, Yichao Ji, Lin Cheng
Abstract This paper presents a symbol power tracking supply modulator that delivers a high output voltage and a wide output range for 5G high-voltage GaN PAs. To accelerate voltage transitions, a two-step subranging DVS
University of Science and Technology of China, Hefei, China
ISSCC 2026 Session 26 Power Management
A 100A 93.4%-Peak-Efficiency LLC Resonant Converter with an Embedded Primary-Current-Extracted Regulator
Zeguo Liu1, Yichao Ji1, Zhiren Luo1, Yu Ge1, Weiwei Xu2, Weiwei Huang2, Lin Cheng1,2
Abstract This paper presents a 100A 93.4%-peak-efficiency LLC resonant converter with an embedded primary-current-extracted regulator. The proposed regulator powers the gate drivers of the LLC converter, eliminating the
University of Science and Technology of China, Hefei, China, 2Hefei CL
ISSCC 2026 Session 26 Power Management
A 92.4%-Peak-Efficiency 48V to 0.8-to-1.6V Hybrid Converter with Inductor-Interleaved Fibonacci Switched-Capacitor
Hyun-Woo Jeong, Chan-Ho Lee, Hyeon-Ji Choi, Sung-Wan Hong
Abstract This paper presents a 92.4%-peak-efficiency 48V to 0.8-to-1.6V hybrid converter based on an inductor-interleaved Fibonacci switched-capacitor (I2-FSC). The proposed converter reduces ΔVL with few flying capacito
Sogang University, Seoul, Korea
ISSCC 2026 Session 26 Power Management
An Inductor-at-Middle Hybrid Buck Converter with Shared Power-Signal Path for Distributed Vertical Power Delivery
Zhongyao Zhu1,2, Junwei Huang2, Zhibang Song1,2, Zhewen Yu1,2, Shousheng Han2, Sai-Weng Sin2, Yan Lu1
Abstract This work presents an inductor-at-middle hybrid buck converter for high-current density vertical power delivery, reusing the power inductors as signal feedback paths. The proposed switching-bus-multiplexing cont
Tsinghua University, Beijing, China, 2University of Macau, Macau, Chin
ISSCC 2026 Session 26 Power Management
A 12-to-1V 90.5%-Peak-Efficiency 721A/cm3-Current-Density Quad-Output Converter with One Shared DC Capacitor
Qingqing Min1, Jinyi Yuan1, Ji Jin1, Yichao Ji1, Weiwei Xu2, Lin Cheng1,2
Abstract This paper presents a 12-to-1V 4-output hybrid DC-DC converter that shares a single DC capacitor among all outputs. This shared capacitor stores and redistributes energy, ensuring independent regulation at each
University of Science and Technology of China, Hefei, China, 2Hefei CL
ISSCC 2026 Session 26 Power Management
A Multi-Phase Hybrid Converter with Q Samplers Enabling Simultaneous IL Auto-Balance and Arbitrary Phase Count
Jiacheng Yang*, Zihao Tang*, Rui P. Martins, Mo Huang
*Equally Credited Authors (ECAs) Abstract The paper presents a multiple-phase hybrid converter with Q samplers. Split-TON control enables VCF auto-balance and arbitrary phase counts under all-phase interleaving, while 0V
University of Macau, Macau, China
ISSCC 2026 Session 26 Power Management
A Compact 4Vin 93.4%-Peak-Efficiency 12A Load and 20mV Undershoot Resonant Sigma Converter with PCB-Embedded Converter-onSubstrate Packaging
Yukan Du, Shengdao Ren, Zheyuan Fei, Ziteng Chen, Menglian Zhao, Chushan Li, Yong Ding, Wuhua Li, Zhichao Tan, Wanyuan Q
Abstract This work presents a 4V input 12A load resonant sigma converter which consists of a 10MHz high-side switched-capacitor Buck (SCB) and a 5MHz low-side direct resonant switchedcapacitor (ReSC) converter. The propo
Zhejiang University, Hangzhou, China
ISSCC 2026 Session 25 Hardware Security
A PVT Variation- and Attack-Tolerant Metastability-Based TRNG Using Binary Search in 2nm
Yelim Youn1, Yong Lim1,2, Jongmi Lee1, Dongyeon Hong1, Wan Kim1, Yong-Sik Kwak1, Kyoung-Jun Moon1, Bogyeong Kang1, Sangm
Abstract This work presents a single source, metastability-based TRNG using binary search with offset-tunable comparator. The proposed TRNG operates without warm-up time and is robust against low-frequency noise, PVT var
Samsung Electronics, Hwaseong, Korea, 2now with Yonsei University, Seo
ISSCC 2026 Session 25 Hardware Security
A Sub-Threshold All-NMOS Reconfigurable PUF with Secure Configuration Selection for Stable 6b/Cell
Shufan Xu*, Kunyang Liu*, Lando Chan, Hironori Tagawa, Hirofumi Shinohara, Kiichi Niitsu
*Equally Credited Authors (ECAs) Abstract In this work, a reconfigurable PUF featuring secure configuration selection is presented. Without exposing secret PUF data, it achieves 6 stable bits per cell (b/cell) and “zero”
Kyoto University, Kyoto, Japan
ISSCC 2026 Session 25 Hardware Security
TinyPAD: A 166µm2/lane Variation-Tolerant Probing-Attack Detector for an 8Gb/s/lane Chip-to-Chip Interface in 16nm FinFET
Mao Li1, Rentao Wan1, Sanu K Mathew2, Vivek De2, Mingoo Seok1
Abstract We present TinyPAD, a 166µm2/lane probing-attack detector in 16nm FinFET with 82pF maximum supported loading as well as 0.2pF minimum detectable capacitance (MDC) that operates robustly over -40 to125°C and from
Columbia University, New York, NY, 2Intel, Hillsboro, OR
ISSCC 2026 Session 25 Hardware Security
A 17%/27% Area-/Energy-Overhead Glitch-Transition Secure SHA-3 Engine Fusing Dual-Rail Precharge Logic and Asymmetric Masking
Cankun Zhao1,2, Hanyue Shui1,2, Bohan Yang1,2, Wenping Zhu1,2, Yuluan Cao1,2, Zhang Hou1,2, Yuqi Liu1,2, Xiangdong Han1,
Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, China Wuxi Research Institute of Applied Technologies, Tsinghua University, Beijing, China, 4Micro Innovation Integrated Circuit Desi
Hanning Wang1,2, Jinjiang Yang3, Min Zhu4, Aoyang Zhang1,2, Leibo Liu1
ISSCC 2026 Session 25 Hardware Security
A 0.05mm2 1.19-to-7.34mW SQIsign-1D Isogeny-Based Post-Quantum Signature Verification Accelerator for IoT
Krishna Sai Tarun Ramapragada, Utsav Banerjee
Abstract This work presents a 0.05mm2 and 1.19-to-7.34mW hardware accelerator for the isogenybased NIST post-quantum digital signature candidate SQIsign. Our Montgomery multiplier design enables 2× speedup and energy sav
Indian Institute of Science, Bengaluru, India
ISSCC 2026 Session 25 Hardware Security
OmniCrypt: A 435.86M-GOPS/W Bootstrappable Multi-Scheme FHE Accelerator with On-Chip Data Generation for Privacy-Preserving Computation
Adiwena Putra*, Hyunjun Cho*, Sungwoong Yune, Cuong Manh Duong, Jaeho Jeon, Joo-Young Kim
*Equally Credited Authors (ECAs) Abstract OmniCrypt is a silicon-proven multi-scheme FHE accelerator that supports both bootstrapping and scheme switching. Fabricated in 28nm CMOS (12.96mm2), it integrates three speciali
KAIST, Daejeon, Korea
ISSCC 2026 Session 25 Hardware Security
A 16nm 0.042mm2 0.66µJ/Ops Lightweight MLWE PQC KEM with Cryptanalysis-ASIC Co-Optimization
Archisman Ghosh*1, Ming-Che Li*1, Lingke Ding1, Suparna Kundu2, Abdullah Sayeed1, Angshuman Karmakar3, Harshit Naman1, S
(ECAs) 1 Abstract Resource-limited devices demand post-quantum cryptography (PQC) within stringent power, area, and memory limits. To our knowledge this work introduces the first cryptanalysis-ASIC co-optimized PQC IC, a
Ingrid Verbauwhede2, Shreyas Sen1 Purdue University, West Lafayette, I
ISSCC 2026 Session 25 Hardware Security
A 28nm 0.48mJ/boot Torus FHE Processor for Arbitrary Computation on Encrypted Data
Xinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang, Song Wang, Zhen Yang, Jun Han
Abstract This work presents a 3.24mm2 torus fully homomorphic encryption (FHE) processor fabricated in 28nm CMOS, featuring: 1) a security-preserving low-bit-width torus quantization with keys hints reducing latency by 6
Fudan University, Shanghai, China
ISSCC 2026 Session 25 Hardware Security
A 65nm 0.066pJ/b Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks
Kai Cheng1, Yunbo Huang1, Zunsong Yang1, Li Wang1, Hongyu Ren1, Xiaoyu Shan1, Pui-In Mak2, Yong Chen3, Bo Li1
Abstract In Paper 25.10 a floating-latch-based true random number generator (FL-TRNG) is presented that achieves an energy efficiency of 0.066pJ/b by leveraging a floating reservoir capacitor as its power supply. This ar
Institute of Microelectronics of the Chinese Academy of Sciences, Beij
ISSCC 2026 Session 25 Hardware Security
HERACLES: 8192-Way SIMD Programmable Scalable Fully-Homomorphic Encryption SoC for Privacy-Preserving Cloud Computing in Intel 3 CMOS
Anupam Golder1, Raghavan Kumar1, Sachin Taneja1, Kylan Race2, Paolo Aseron1, James Greensky1, Wen Wang1, Huijing Gong1,
Vikram Suresh1, Adish Vartak1, AppaRao Challagundla2, Jeremy Casas1, Poornima Lalwaney1, Duhyeong Kim1, Christopher N. Gutierrez1, Ernesto Zamora Ramos1, Wonhee Cho1, Jose M. Rojas Chaves1, Michael Steiner1, Dan Lake1, N
ISSCC 2026 Session 24 AI / ML
A Touch-Embedded OLED Display-Driver IC with Display Noise Referencing and Display Coupling Noise Prediction Based on Dedicated Neural Networks for Mobile Applications with CoE Display
Yun-Rae Jo, Sewhan Na, Sanho Byun, Junchul Park, Gyeongmin Ha, Jiheon Ok, Tae-Gyun Song, Woo-Nyoung Lee, Jihyun Lee, Hyu
controller to overcome the interference issue between touch and display electrodes. In addition, an analog frontend (AFE) circuit is introduced to suppress coupling noise from display, and a dedicated neural network engi
Siwoo Kim, Jae-Youl Lee Samsung Electronics, Hwaseong, Korea Abstract
ISSCC 2026 Session 24 Sensors
A 10b Display Driver IC with a Pivoting Translinear-Loop DAC-in-Buffer Enabling 1μs 1-H Scan Time and 1722μm2 per Channel
Hyeong-Joon Kim, Yousung Park, Kihyun Kim, Seunghwa Shin, Hyun-Sik Kim
Abstract This paper presents a 10b display driver IC (DDI) for high-resolution OLEDs. It features a novel pivoting translinear-loop (PTL) DAC-in-buffer that overcomes the area, speed, and linearity trade-offs. A key enab
KAIST, Daejeon, Korea
ISSCC 2026 Session 24 Sensors
A 512ch 10b Source-Driver IC with Current-Mode Auto-Zeroing Scheme Achieving 1.4mV DVO and 600ns 1-Horizontal Time for Mobile OLED Displays
Yousung Park, Gyu-Wan Lim, Hyun-Sik Kim
Abstract This paper presents a 10b source-driver IC (SD-IC) for ultra-fast, uniform-luminance mobile OLED displays. A current-mode auto-zeroing (CM-AZ) scheme transparently cancels outputbuffer offset—lowering DVO with z
KAIST, Daejeon, Korea
ISSCC 2026 Session 24 Sensors
A 144mW 161Mpixels/s Tensor Display Processor for 3D Virtual Reality
Ching-Yen Lee, Yueh-Feng Tsai, Ying-Sheng Lin, Chia-Hsiang Yang
Abstract This work presents a 3D display processor that converts the focal stack to tensor display. Algorithm-architecture co-optimization is applied to reduce the computational complexity and hardware complexity. It ach
National Taiwan University, Taipei, Taiwan
ISSCC 2026 Session 24 Sensors
A 4042-PPI 10b 240Hz Digital-PWM CMOS Backplane for Micro-LED-on-Silicon Displays with a Shared, Unified Memory-in-Pixel Architecture
Kihyun Kim, Jun-Gi Lee, Hyun-Sik Kim
Abstract This paper presents a 10b 240Hz digital-PWM CMOS backplane for μLED-on-Silicon with a shared, unified memory-in-pixel structure. A unified D-FF chain (UDC) merges the in-pixel register, counter, and comparator i
KAIST, Daejeon, Korea
ISSCC 2026 Session 24 Sensors
A 28nm CMOS 1-Chip In-Pixel Memory Backplane Circuit with Pixel-Level Sensing and Compensation for 6652-PPI MicroLED AR Glasses
Yongil Kwon, Sunkwon Kim, Youngkil Choi, Taehyun Kwon, Seongyoung Ryu, Sewhan Na, Kangjoo Kim, Uijong Song, Hyun-Wook Li
6652-PPI microLED AR display. Pixel-level sensing with pBIST enables accurate calibration and compensation of current variation. The 2.7µm-pitch array integrates an 8b shifter with MSB latch for PWM. System techniques in
Samsung Electronics, Suwon, Korea Abstract This work presents a 28nm C
ISSCC 2026 Session 23 Wireline I/O
A 112Gb/s NRZ Heterodyne Detection 23ns Settled Burst-Mode RX with CD Suppression and Envelope Demodulation for 100G PON
Cheng Wang, Ye Gu, Gertjan Coudyzer, Shengpu Niu, Jing Zhang, Xin Yin
Abstract This work presents a burst-mode receiver based on an intensity modulation heterodyne detection scheme. SSB quadrature IF generation and envelope detection enhance baseband signal integrity and chromatic dispersi
imec - Ghent University, Ghent, Belgium
ISSCC 2026 Session 23 Wireline I/O
A 212Gb/s/λ 0.91pJ/b Direct-Drive O-Band Monolithic Coherent Transmitter Based on Carrier-Injection-Mode Mach-Zehnder Modulator
Antroy Roy Chowdhury1, Wahid Rahman1, Ahmed ElShater2, Tamer Ali2, Vladimir Stojanovic1,3
Abstract This work presents an O-band coherent direct-drive optical transmitter (OTX) in 45nm CMOS-SOI using a compact 0.4mm monolithically integrated forward-biased PIN-MZM. A multistage linear driver with shunt peaking
University of California, Berkeley, CA, 2MediaTek, Irvine, CA, 3Ayar L
ISSCC 2026 Session 23 Wireline I/O
A 6.4Tb/s 4.2pJ/b Co-Packaged Optics ASIC with Direct-Drive Integrated TIA and Retimed Segmented Mach-Zehnder Modulator Driver in 7nm FinFET
Mahdi Kashmiri, Ajay Yadav, Jin Namkoong, Behrooz Nakhkoob, Tony Kao, Shen Shen, Vaibhav Pandey, Kuan-Chang Chen, Jinho
4Tb/s co-packaged optics ASIC integrates 64 ingress path direct-drive TIAs and 64 egress path retimed segmented Mach-Zehnder modulator drivers in 7nm FinFET. The 7nm ASIC is 3D packaged with a photonics IC (PIC) and achi
Shayan Kazemkhani, Sang Young Kim, Simar Maangat, Bo Nguyen, Mike Robi
ISSCC 2026 Session 23 Wireline I/O
A 2×500Gb/s Monolithic Silicon-Photonic DWDM PAM-4 Transceiver in 45nm CMOS SOI
Ziang Xu*, Yalong Lin*, Jinxuan Jin*, Zhenkai Ye*, Dacheng Xu, Aolin Xu, Chaodi Sheng, Binwen Hong, Xiaojun Bi
*Equally Credited Authors (ECAs) Abstract This work presents a monolithic 2×5λ DWDM microring transceiver in 45nm CMOS SOI delivering 2×500Gb/s (100Gb/s PAM-4/channel). The transceiver features a low-noise TIA with Q-tam
Huazhong University of Science and Technology, Wuhan, China
ISSCC 2026 Session 23 Wireline I/O
A 2-Channel 800Gb/s Transceiver for Coherent-Lite Applications with <300ns Latency in 5nm FinFET
Marco Sosio1, Claudio Nani1, Enrico Monaco1, Nicola Ghittori1, Domenico Albano1, Alessio Di Pasquo1, Alessandro Bosi1, T
Fulvio Martinelli1, Victor Karam2, Devrishi Khanna2, Mehdi N. Khiarak2, Sasan Cyrusian3, Mehdi Davoodi3, Marco Garampazzi1, Nimesh N. Miral1, Fabio Giunco1, Ivan Fabiano1, Nicola Codega1, Claudio Asero1, Daniel L. Herbas
ISSCC 2026 Session 23 Wireline I/O
A 32Gb/s/λ 256Gb/s/Fiber Half-Rate Bandpass-Filtered Clock-Forwarding DWDM Optical Link in a 3D-Stacked 7nm EIC/65nm PIC Technology
Sanquan Song1, Nandish Mehta1, Nikola Nedovic1, Angad Rekhi1, Georgios Kalogerakis1, Li Xu1, Brian Zimmer1, Stephen G. T
Ward Lopes1, Benjamin G. Lee3, Thomas H. Greer III2, C. Thomas Gray2 Nvidia, Santa Clara, CA, 2Nvidia, Durham, NC, 3Nvidia, Ridgefield, CT 1 Abstract We present a 32Gb/s/λ dense wavelength division multiplexing bandpass-
ISSCC 2026 Session 22 Other
A 500kGy Radiation-Hardened 2.4GHz Wi-Fi Receiver for Innovative Nuclear Power Plant Decommissioning
Yasuto Narukiyo1, Sena Kato1, Kotaro Yanaka1, Yuya Takahashi1, Masaya Miyahara2, Jill Mayeda1, Atsushi Shirane1
Abstract This work presents a 2.4GHz Wi-Fi receiver in 65nm CMOS, designed with radiationhardened techniques to sustain operation under total ionizing dose to 500kGy. Such tolerance addresses the requirements of nuclear
Institute of Science Tokyo, Tokyo, Japan, 2High Energy Accelerator Res
ISSCC 2026 Session 22 Other
A Radiation-Hardened Self-Healing CMOS Imager with Online Pixel/Logic Annealing and Tile-Adaptive Compression for Space Applications
Quan Cheng*1,2, Zhengke Yang*1, Haoyuan Li2, Qiufeng Li1, Zhen Kong1, Gaoqiang Niu1, Yuan Liang1, Jiamin Li1, Jerald Yoo
Abstract CMOS imagers in space suffer radiation-induced faults and downlink bandwidth limits. This work presents an 180nm self-healing imager with localized online thermal annealing for both pixels and logic, as well as
Southern University of Science and Technology, Shenzhen, China, 2Kyoto
ISSCC 2026 Session 22 Other
A Multi-Qubit Cryo-CMOS SoC with Polar-Based Electron-Spin and PDM-Based Nuclear-Spin Controllers for Color Centers in Diamond
Niels Fakkel*, Luc Enthoven*, Mohamed Abdelrahman Elbadry, Hendrik Benjamin van Ommen, Margriet van Riggelen, Jiwon Yun,
nitrogen-vacancy (NV) centers in diamond enables a scalable quantum platform. This work introduces a combined Class-DE RFDAC and classD PDM driver for multi-qubit electron- and nuclear-spin control. A switch allows share
Fabio Sebastiano**, Masoud Babaie** TU Delft, Delft, The Netherlands *
ISSCC 2026 Session 22 Other
A 16-Channel Low-Power Cryo-CMOS Flux Control Pulse Generator ASIC in 14nm FinFET Technology
Kevin Tien1, David J. Frank1, John F. Bulzacchelli1, Pat Rosno2, Daniel Moertl2, John Timmerwilke1, Ari Noori1, Devin Un
Daniel Ramirez2, Timothy J. Schmerbeck2, Bryce Snell2, Jeremy Ekman2, Ryan Black2, Mark Yeck1, Tom Haselhorst2, Emma Erickson2, Kevin Demsky2, Christian W. Baks1, Jonathan Kaus2, Andrea Ruffino3, Pier Andrea Francese3, A
ISSCC 2026 Session 22 Other
A Cryo-CMOS Color-Center Quantum Controller with Diamond Waveguide Micro-Chiplet Integration
Jinchen Wang, Yuyang Han, Isaac B. Harris, Eunseok Lee, Yong Hu, Di Liu, Dirk Englund, Ruonan Han
Abstract We present a scalable cryo-CMOS controller for color-center-based quantum processors. A diamond waveguide micro-chiplet with NVs is pick-and-placed on CMOS with a 3D-printed prism for scalable photonic readout.
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2026 Session 21 RF & Wireless
A -82.3dB THD+N 60V Fully Integrated Shunt-Resistor-Based In-Line Current Sensor with DLL-Assisted Dynamic Body-Biasing Technique
Heng Ma, Huajun Zhang, Qinwen Fan
Abstract Floating-Gm-based current sensors are effective in rejecting PWM common-mode voltage. But their linearity drops at high voltages due to substrate-current-induced body effect in LDMOS devices. To address this iss
TU Delft, Delft, The Netherlands
ISSCC 2026 Session 21 RF & Wireless
A CMOS Hybrid Common-Gate Current-Integrating Sampler with >37dB SNDR Across 51GHz BW in a 128GS/s Front-End
Jun Dai1, Yi Zhong1, Yunsong Tao1, Aodong Zhang1, Mingtao Zhan1, Hao Zhang2, Lu Jie1, Nan Sun1
Abstract This work proposes a CMOS hybrid common-gate current integrating sampler to address linearity, BW, and jitter limitations in prior wideband ADC front-ends. The front-end employs a hybrid common-gate V-I converte
Tsinghua University, Beijing, China, 2Magnichip, Nanjing, China
ISSCC 2026 Session 21 RF & Wireless
A Battery-Free Wireless Electrochemical-Interface SoC Featuring 143dB Dynamic Range for Multimodal Wearables
Weixiao Wang, Yili Shen, Tianyi Cai, Qijing Xiao, Yuxuan Luo, Bo Zhao
Abstract A battery-free wireless electrochemical-interface SoC is implemented and demonstrated in a sweatband prototype for physiological monitoring in body sweat, where the proposed techniques improve the dynamic range
Zhejiang University, Hangzhou, China
ISSCC 2026 Session 21 RF & Wireless
A ±60mA-Inaccuracy Low-Side Average Current Sensor with Operating-Conditions-Insensitive Control Supporting 0.1-to-3A Load Range and Sub-100ns Sample Time for Automotive USB Charge Application
Jian-Jun Kuang1,2, Xin Ming1, Xin-Ce Gong1, Tian-Chen Lang2, Xiang Geng2, Bo Zhang1
Abstract In Paper 21.6, UESTC and SouthChip Semiconductor Technology present a low-side average current sensor for automotive USB charging, which supports 0.1-to-3A load range and sub100ns sample time with ±60mA inaccura
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2026 Session 21 RF & Wireless
A 0.6V 625um2 Fully Stacked RC-Based Temperature Sensor Using Low TCR Metal Resistor Achieving 0.017nJ·%2-Accuracy FoM in 2nm Gate-All-Around Process
Haejung Choi, Jooseong Kim, Woojoong Jung, Sungmin Yoo, Jun-Hyeok Yang, Sunghyuck Lee, Jihye Park, Michael Choi, Ben Rhe
Abstract The proposed RC-based temperature sensor, fabricated on a 2nm gate-all-around process, minimizes silicon area by fully stacking low temperature coefficient of resistance (TCR) metal resistors and a ring-oscillat
Samsung Electronics, Yongin, Korea