全部论文

Papers 2008–2026

共 3875 篇 ISSCC 论文，按年份倒序排列

年份 Year
2026 2472025 2422024 2222023 2002022 1672021 1952020 2022019 1812018 2052017 2082016 2002015 1912014 2032013 2102012 1882011 1962010 2102009 1802008 228
领域 Topic
RF & Wireless 362Power Management 302Wireline I/O 300Wireless 293Data Converters 279Digital Processors 268Memory 266AI / ML 231Digital Circuits 220Medical & Bio 211Image Sensors 184Analog Circuits 169mm-Wave 138Clocking & PLLs 127Sensors 100Plenary 63Hardware Security 36Quantum & Photonics 29Industry Highlights 7
顶级机构
University of California 101Delft University of Technology 73University of Macau 58KAIST 51Massachusetts Institute of Tec 48Tsinghua University 39National Taiwan University 38University of Michigan 37Georgia Institute of Technolog 35Columbia University 28Hong Kong University of Scienc 24MediaTek 23
ISSCC 2026 Session 21 RF & Wireless
A Background-Calibrated NPN-Based Temperature Sensor with 0.05°C (3σ) Inaccuracy from -70°C to 125°C
Nandor G. Toth, Kofi A. A. Makinwa
Abstract In this work, an NPN-based temperature sensor is presented that introduces a backgroundcalibration scheme to correct all current-domain errors in its front-end. It achieves an inaccuracy of 0.05°C (3σ) from -70°
TU Delft, Delft, The Netherlands
ISSCC 2026 Session 21 RF & Wireless
A Temperature- and Aging-Compensated TMR Current Sensor with ±0.13% Sensitivity Variation from -40°C to 120°C
Tianxiang Qu, Nan Wang, Kaiwen Zhou, Jiayao Liu, Longxi Xiang, Mingqian Sun, Zhiliang Hong, Xiaoyang Zeng, Jiawei Xu
Abstract This paper presents a TMR-based contactless current sensor that mitigates sensitivity drift due to temperature and aging. The proposed sensitivity stabilization loop continuously adjusts the TMR sensitivity, mak
Fudan University, Shanghai, China
ISSCC 2026 Session 21 RF & Wireless
A Fully Integrated GMR Biosensor with On-Chip Coils and Sensors Achieving 605 Resolution FoM for Multiplexed PoC Diagnostics
Mengze Wu1, Remy Lassalle-Balier2, Pablo Aguirre3, Florencia Ferrer3, Sina Haji Alizad4, Shekher Kummari1, Alex Latham4,
Abstract This paper presents a fully integrated GMR biosensor chip for point-of-care in vitro diagnostics featuring on-chip sensors, excitation coils, and a digital back-end. The system achieves 120nTrms noise, 0.38ppm s
University of California, San Diego, CA, 2Allegro MicroSystems, Chavan
ISSCC 2026 Session 20 AI / ML
A Compact 26/38GHz-Reconfigurable Dual-Band Low-Noise Amplifier Using Transformer-Based Pole-Zero-Inversion Image-Rejection Technique Achieving >39/41dB IRR for 5G Multi-Band Applications
Jiaming Luo, Jincai Wen, Yuxia Wu, Xu Wang, Lingling Sun
Abstract This paper presents a compact 26/38GHz reconfigurable dual-band low-noise amplifier (LNA) for a narrow-LO dual-side mixing. By adopting a transformer-based pole-zeroinversion image-rejection technique, the LNA a
Hangzhou Dianzi University, Hangzhou, China
ISSCC 2026 Session 20 RF & Wireless
A 16-to-256QAM G-Band Subharmonic Phase-Modulating Transmitter for Beyond-5G Communications
Jia Zhou1, Jieqiong Du1, Chao-Jen Tien1, Jhih-Wei Chen1, Ruei-Chen Soong1, Francisco Cardenas Beltran1, Lachlan Cuskelly
Angeles, CA, 3NXP Semiconductors, San Jose, CA. 1 Abstract This paper presents a highly integrated G-band digital transmitter for beyond-5G communications featuring: 1) a subharmonic phase-modulating architecture with ti
Adrian Tang1,2, Sai-Wang Tam3, Mau-Chung Frank Chang1 University of Ca
ISSCC 2026 Session 20 RF & Wireless
An Ultra-Compact D-Band Transceiver Front-End Based on a Common-Gate Bidirectional Amplifier Achieving 11.2dBm TX Psat and 8.2dB RX Average NF for an Area-Constrained 2D Beamformer AiP
Syed Mohammad Ashab Uddin1,2, Wooram Lee1
Abstract An ultra-compact D-band transceiver based on a common-gate bi-directional amplifier is presented in a 45nm RFSOI process for an area-constrained 2D beamformer antenna-inpackage. By employing a switchless symmetr
Pennsylvania State University, University Park, PA, 2Texas Instruments
ISSCC 2026 Session 20 RF & Wireless
A 330-to-344GHz GaN Power Amplifier with Maximum-Available-Gain-Boosting Technique and Compact Tandem Coupler Achieving 86mW Output Power at 340GHz
Weibo Wang*1,2, Wenhua Chen*3, Kenan Xie*4, Chenjie Luo2, Yibin Zhang2, Dechun Shang2, Ziwei Jiang2, Guodong Yu2, Yan Ch
Tianjin University, Tianjin, China *Equally Credited Authors (ECAs) 1 4 Abstract This paper demonstrates a 330-to-344GHz GaN power amplifier (PA), fabricated using a 35nm GaN HEMT process with a 15-stage cascaded archite
National Key Laboratory of Solid-State Microwave Devices and Circuits,
ISSCC 2026 Session 20 RF & Wireless
OP1dB Deviation (dB) 14.0 13.5 12.5 PAE (%) PAE (%) Power Gain (dB) Pout (dBm) VSWR @ 13GHz Pout (dBm) PG Deviation (dB) VSWR Angle (o) RIMD7U VSWR @ 13GHz VSWR Angle (o) VSWR Angle (o) PAEOP1dB -PAEOP1dB@50Ω 48.25dBc RIMD5U Main Tone RIMD7L RIMD5L RIMD3L 27.5dBc Coupled Tone RIMD3U PG Deviation (dB) Pout (dBm) PG Deviation (dB) VSWR @ 13GHz PAEOP1dB -PAEOP1dB@50Ω Large Signal Performance PAEOP1dB -PAEOP1dB@50Ω OP1dB Deviation (dB) S12 S22 VSWR 4:1 OP1dB Deviation (dB) Power Gain (dB) S11 VSWR 3:1 PAE (%) Power Gain (dB) VSWR 2:1 CW @ 12.25GHz S21
Figure 20.4.3: Measured PA S-parameters, stability factors, and large-signal, VSWR Angle (o)
VSWR Angle (o) VSWR Angle (o) performance at 12.25GHz (top), and across the frequency (bottom right); and the RIMD Figure 20.4.4: Large-signal performance of the PA across the 12.5-to-14.5GHz frequency range under three
ISSCC 2026 Session 20 RF & Wireless
A mm-Wave Doherty Power Amplifier in a Single-Path Footprint Using Compact Reciprocal Doherty Networks
Lianbo Liu1, Yidong Fang1, Qiang Zhou2, Taiyun Chi2, Sensen Li1
Abstract This paper presents a compact, single-path-footprint Doherty PA with minimized passive network areas. A systematic analysis for its realization is developed based on the proposed theory of reciprocal Doherty net
University of Texas, Austin, TX, 2Rice University, Houston, TX
ISSCC 2026 Session 20 RF & Wireless
A High Back-off Efficiency Unequal-Stacked Doherty Power Amplifier Achieving 16.7dBm Pavg in a 22nm FDSOI CMOS Technology for 5G FR2 Applications
Seungwon Park, Jooseok Lee, Seungjae Baek, Taewan Kim, Yifei Chen, Sehyug Jeon, Sung-gi Yang
Abstract This paper proposes an unequal-stacked Doherty power amplifier. The proposed Doherty structure consists of a common-source topology for the carrier amplifier and an N-stacked topology for the peaking amplifier w
Samsung Electronics, Seoul, Korea
ISSCC 2026 Session 20 RF & Wireless
A 215GHz 8×8 Radiator-Oscillator Array with Robust Coupling Achieving 25.5dBm EIRP and 12.9% FTR
Ahmed Elmenshawi1, Sriram Muralidharan2, Mona M. Hella1
Abstract A 215GHz 8×8 radiator-oscillator array with robust coupling achieving 25.5dBm average EIRP over a 12.9% continuous frequency tuning range. The proposed coupling scheme, based on distributed coupling through mult
Rensselaer Polytechnic Institute, Troy, NY, 2Oso Semiconductor, Berkel
ISSCC 2026 Session 20 RF & Wireless
A 214-to-242GHz Miniaturized Co-Packaged PA-Antenna Array with 29dBm Lens-less EIRP in a 0.13μm SiGe Process
Qianqi Meng, Zhihua Wang, Peigen Zhou, Dawei Tang, Siyuan Tang, Junyue Xiao, Rui Zhou, Jinben Li, Zhe Chen, Jixin Chen,
Abstract This work presents a miniaturized, high-power, and wideband THz PA-antenna array, realizing 29dBm lens-less peak EIRP from 214 to 242GHz. To improve the BW and Psat of the PA, a folded 10th-order power-splitting
Southeast University, Nanjing, China
ISSCC 2026 Session 20 RF & Wireless
An Ultra-Compact Asymmetrically Load-Pulled Series Doherty Power Amplifier in 22nm FDSOI CMOS with 25.3dBm Psat and 29.7% PAE6dB for Ku-Band 6G FR3
Jinglong Xu1, Tzu-Yuan Huang1,2, Mohamed Eleraky1, Islam Tolaib1, Hua Wang1
Abstract This paper presents an ultra-compact asymmetrically load-pulled series Doherty PA in 22nm CMOS SOI with a single-footprint output combiner. A quantitative analysis of a single transformer as an impedance inverte
ETH Zurich, Zurich, Switzerland, 2ARGUS SPACE AG, Zurich, Switzerland
ISSCC 2026 Session 2 Digital Processors
A 0.24mJ/Frame Quadratic Interpolation 4DGS Processor with Recursive Computation Reuse and Tree-Based Parallel-Rendering
Xiaolong Yang, Yang Wang, Wende Xu, Yubin Qin, Huanyu Wang, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu,
Abstract 4D Gaussian Splatting (4DGS) has widespread applications in fields such as VR, AR and industrial simulation. However, 4DGS suffers from significant memory requirements, redundant computations and low PE utilizat
Tsinghua University, Beijing, China
ISSCC 2026 Session 2 AI / ML
Tiamat: A 98-to-134ms/Step Transformer-Based Diffusion Model Processor Supporting Classifier-Free Guidance for Image Generation
Po-Yen Lu, Po-Wei Chen, Shau-Hua Yeh, Zhi-Jun Zhang, Yong-Tai Chen, Ting-Yu Wang, Chao-Tsung Huang
Abstract A 16nm FinFET transformer-based diffusion model processor chip is fabricated for supporting class-conditional DiT-XL/2 and text-to-image PixArt-α with 98ms and 134ms generation time per step with 7.37TOPS and 14
National Tsing Hua University, Hsinchu, Taiwan
ISSCC 2026 Session 2 Digital Processors
Spyre: An Inference-Optimized Scalable AI Accelerator for Enterprise Workloads
Matthew Cohen1, Monodeep Kar1, Swagath Venkataramani1, Viji Srinivasan1, Brian Veraa2, Matthew Ziegler1, Nianzheng Cao1,
Michael Guillorn1, Sandra Woodward3, JohnDavid Lancaster1, Josh Hursey4, Kyu-hyoun Kim1, Alberto Mannari5, Amrit Nagarajan1, Ananda Samajdar1, Bahman Hekmatshoartabari1, Bob Galbraith3, Ching Zhou1, Dave Satterfield1, Gr
ISSCC 2026 Session 2 AI / ML
UniC-Vision: A 14.4Gb/s 7.3pJ/b Universal Vision Transformer OFDM Channel Estimation Accelerator for B5G/6G AI-RAN
Sangbu Yun1,2, Chanhee Lee1,2, Soonhyun Kwon1, Jeongtaek Chang3, Zhengya Zhang3, Youngjoo Lee1
Abstract This work presents an AI-RAN channel estimation accelerator for next-generation communications, offering hyper reliability, low latency, and universal frequency range coverage, thereby meeting B5G/6G requirement
Korea Advanced Institute of Science and Technology, Daejeon, Korea, 2P
ISSCC 2026 Session 2 Digital Processors
A 71.3mJ/Frame End-to-End Driving Processor with Flexible Heterogeneous Core Orchestration via Sparsity Reasoning
Jueun Jung*1,2, Sangho Lee*1, Junghyun Yoo2, Ghangmin Yun2, Kyuho Jason Lee2
*Equally Credited Authors (ECAs) 1 Abstract A multi-modal end-to-end driving processor is proposed with 4 features: 1) a sparsity reasoning unit to maximize sparsity exploitation, 2) a flexible sparse-dense heterogeneous
Ulsan National Institute of Science and Technology, Ulsan, Korea, 2Yon
ISSCC 2026 Session 2 Digital Processors
A Quad-Chiplet AI SoC with Full-Chip Scalable Mesh Over 16Gb/s UCIe-Advanced Die-to-Die Interface for Large-Scale AI Inferencing
Chang-Hyo Yu, Jaewan Bae, Jinseok Kim, Hongyun Kim, Wongyu Shin, Jae-Sung Yoon, Young-Jae Jin, Jungju Oh, Jaebong Lee, E
Sungpill Choi, Donghan Kim, Hyunje Jo, Hyunho Kim, Hyungseok Heo, Hyunsung Kim, Seung-Goo Kim, Myunghoon Choi, Sangeun Je, Junhee Ham, Juyeong Yoon, Yashael Faith Arthanto, Sung-il Bae, Sanggyu Park, Joungwoo Lee, Heeyou
ISSCC 2026 Session 2 Digital Processors
A 1286fps 0.39mJ/Frame Modeling/Rendering Unified 3D GS Processor with Locality-Optimized Computation and Reconfigurable Architecture
Hedi Wang*, Xiaoyu Feng*, Weichen Gao, Huazhong Yang, Yongpan Liu
*Equally Credited Authors (ECAs) Abstract A modeling/rendering unified 3D GS processor is proposed with: 1) A locality-aware dynamic fine-grained rendering engine for reduced redundant computation. 2) A locality-optimize
Tsinghua University, Beijing, China
ISSCC 2026 Session 2 Digital Processors
AMD Instinct MI350 Series GPUs: CDNA 4-Based 3D-Stacked 3nm XCDs and 6nm IODs for AI applications
Ramasamy Adaikkalavan1, Alan Smith1, Teja Singh1, Sundar Rangarajan1, Eric Chapman1, Samuel Naffziger2, Subramaniam Maiy
Sriram Sundaram1, Mark Silla1, Duncan Law5, Kathy Hoover1, Samuel Lipson1, Kevin Duda2, Vinay Parthasarathy6, Deepesh John1, Hanish Vemulapalli1, Srinivas Pavan Kumar Gade7 AMD, Austin, TX, 2AMD, Fort Collins, CO, 3AMD,
ISSCC 2026 Session 19 Power Management
A 2.15W 120V/230Vac to 5-to-12Vdc Offline Power Converter with Full-Duty-Cycle Input-Series Dual-Branch Converter Achieving 1088mW/cm3 and 87.2% Peak Efficiency
Gang Liu1,2, Junmin Jiang2, Sijun Du3, Xun Liu1
Abstract This paper presents a 120V/230Vac to 5-to-12Vdc offline power converter consisting of a capacitor-drop AC-DC rectifier and a full-duty-cycle input-series dual-branch DC-DC converter for IoT devices. The proposed
Chinese University of Hong Kong, Shenzhen, China, 2Southern University
ISSCC 2026 Session 19 AI / ML
A Fully Integrated Bidirectional 5-Level Isolated DC-DC Converter with 42.5% Efficiency and 170mW/mm2 Transformer Power Density
Kishalay Datta, Yue Wu, Charles Sullivan, Jason Stauth
Abstract This work presents a bidirectional 5kV-isolated DC-DC converter, fully-integrated in a 180nm SOI CMOS process. The design uses a distributed multi-winding transformer to maximize utilization of the standard on-c
Dartmouth College, Hanover, NH
ISSCC 2026 Session 19 Power Management
A Hybrid Bipolar-Output Isolated Converter with +15V/–5V Outputs for SiC Gate Drivers
Joo-Mi Cho, Jeong-Hun Kim, Yong-Chan Lee, Sung-Wan Hong
Abstract This paper presents a hybrid bipolar-output isolated (HBO-I) gate-driver power supply (GDPS) that combines a flyback-based TX with primary-side regulation (PSR) and a switched-capacitor-based RX. Even with a com
Sogang University, Seoul, Korea
ISSCC 2026 Session 19 AI / ML
A 68%-Peak-Efficiency Single-Transformer Multi-Output Isolated DC-DC Converter with a Regulated Negative Rail
Qiao Huang*1, Dongfang Pan*1, Weiwei Xu2, Yongle Zhang1, Lin Cheng1,2
*Equally Credited Authors (ECAs) 1 Abstract This paper presents a single-transformer multi-output isolated DC-DC converter generating three regulated rails (+15V, −5V, and +5V) from wide 12/24V inputs. By sharing a commo
University of Science and Technology of China, Hefei, China, 2Hefei CL
ISSCC 2026 Session 19 Power Management
A Binary-Weighted Switched-Capacitor Gate Driver IC for Overcoming Trade-offs Between Driving Loss and Delay Time with Gate-Current Feedback Achieving 85% Driving Loss Reduction
Kohei Horii, Koutaro Miyazaki, Shusuke Kawai, Hiroaki Ishihara
Abstract A binary-weighted switched-capacitor gate driver IC achieving up to 85% reduction in driving loss (Edrv) is presented. Four binary-weighted flying capacitors enable nine-level gate-voltage segmentation, enhancin
Toshiba, Kawasaki, Japan
ISSCC 2026 Session 19 Power Management
A Digital-Feedback Active-Gate-Driver IC for 600A 1200V SiC MOSFETs Supporting High- and Low-Side Drive with Simultaneous dVds/dt Control and Vds Surge Suppression Enabled by Miller Capacitance Calibration
Shusuke Kawai, Kohei Horii, Koutaro Miyazaki, Yuto Bushimata, Satoshi Takaya, Hiroaki Ishihara
Abstract A digital feedback active gate driver IC applicable to both high- and low-side 600A, 1200V SiC MOSFETs is proposed and demonstrated on the high-side. High-side voltage sensing uses a parasitic Miller capacitance
Toshiba, Kawasaki, Japan
ISSCC 2026 Session 19 Power Management
A 94.8%-Peak-Efficiency Double Step-Up SIBO Converter Achieving 88% Output Ripple Reduction for AMOLED Display
Hyeon-Ji Choi, Joo-Mi Cho, Sang-Yun Nam, Sung-Wan Hong
Abstract This paper presents a double step-up single-inductor bipolar-output (DSU-SIBO) converter for AMOLED displays. By employing a 1:2 charge pump, the proposed design reduces both DC and AC components of the inductor
Sogang University, Seoul, Korea
ISSCC 2026 Session 19 Power Management
A Three-Mode Single-Inductor Four-Quadrant Converter Achieving 94.6% Peak Efficiency with Seamless Zero-Crossing
Peng Cao1,2, Jiawei Xu2, Zhiliang Hong2
Abstract This paper presents a three-mode single-inductor four-quadrant converter with 94.6% peak efficiency for electrochromic smart windows. It supports a 5 to 12V input, a −5 to +5V output and a −3 to 3A load current,
Nanjing University, Suzhou, China, 2Fudan University, Shanghai, China
ISSCC 2026 Session 19 Power Management
Piggybacked SC-on-CSCR: A Modular On-Chip Switched-Capacitor Converter for 12-to-60V Input 1.8-to-5V Output Achieving 5.67mW/mm2 Power Density and 71.5% Peak Efficiency
Yunzhe Yang1, Xin Zhang2, Sijun Du1
Abstract This paper presents an on-chip switched-capacitor converter, named piggybacked SC-onCSCR, featuring: 1) a power density of 5.67mW/mm2 enabled by eliminating high-voltage switches and jointly utilizing MOM and MO
Delft University of Technology, Delft, The Netherlands, 2IBM T. J. Wat
ISSCC 2026 Session 18 Other
A 28nm 47.3TFLOPs/W 894mJ/Inference Visual Autoregressive Accelerator with Differential-Amplifier Speculation and Chain-Reaction-Like Parallel Generation
Zhiheng Yue*, Xujiang Xiang*, Jiamu Fu, Shaojun Wei, Yang Wang, Yang Hu, Shouyi Yin
*Equally Credited Authors (ECAs) Abstract To accelerate Visual Autoregressive (VAR) applications, this work implements a 28nm VAR accelerator achieving 47.3TFLOPs/W and <0.6% FID loss. A differential visual attention amp
Tsinghua University, Beijing, China
ISSCC 2026 Session 18 AI / ML
SpikeRAM: A 48.1pW/Synapse/Bit Event-Driven Spiking Compute-Near/In-Memory Processor with Neuromorphic Sensor Enabling Life-Long On-Chip Learning
Haotian Fu1, Yue Zhou1, Zhuo Zhang1, Hongzhao Zheng1, Renxu Yang1, Yulong Huang1, Dezhen Yang2, Yannan Xing3, Tugba Demi
Switzerland, 5SynSense, Ningbo, China 1 4 Abstract SpikeRAM is a high efficiency (48.1pW/Synapse/Bit) memory-centric neuromorphic system with perception, computing and on-chip learning, achieving 464M synapses and 8.28mW
Hong Kong University of Science and Technology, Guangzhou, China, 2Nor
ISSCC 2026 Session 18 Other
SMoLPU: 122.1μJ/Token Sparse MoE-Based Speculative Decoding Language Processing Unit with Adaptive-Offload NPU-CIM Core
Sangwoo Ha1, Jingu Lee1, Youngjin Moon1, Sunjoo Whang1, Wooyoung Jo1, Gwangtae Park1, Sangjin Kim1, Soyeon Um2, Junha Ry
decoding LLM processor with an NPU-CIM core. It has 3 features: 1) Token-adaptive expert refinement removes redundant expert activations and schedules expert load order, achieving 2.3×/4.2× energy efficiency improvement
KAIST, Daejeon, Korea, 2Massachusetts Institute of Technology, Cambrid
ISSCC 2026 Session 18 AI / ML
A 22nm 1.87ms/Frame Streaming Multi-Speaker ASR Accelerator Leveraging Contextual-Aware Redundancy Skipping with 2D-Writable Microscaling Compute-in-Memory and Similarity-Aware TCAM Design
Wenjie Ren*, Mingxuan Li*, Zhenghao Jin, Yifan Ding, Ruohuang Xu, Xiangjun Ye, Yufei Ma, Tianyu Jia, Le Ye
*Equally Credited Authors (ECAs) Abstract This paper presents a DCIM-based accelerator for on-device streaming multi-speaker ASR (MS-ASR), featuring: 1) a context-aware redundancy skipping scheme with online sparse block
Peking University, Beijing, China
ISSCC 2026 Session 18 Other
A 3.19pJ/b Electro-Optical Router with 18ns Setup Frame-Level Routing and 1-to-6 Wavelength-Flexible Link Capacity for Photonic Interposers
Yvain Thonnart1, Christian Bernard2, Stéphane Bernabé2, Myriam Assous2, Laura Boutafa2, Benoit Charbonnier2, Rémi Frania
Vincent Josselin2, Stéphane Malhouitre2, Laurent Mendizabal2, André Myko2, Damien Saint Patrice2, Rémi Vélard2, Jean Charbonnier2 CEA-List, Grenoble, France, 2CEA-Léti, Grenoble, France 1 Abstract Global interconnect on
ISSCC 2026 Session 17 Other
Maia: A Reticle-Scale AI Accelerator
S. Xu1, G. Mandal1, S. Jahagirdar1, S. Tripathy2, P. Parthasarathy1, S. Srinivasan1, A. Levin1
Microsoft, Mountain View, CA, 2Microsoft, Bengaluru, India 1 Abstract In Paper 17.4, the architecture and implementation of Microsoft’s MAIA AI silicon, a reticlescale 750W AI SoC, is presented. Innovation across power d
ISSCC 2026 Session 17 Other
ARIES and REGULUS: A Unified and Scalable Hardware-Software Co-Designed NPU SoC Family for On-Device and On-Premises Multimodal Inference
D. Shin, H. Yang, S. Jeon, J. Park, S. Han, J. Park, J. Lee, J. Kim, H. Kim, Y. Oh, M. Kim, C. Jung, W. Kim, S. Kim, H.
Y. Min, C. Song, A. Kanybek, Y. Jung, J. Song, S. Cho, H. Na, J. Park, D. Si, B. Lee, B. Park, H. Jeon Mobilint, Seoul, Korea Abstract We present a scalable NPU architecture, proven in two SoCs (ARIES and REGULUS), desig
ISSCC 2026 Session 17 Other
The STM32N6 Microcontroller: Enabling Intelligent Edge AI for IoT and Beyond
G. Desoli1, J-F. Agaësse2, N. Chawla3, E. Hilkens2, T. Boesch4, V. Taufour2, M. Ayodhyawasi3, P. Ravenhill2, S. Pal-Sing
Abstract The STM32N6 microcontroller meets the growing need for intelligent edge devices in IoT, wearables, industrial automation, and smart home systems supporting real-time, energyefficient AI processing at the edge, r
STMicroelectronics, Cornaredo, Italy, 2STMicroelectronics, Grenoble, F
ISSCC 2026 Session 17 Other
NVIDIA GB10: SoC Built for AI Acceleration
A. Skende1, G. Rosseel2, N. Pinckney3
Nvidia, Westford, MA, 2Nvidia, Santa Clara, CA, 3Nvidia, Austin, TX 1 Abstract This paper details the GB10 SoC that powers the recently launched DGX™ Spark workstation. A dual-die solution, fabricated in TSMC’s 3nm proce
ISSCC 2026 Session 16 Power Management
A 96.6% Single-Mode Hybrid Dual-Path Buck-Boost Converter with Conduction Loss Reduction through Conversion-Ratio-Based Adaptive 3-Phase Control
Minsu Kim1, Yunho Lee1, Hyunjun Park1, Hongseok Kim1,2, Woojoong Jung1,2, Minwoo Kim2, Junhyun Bae2, Hyoung-Seok Oh2, Hw
Abstract This paper presents a 3-phase dual-path buck-boost converter that effectively reduces conduction loss by combining a dual-path topology with adaptive 3-phase control. The proposed control technique minimizes ind
Korea University, Seoul, Korea, 2Samsung Electronics, Hwaseong, Korea
ISSCC 2026 Session 16 Power Management
A Battery Charger Based On Mesh-Connection 2×CF Continuously-Scalable-Conversion-Ratio Converter Achieving 3.2W/mm3 Power Density
Yuanfei Wang1, Zhiyuan Zhang1, Yihan Zhang2, Rui P. Martins1, Mo Huang1
Abstract This work presents a battery charger for smartwatches based on a mesh-connected continuously scalable-conversion ratio converter that uses only two flying capacitors. The proposed design reduces the number of in
University of Macau, Macau, China, 2Hong Kong University of Science an
ISSCC 2026 Session 16 Power Management
A 90.7%-Efficiency Piezoelectric Resonator-Based Sigma Converter with 6-Phase 2-DoF On-Chip Regulation and Zero-Standby Sigma Mode for Transient and Output Power Enhancement
Shunmin Jiang1, Tiansu Wang1, Patrick Mercier2, Sijun Du1
Abstract This paper proposes an on-chip sigma regulation system for the accurate and power-efficient control of piezoelectric resonator (PR)-based DC-DC converters to address the challenges of conventional off-chip contr
Delft University of Technology, Delft, The Netherlands, 2University of
ISSCC 2026 Session 16 Power Management
A Parameter-Free Runtime-Energy-Loss Optimizer Achieving 2.15% Error in Energy-Recycling Duty-Cycled Systems
Jianxin Yang, Rui P. Martins, Mo Huang
Abstract This work proposes a predefined-parameter-free runtime-Eloss optimizer for energy-recycling duty-cycled systems. By leveraging a 3-level converter to recycle output-capacitance energy to the flying capacitor, it
University of Macau, Macau, China
ISSCC 2026 Session 16 Power Management
A Single-Inductor Multi-Channel Thermoelectric Energy Harvesting Interface Realizing Uneven Temperature MPPT with 39.6% Efficiency Enhancement and 62mV Tapped-Inductor-Oscillator-Based Start-Up
Yunzhe Yang, Sijun Du
Abstract This paper presents a thermoelectric energy harvesting (TEH) interface that realizes: 1) a multi-channel TEH for maximum power point tracking (MPPT) under uneven temperature conditions, improving efficiency by u
Delft University of Technology, Delft, The Netherlands
ISSCC 2026 Session 16 Power Management
A One-Stage Bidirectional Rectifier with Pre-Charge-Based MPPT for Triboelectric Energy Harvesting with 93% MPPT Efficiency and 8.86× Power Enhancement
Wenyu Peng, Jida Peng, Willem van Driel, Guoqi Zhang, Sijun Du
Abstract This work proposes a one-stage bidirectional rectifier with a pre-charge voltage (VPC) based perturb-and-observe (P&O) maximum power point tracking (MPPT) algorithm for triboelectric energy harvesting. The propo
Delft University of Technology, Delft, The Netherlands
ISSCC 2026 Session 16 Power Management
A Fully Integrated Piezoelectric Energy-Harvesting Interface with Single-Stage Bias-Flip and MPPT Achieving 5.63× Maximum Output Power Improving Rate
Xiaonan Wu1, Jinyi Yuan1, Minghao Shang1, Baochuang Wang1, Sijun Du2, Lin Cheng1
Abstract This paper presents a fully integrated PEH interface that enhances output power while minimizing on-chip capacitor area. The proposed design employs a SC structure that reuses both the piezoelectric capacitor an
University of Science and Technology of China, Hefei, China, 2TU Delft
ISSCC 2026 Session 16 Power Management
A Bias-Flip-Based Piezoelectric Energy Harvesting Interface with a Digital Track-and-Lock MPPT Achieving Sampling-Free Operation and 99.8% MPPT Efficiency
Rui Zhang1, Chuhui Wang2, Zhongxin Ye1, Ka Nang Leung2, Jianping Guo1
Abstract A fully digital MPPT is proposed for a bias-flip piezoelectric energy harvester. Once the MPP is identified, its parameters are stored and locked. Even if the vibration amplitude or frequency changes or disappea
Sun Yat-Sen University, Guangzhou, China, 2Chinese University of Hong
ISSCC 2026 Session 16 AI / ML
Fully Integrated mm-Scale 5G RF MIMO Harvester with -40dBm Sensitivity and Spatial MPPT via Hybrid Transformer-Based Combining/Shifting
Andrea Ballo1,2, Ruiyuan Yang2, Karim Ali2, Massimo Bruno Alioto2
Abstract A MIMO RF harvester in the 5G 28-GHz band with spatial MPPT is introduced to self-align high-gain harvesting direction with maximum power availability. Spatial scanning is enabled by a hybrid 2-level RF/DC anten
University of Catania, Catania, Italy, 2National University of Singapo
ISSCC 2026 Session 16 Power Management
PV Energy-Harvesting Interface Using Reconfigurable Self-Clamp CSCR Converter Achieving 3.83× High-Efficiency VCR Ratio and Open-Voltage-Sense-Free MPPT
Ziyang Zhong, Rui P. Martins, Mo Huang
Abstract This work presents a PV energy harvesting interface using a self-clamp CSCR SC converter. It reduces VCF stress without additional SC stages, enabling low-voltage CFs, 17.1mW/mm2 power density and 90% peak PCE.
University of Macau, Macau, China
ISSCC 2026 Session 15 Memory
A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme
Kiheung Kim*, Hong-Joo Song*, Youngdo Um, Jinhun Jang, Seungjun Lee, Hoseok Seol, Hye-Jung Kwon, Ji-Hwan Seol, Hoon Shin
JongMoon Choi, Sung-Woo Yoon, Sang Yun Kim, Dongkeon Lee, Minsoo Jang, Daehyun Kwon, Sangyong Lee, Jinguk Kim, Jonghyuk Kim, In Jung, Taeha Song, Chang Won Kim, Seung Ho Baek, Jinyong Choi, Young-Hun Seo, Won Ho Choi, Ch