ISSCC 2019
Session 6
Wireline I/O
A 180mW 56Gb/s DSP-Based Transceiver for HighDensity IOs in Data Center Switches in 7nm FinFET Technology
Po-Shuan Weng2, Yi-Chieh Huang2, Chun-Cheng Liu2, Chien-Hua Wu2, Shih-Hao Huang2, Chungshi Lin2, Ke-Chung Wu2, Kun-Hung Tsai2, Kai-Wen Tan2, Ahmed ElShater1, Kuang-Ren Chen2, Wei-Hao Tsai2, Huan-Sheng Chen2, Weiyu Leng1,
ISSCC 2019
Session 6
Wireline I/O
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET
Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta,
ISSCC 2019
Session 6
Wireline I/O
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss
Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto Huawei Technologies, Ottawa, ON, Canada With the introduction of PAM
ISSCC 2019
Session 6
Wireline I/O
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
wireline communications has led to emerging standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses (>20dB) [1], but their power consum
ISSCC 2019
Session 5
Image Sensors
A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS
characteristics of signals in the terahertz band (100GHz to 10THz) located between the millimeter wave band and the infrared band. In particular, terahertz waves have higher spatial resolution than mm-waves. Moreover, th
ISSCC 2019
Session 5
Image Sensors
A 256×256 40nm/90nm CMOS 3D-Stacked 120dBDynamic-Range Reconfigurable Time-Resolved SPAD Imager
Kingdom 3 Heriot-Watt University, Edinburgh, United Kingdom 1 2 Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to
ISSCC 2019
Session 5
Image Sensors
A 400×400-Pixel 6μm-Pitch Vertical Avalanche Photodiodes CMOS Image Sensor Based on 150ps-Fast Capacitive Relaxation Quenching in Geiger Mode for Synthesis of Arbitrary Gain Images
Yugo Nose, Motonori Ishii, Seiji Yamahira, Shigetaka Kasuga, Mitsuyoshi Mori, Tatsuya Kabe, Kentaro Nakanishi, Manabu Usuda, Akihiro Odagawa, Tsuyoshi Tanaka Panasonic, Nagaokakyo, Japan The intensive development of Sing
ISSCC 2019
Session 5
Image Sensors
Dual-Tap Pipelined-Code-Memory Coded-Exposure-Pixel CMOS Image Sensor for Multi-Exposure Single-Frame Computational Imaging
Nikita Gusev1, Gairik Dutta1, Rahul Gulve1, Harel Haim1, Manuel Moreno Garcia3, David Stoppa4, Kiriakos N. Kutulakos1, Roman Genov1 University of Toronto, Toronto, Canada Synopsys, Toronto, Canada 3 Fondazione Bruno Kess
ISSCC 2019
Session 5
Image Sensors
A 76mW 500fps VGA CMOS Image Sensor with TimeStretched Single-Slope ADCs Achieving 1.95e- Random Noise
Kumoh National Institute of Technology, Gyeongbuk, Korea 1 2 The demand for high-frame-rate CMOS image sensors is steadily increasing. Column-parallel single-slope (SS) ADCs are widely used in CMOS image sensors, because
ISSCC 2019
Session 5
Image Sensors
A Data-Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection
CA 1 2 Histograms of Oriented Gradients (HOG) are attractive features for object detection in embedded vision applications, as they provide a good trade-off between complexity and detection accuracy. A custom 8b CMOS ima
ISSCC 2019
Session 5
Image Sensors
Energy-Efficient Low-Noise CMOS Image Sensor with Capacitor Array-Assisted Charge-Injection SAR ADC for Motion-Triggered Low-Power IoT Applications
life, the demand for different sensor modalities, especially imaging, is rising. IoT imagers are often compact and have small form-factor batteries and thus must be designed with both low power (improving battery life) a
ISSCC 2019
Session 5
Image Sensors
A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration SingleFrame HDR and On-Chip Binarization Algorithm for Smart Vision Applications
Wenjie Shi2, Jinjian Hou2, Ke Shao2, Haojie Wang2, Pengge Xiao2, Zexu Shao2, Xiao Xie1, Xiaoyong Wang1, Chris Yiu1 SmartSens Technology, San Jose, CA SmartSens Technology, Shanghai, China 1 2 Request for smart vision rel
ISSCC 2019
Session 4
AI / ML
A 60GHz CMOS Power Amplifier with Cascaded Asymmetric Distributed-Active-Transformer Achieving Watt-Level Peak Output Power with 20.8% PAE and Supporting 2Gsym/s 64-QAM Modulation
Since its invention in early 2000s, Distributed Active Transformer (DAT) has been a popular power-combiner technique for high-power high-efficiency Power Amplifiers (PAs) in voltage-limited Silicon processes at GHz frequen
ISSCC 2019
Session 4
Power Management
A Highly Linear Super-Resolution Mixed-Signal Doherty Power Amplifier for High-Efficiency mm-Wave 5G Multi-Gb/s Communications
As the millimeter-wave (mm-wave) spectrum is believed to drive the next wireless communication revolution, there is a growing need for architectural research on advanced transmitter (TX) or power amplifier (PA) that can r
ISSCC 2019
Session 4
Power Management
A Compact DC-to-108GHz Stacked-SOI Distributed
Achieving 1.525THz GBW, 20.8dBm Peak P1dB, and Over 100Gb/s in 64-QAM and PAM-4 Modulation Omar El-Aassar, Gabriel M. Rebeiz University of California, San Diego, La Jolla, CA Distributed amplifiers (DAs) are important cir
ISSCC 2019
Session 4
Power Management
A mm-Wave 3-Way Linear Doherty Radiator with MultiAntenna Coupling and On-Antenna Current-Scaling Series Combiner for Deep Power Back-Off Efficiency Enhancement
There is a growing interest in exploring antenna-electronic co-designs that leverage antennas (including their low-loss metal structures, design versatility, multi-feed driving capabilities) as a new design paradigm to r
ISSCC 2019
Session 4
Power Management
A 13.5dBm Fully Integrated 200-to-255GHz Power Amplifier with a 4-Way Power Combiner in SiGe:C BiCMOS
In order to efficiently utilize the frequency band above 200GHz for radar and communication applications, enough transmitted output power is essential to overcome the elevated path loss. For silicon-based technologies, th
ISSCC 2019
Session 4
AI / ML
A Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Amplifier Using a Compact 2nd-Harmonic-Shorting Four-Way Transformer and Integrated Thermal Sensors proposed four-way transformer achieves simultaneous fundamental and 2ndharmonic impedance matching with the efficient parallel power combining capability.
Mark Doherty2, John D. Cressler1 The electro-thermal behavior of the output stage is described in Fig. 4.4.3. The thermal sensor QREF is located between two SiGe HBT arrays QP/QN in a symmetrical fashion to sense and tra
ISSCC 2019
Session 4
Power Management
A Multiphase Interpolating Digital Power Amplifier for TX Beamforming in 65nm CMOS
Future 5G communications will heavily leverage beamforming and MIMO techniques, owing to the improvement in data transmission capacity. In a transmit (TX) beamformer, the phase and amplitude of an array of TXs can be arb
ISSCC 2019
Session 4
AI / ML
A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement
Sophisticated OFDM modulation schemes with high spectrum efficiency and data throughput in modern wireless communication systems often result in a large peak-to-average power ratio (PAPR). Besides, wireless standards like
ISSCC 2019
Session 4
Power Management
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency
Modern wireless communication systems often utilize spectrum-efficient modulation schemes for higher data throughput, given the finite bandwidth. This type of modulation schemes, such as Orthogonal Frequency Division Multi
ISSCC 2019
Session 30
Wireline I/O
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCOBased Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator
generate low-jitter high-frequency signals, while using a ring VCO. In the sense that the VCO jitter is removed periodically by the reference clock, SREF, an MDLL also can be considered to be an ILCM. However, the most c
ISSCC 2019
Session 30
Wireline I/O
A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM output current of the I-SSCP is zero, which means the sampled input differential voltage (VSAM+-VSAM-) is around 0V. At the same time, (VP+-VP-) is also around 0V, and both VP+ and VP- are kept almost constant regardless of the output frequency.
To solve the issue of the conventional SSPD mentioned above, the LV SSPD (Fig. 30.8.3) is adopted. It adopts two high-level boosted inverters (HBINV) to enhance the turn-on voltage of the gate of M1 and M2 in the SSPD. T
ISSCC 2019
Session 30
Wireline I/O
An 8b Injection-Locked Phase Rotator with Dynamic Multiphase Injection for 28/56/112Gb/s Serdes Application
Growing traffic in data centers imposes multiple challenges on serial link design with higher speed and stringent power requirements. Clocking is one major challenge due to the significant portion of total power that clock
ISSCC 2019
Session 30
Wireline I/O
A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter
Yangjin Ma2, Tam Huynh2, Christopher Williams2, Leonardo Vera2, Yang Liu2, Ruizhi Shi2, Matthew Streshinsky2, Ari Novack2, Ran Ding2, Rick Younce2, Rafid Sukkar2, Jose Roman2, Michael Hochberg2, Sudip Shekhar1, Alexander
ISSCC 2019
Session 30
Wireline I/O
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS
Ryan Bespalko1, Dustin Dunwell1, James Bailey1, Bo Wang1, Alireza Sharif-Bakhtiar1, Michael O'Farrell1, Kerry Tang1, Anthony Chan Carusone2, David Cassan1, Davide Tonietto3 Huawei Technologies, Toronto, Canada University
ISSCC 2019
Session 30
Wireline I/O
A 32Gb/s 2.9pJ/b Transceiver for Sequence-Coded PAM-4 Signalling with 4-to-6dB SNR Gain in 28nm FDSOI CMOS
Intel, Santa Clara, CA 1 2 Multilevel signaling such as PAM-4 makes more efficient use of the better part of the channel response by mapping multiple bits in the same time interval (i.e. UI). At the same time, to achieve
ISSCC 2019
Session 30
Wireline I/O
A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems
Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi Toshiba Memory, Kawasaki, Japan High-bandwidth (BW) and large-capacity storage systems with NAND Flash memory (h
ISSCC 2019
Session 30
Wireline I/O
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
Cosimo Aprile1,2, Thomas Morf2, Marcel Kossel2, Alessandro Cevrero2, Ilter Ozkaya1,2, Andreas Burg1, Thomas Toifl2, Yusuf Leblebici1 EPFL, Lausanne, Switzerland IBM Zurich Research Laboratory, Rueschlikon, Switzerland 3 *
ISSCC 2019
Session 30
Wireline I/O
Single-Pair Automotive PHY Solutions from 10Mb/s to 10Gb/s and Beyond Gerrit W. den Besten
control busses to a high-performance data network for connecting sensors, processors, and actuators to enable autonomous driving [1]. A plurality of highbandwidth nodes like cameras, displays, radars, and wireless transc
ISSCC 2019
Session 3
Data Converters
A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier
architecture has been a popular choice for power-efficient ADCs used in applications such as medical imaging. The simple and scalable architecture of the SAR ADC enables efficient multi-bit conversion per stage [1,2] howev
ISSCC 2019
Session 3
Data Converters
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm
critical performance limiter. In “deep” pipelined ADCs that contain many stages, the clock tree constitutes a highly distributed network, with parasitics and mismatch creating skew between the different branches. Sufficie
ISSCC 2019
Session 3
Data Converters
A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 The two-step SAR ADC is an energy-efficient architecture for high-resolution applications, which faces headroom challenges from the voltage-domain resi
ISSCC 2019
Session 3
Data Converters
A 0.01mm2 25μW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor coupled CT pipelined ADC is suitable for a wide range of applications where information does not reside at DC, such as audio, biological, and communication signals by setting the proper pass band frequencies.
Shaolan Li1, Wenda Zhao1, Abhishek Mukherjee1, Nan Sun1 Figure 3.4.3 shows the overall schematic and timing diagram of the proposed ADC. At the rising edge of CLKsys, the 1st-stage CT SAR is triggered. After its operatio
ISSCC 2019
Session 3
Data Converters
A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS
Maarten Strackx2, Marcel J. M. Pelgrom1, Michiel Steyaert1, Marian Verhelst1, Filip Tavernier1 KU Leuven, Heverlee, Belgium Nokia Bell Labs, Antwerpen, Belgium 1 2 Emerging 5G communication systems require ADCs to direct
ISSCC 2019
Session 3
Data Converters
A 7.6mW 1GS/s 60dB SNDR Single-Channel SARAssisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier
Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Continuous technology scaling has allowed unceasing growth of the sampling rate of a single channe
ISSCC 2019
Session 3
Data Converters
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion
direct-RF sampling all rely on some form of residue amplification to minimize the number of interleaved channels and meet demanding specifications. Despite architectural efforts to reduce the total number of amplifiers in t
ISSCC 2019
Session 29
Quantum & Photonics
SHARC: Self-Healing Analog with RRAM and CNFETs
promising emerging technology for energy-efficient electronics (Fig. 29.8.1). Despite this promise, CNTs are subject to substantial inherent imperfections; every ensemble of CNTs includes some percentage of metallic CNTs
ISSCC 2019
Session 29
Quantum & Photonics
A 500Mb/s -46.1dBm CMOS SPAD Receiver for Laser Diode Visible-Light Communications
Kingdom 3 Photon Force, Edinburgh, United Kingdom 1 2 III-nitride laser diodes (LDs) are promising sources for light fidelity (LiFi) networks, underwater wireless optical communications (UWOC), and plastic optical fiber (P
ISSCC 2019
Session 29
Quantum & Photonics
A Digital-Type GaN Driver with Current-Pulse-Balancer Technique Achieving Sub-Nanosecond Current Pulse Width for High-Resolution and Dynamic Effective Range LiDAR System
applications, short laser pulse ILASER widths through GaN FET control methods and effective assurance of accurate ILASER are major challenges in highresolution light detection and ranging (LiDAR) systems (top of Fig. 29.
ISSCC 2019
Session 29
Quantum & Photonics
A Single-Chip Optical Phased Array in a 3D-Integrated Silicon Photonics/65nm CMOS Technology
Jelena Notaros2, Ami Yaacobi2, Erman Timurdogan2, Christopher Baiocco3, Nicholas Fahrenkopf3, Seth Kruger3, Tat Ngai3, Yukta Timalsina3, Michael R. Watts2, Vladimir Stojanovic1 University of California, Berkeley, CA Mass
ISSCC 2019
Session 29
Quantum & Photonics
Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping
Atsushi Shirane1, Mitsuru Suzuki2, Kazuhiro Harasaka2, Kazuhiko Adachi2, Shinya Yanagimachi3, Kenichi Okada1 Tokyo Institute of Technology, Tokyo, Japan Ricoh, Miyagi, Japan 3 National Institute of Advanced Industrial Sc
ISSCC 2019
Session 29
Quantum & Photonics
A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic
Kyushu University, Fukuoka, Japan 1 2 A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8-bit signe
ISSCC 2019
Session 29
Quantum & Photonics
A Scalable Quantum Magnetometer in 65nm CMOS with Vector-Field Detection Capability
Room-temperature control and detection of the nitrogen vacancy (NV) center in diamond’s spin-state has enabled magnetic sensing with high sensitivity and spatial resolution [1], [2]. However, current NV sensing apparatus
ISSCC 2019
Session 29
Quantum & Photonics
A 28nm Bulk-CMOS 4-to-8GHz <2mW Cryogenic Pulse Modulator for Scalable Quantum Computing
Ofer Naaman2, Rami Barends2, Ted White2, Marissa Giustina2, Daniel Sank2, Pedram Roushan2, Kunal Arya2, Benjamin Chiaro3, Julian Kelly2, Jimmy Chen2, Brian Burkett2, Yu Chen2, Andrew Dunsworth3, Austin Fowler2, Brooks Fo
ISSCC 2019
Session 28
Wireless
A 21dBm-OP1dB 20.3%-Efficiency -131.8dBm/Hz-Noise X-Band Cartesian-Error-Feedback Transmitter with Fully Integrated Power Amplifier in 65nm CMOS
Zhejiang University, Hangzhou, China 1 2 The increase of carrier frequency enables the utilization of the abundant highfrequency resource to meet the ceaseless demand for high data-rates. With respect to the transmitter,
ISSCC 2019
Session 28
Wireless
A Wideband Blocker-Tolerant Receiver with High-Q RF-Input Selectivity and <-80dBm LO Leakage voltage swing at the drain of BPCG. The noise and IM3 generated in the BPCG circuit are ultimately cancelled at BB output upon optimum gain and phase matching between CG and NC downconversion paths.
capacitances along the BPCG loop cause slight shift of BP center frequency seen at RF_in. By feeding amplified BB signals within the notch filter to adjacent branches (e.g., A to B in Fig. 28.7.2), phase lead is introduced
ISSCC 2019
Session 28
Wireless
Full-Duplex 2×2 MIMO Circulator-Receiver with High TX Power Handling Exploiting MIMO RF and Shared-Delay Baseband Self-Interference Cancellation
recent years due to multiple benefits such as increased spectral efficiency and improved network latency [1-5]. Several challenges remain in the quest for high-performance integrated FD radios. Transmitter (TX) power handl
ISSCC 2019
Session 28
Wireless
Non-Magnetic 60GHz SOI CMOS Circulator Based on Loss/Dispersion-Engineered Switched Bandpass Filters
There has been significant recent research on non-magnetic non-reciprocal components at RF and mm-waves, such as circulators and isolators, based on spatio-temporal modulation [1-3]. Circulators enable simultaneous transm
ISSCC 2019
Session 28
Wireless
A High-Q Resonant Inductive Link Transmit Modulator/Driver for Enhanced Power and FSK/PSK Data Transfer Using Adaptive-Predictive Phase-Continuous Switching Fractional-Capacitance Tuning
As well as transferring power, inductively coupled systems such as RFID and wireless charging commonly require a downlink channel to transfer data to the receiving function, for simplicity usually using the same carrier