ISSCC 2020
Session 13
Memory
A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique pairs for low input offset to reduce a random dopant fluctuation. In order to reduce an input offset, the error amplifier designs that DC gain is above 74dB with all PVT variations. The Monte-Carlo simulation shows the variation is decreased by 46.9%, comparing to conventional one.
Sunghwa Ok, Jongwoo Kim, Kayoung Cho, Hyunchul Lee, Geonu Kim, Kangwoo Park, Kwanho Kim, Heejoo Lee, Sooyeol Chai, Chankeun Kwon, Hanna Cho, Chanhui Jeong, Yujin Yang, Jayoon Goo, Jangwon Park, Juhyeong Lee, Heonki Kim,
ISSCC 2020
Session 12
Wireline I/O
A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver
DACs with an analog bandwidth (BW) of at least 50GHz to support advanced modulation schemes. CMOS-based DACs are preferred because they support monolithic integration of the DSP and DAC, but the achievable sampling rate
ISSCC 2020
Session 12
Wireline I/O
A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters
attention for constructing large-capacity optical core/metro networks and even data center interconnects. Data rates in the next generation of coherent optical transmission systems are expected to exceed 400Gb/s, for whi
ISSCC 2020
Session 12
Wireline I/O
A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications
Angelo Palladino1, Antonio Santipo1, Lorenzo Gerosa1, Matteo Repossi1, Gianluca Catrini2, Marta Campo2, Francesco Radice1, Andrea Diodato1, Roberto Pelleriti2, Daniele Baldi1, Laura Tarantini1, Luca Maggi1, Gianluca Rada
ISSCC 2020
Session 12
Wireline I/O
A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control
stringent demands on the bandwidth and energy efficiency of data center interconnects, spurring the development of several 400G Ethernet standards [1]. Siliconphotonics-based solutions are of particular interest for low
ISSCC 2020
Session 11
Power Management
A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries
Taehwang Kong2, Sang-Ho Kim2, Sungyong Lee2, Michael Choi2, Jongshin Shin2, Gyu-Hyeong Cho1, Hyun-Sik Kim1 KAIST, Daejeon, Korea Samsung Electronics, Hwaseong, Korea 1 2 As internet-of-things (IoT) devices continue to be
ISSCC 2020
Session 11
Power Management
A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8% Power Efficiency and 0.87µs/V DVS Rate
Dongsu Kim, Jaeyeol Han, Jun-Suk Bang, Yumi Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho Samsung Electronics, Hwaseong, Korea In recent years, buck-boost converters have been widely utilized for batte
ISSCC 2020
Session 11
Power Management
A 1.46mm2 Simultaneous Energy-Transferring SingleInductor Bipolar-Output Converter with a Flying Capacitor for Highly Efficient AMOLED Display in 0.5µm CMOS Sung-Wan Hong
being more widely used in various electronic devices. As the display is one of the modules that consumes the largest portion of the power in electronic devices, displays must be designed to operate with a higher efficien
ISSCC 2020
Session 11
Power Management
A 2-Phase Soft-Charging Hybrid Boost Converter with Doubled-Switching Pulse Width and Shared Bootstrap Capacitor Achieving 93.5% Efficiency at a Conversion Ratio of 4.5 and vice versa in state-2 (at t3). As VDR34 is reused to charge C5 and C6, an additional drop on VDR34 will occur at t1 and t3. However, thanks to the proposed topology, M5 and M6 are relatively small since they have low voltage stress and small high-side (HS) currents (to be explained next). This reduces both the sizes of C5 and C6, and the VDR34 drop.
Figure 11.5.4 normalizes the power losses of the proposed HB to those of a 2PCB, with CR=4.5. We choose both the same inductor DCR and switch on-resistance (RON) for the two topologies. However, all the switches in 2P-CB
ISSCC 2020
Session 11
Power Management
A 48-to-80V Input 2MHz Adaptive ZVT-Assisted GaNBased Bus Converter Achieving 14% Light-Load Efficiency Improvement
In modern hybrid electric vehicles, wide-input-range intermediate bus converters (IBCs) are essential in 48V power systems [1]. To increase the power efficiency, e-mode GaN FETs have been adopted in the IBCs [2, 3], as t
ISSCC 2020
Session 11
Power Management
A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency
disabled after a fixed delay. It discharges the HSSet and HSReset nodes to prepare the level shifter for the next signal transmission. Due to measured slew rates as high as 20V/ns, a common-mode blanking circuit is used
ISSCC 2020
Session 11
Power Management
A Fully Integrated Resonant Switched-Capacitor Converter with 85.5% Efficiency at 0.47W Using On-Chip Dual-Phase Merged-LC Resonator
Fully integrated power management is important for a variety of applications spanning performance and mobile computing, embedded systems, and communications. However, monolithic integration has been elusive due to the li
ISSCC 2020
Session 11
Power Management
A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation
Texas Instruments, Santa Clara, CA 1 2 In industrial and automotive applications, 12V/24V power systems are widely used. In such systems, high step-down DC-DC converter is highly desirable to deliver a wide range of curr
ISSCC 2020
Session 10
RF & Wireless
A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS
Next-generation phased-array systems with large modulated bandwidths (BW) and high energy efficiency will enable Gb/s wireless communications. The spatial signal processing at this large scale using state-of-the-art phas
ISSCC 2020
Session 10
RF & Wireless
A 0.26mm2 DPD-Less Quadrature Digital Transmitter With <-40dB EVM Over >30dB Pout Range in 65nm CMOS
based on RF digitalto-analog converters (DAC) are optimal for wireless transmitters in CMOS due to the small chip area, low power consumption, and ability to evolve with scaling of the transistor feature size. A DTX inte
ISSCC 2020
Session 10
RF & Wireless
A 4G/5G Cellular Transmitter in 12nm FinFET with Harmonic Rejection
Radio (NR) technology provides much higher data rate and system capacity compared to 4G LTE. This is achieved, among other techniques, by increasing the maximum channel bandwidth per component carrier (CC) from 20MHz in
ISSCC 2020
Session 10
RF & Wireless
A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications
Bassam Khamaisi1, Elan Banin2, Eli Borokhovich2, Nahum Kimiagarov2, Phillip Skliar2, Rotem Banin1, Sarit Zur2, Sebastian Reinhold4, Smadar Bruker2, Tzvi Maimon1, Uri Parker2, Ofir Degani1 Intel, Haifa, Israel, 2Intel, Pe
ISSCC 2020
Session 10
RF & Wireless
A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax
EVM Floor in 55nm CMOS Eric Lu1, Wen-Kai Li2, Zhiming Deng1, Edris Rostami1, Pi-An Wu2, Keng-Meng Chang2, Yu-Chen Chuang2, Chang-Ming Lai2, Yang-Chuan Chen1, Tzu-Hsuin Peng2, Tzung-Chuen Tsai2, Hui-Hsien Liu2, Chien-Chih
ISSCC 2020
Session 10
RF & Wireless
A 12nm CMOS RF Transceiver Supporting 4G/5G UL MIMO
Mohammed Hassan2, Chi-Tsan Chen1, Chao-Wei Wang1, Yen-Chuan Huang1, Li-Han Hung1, Wei-Hao Chiu1, Anson Lin1, Bo-Yu Lin1, Arnaud Werquin2, Chien-Cheng Lin1, Yen-Horng Chen1, Jen-Che Tsai1, Yuan-Yu Fu1, Bernard Tenbroek2,
ISSCC 2020
Session 10
RF & Wireless
A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation
A key aspect of 5G systems is supporting multiband and multistandard applications. Depending on operating conditions, this requires high in-band dynamic range and/or low noise floor at specific out-of-band (OOB) frequenc
ISSCC 2020
Session 10
RF & Wireless
A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR
Achieving <-157.5dBc/Hz OB Noise Gengzhen Qi1, Haijun Shao1, Pui-In Mak1, Jun Yin1, Rui P. Martins1,2 University of Macau, Macau, China, 2University of Lisboa, Lisbon, Portugal 1 For the sub-6GHz 5G New Radio (5G-NR), mo
ISSCC 2020
Session 1
Plenary
The Future of Computing: Bits + Neurons + Qubits
Abstract The laptops, cell phones, and Internet applications commonplace in our daily lives are all rooted in the idea of zeros and ones – in bits. This foundational element originated from the combination of mathematics
ISSCC 2020
Session 1
Plenary
Future Scaling: Where Systems and Technology Meet Nadine Collaert
In a smart society where everything will be connected, an avalanche of data is coming toward us, with numbers going to several hundreds of zettabytes per year by 2025! This data will need to be distributed, stored, compu
ISSCC 2020
Session 1
Plenary
Fertilizing AIoT from Roots to Leaves Kou-Hung Lawrence Loh Senior Vice President & Corporate Strategy Officer
IoT with artificial intelligence, AIoT, enriches everything around the world. The application space is unlimited, ranging from fundamental research, enterprise, industry, transportation, services, and personal daily life
ISSCC 2020
Session 1
AI / ML
The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design Jeffrey Dean
The past decade has seen a remarkable series of advances in machine learning, and in particular deeplearning approaches based on artificial neural networks, to improve our abilities to build more accurate systems across
ISSCC 2019
Session 9
mm-Wave
A 28GHz 20.3%-Transmitter-Efficiency 1.5°-Phase-Error Beamforming Front-End IC with Embedded Switches and Dual-Vector Variable-Gain Phase Shifters
Hanbat National University, Daejeon, Korea *Equally-Credited Authors (ECAs) 1 respectively. The NF of RX at 28GHz is 4.58dB, which is increased only by 1dB compared to simulated NF of LNA without switch and PA. NF variat
ISSCC 2019
Session 9
mm-Wave
A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology
Somnath Kundu1, Abhishek Agrawal1, Peter Sagazio1, Brent Carlton1, Farhana Sheikh1, Arnaud Amadjikpe1, William Lambert3, Divya Shree Vemparala1, Mark Chakravorti1, Satoshi Suzuki1, Robert Flory1, Chris Hull1 Intel, Hills
ISSCC 2019
Session 9
mm-Wave
A 42.2Gb/s 4.3pJ/b 60GHz Digital Transmitter with 12b/Symbol Polarization MIMO
in modern-day handheld computing devices around the unlicensed 57-to-71GHz band, the IEEE 802.11ay standard [1] supports 2-to-4× bonding of 2.16GHz channels (i.e. 4.32 to 8.64GHz), constellations up to 64QAM, and spatial
ISSCC 2019
Session 9
mm-Wave
An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver
Technology, Koganei, Japan 3 Panasonic, Yokohama, Japan 1 2 IEEE Standard 802.15.3d, published in October 2017, defines a high-data-rate wireless physical layer that enables up to 100Gb/s using the lower THz frequency ran
ISSCC 2019
Session 9
mm-Wave
A 145GHz FMCW-Radar Transceiver in 28nm CMOS
require a high range resolution. This paper presents a 145GHz FMCW radar transceiver with on-chip antennas in 28nm bulk CMOS. An RF bandwidth of 13GHz yields an 11mm range resolution, and the high RF carrier permits grea
ISSCC 2019
Session 9
mm-Wave
A 680µW Burst-Chirp UWB Radar Transceiver for Vital Signs and Occupancy Sensing up to 15m Distance
Johan Dijkhuis1, Wilfried Zomagboguelou1,3, Arjan Breeschoten1, Stefano Traferro1, Yan Zhan1, Tom Torf4, Christian Bachmann1, Pieter Harpe3, Masoud Babaie2 imec - Netherlands, Eindhoven, The Netherlands Delft University
ISSCC 2019
Session 9
mm-Wave
A 192-Virtual-Receiver 77/79GHz GMSK Code-Domain MIMO Radar System-on-Chip
Lysander Lim, Ryan Lobo, Dave Welland, Chung-Kai Chow, Andrew Dornbusch, Tim Dupuis, Struan Vaz, Fred Rush, Paul Bassett, Hong Kim, Monier Maher, Otto Schmid, Curtis Davis, Manju Hegde Uhnder, Austin, TX MIMO radars tran
ISSCC 2019
Session 9
mm-Wave
Toward Automotive Surround-View Radars
Weishow Hsu1, Jing-Hong Conan Zhan1, Brian Juan1, Chi-Hang Lok1, Sam Lee1, PC Hsiao1, Qiang Zhou2, Mark Wei1, Hsiang-Yun Chu1, Yu-Lun Chen1, Chao-Ching Hung1, Kevin Fong1, Po-Chun Huang1, Pierce Chen1, Sheng-Yuan Su1, Ya
ISSCC 2019
Session 8
Power Management
A 2MHz 4-to-60VIN Buck-Boost Converter for Automotive Use Achieving 95% Efficiency and CISPR 25 Class 5 Standard
High-voltage highly efficient switching power converters have gained high popularity in automotive applications. Powered by the car battery (VIN), the converters need to experience a wide VIN range from 4V to 60V under ha
ISSCC 2019
Session 8
Power Management
A Fully Integrated 85%-Peak-Efficiency Hybrid MultiRatio Resonant DC-DC Converter with 3.0-to-4.5V Input and 500µA-to-120mA Load Range by a fast capacitive level shifter, which results in very energy efficient highfrequency signal shifting. In contrast, pulsed cascode level shifters are used for
static losses compared to the fast dynamic level shifters. Peter Renz1, Maik Kaufmann1, Michael Lueders2, Bernhard Wicht1 Leibniz University Hannover, Hannover, Germany 2 Texas Instruments, Freising, Germany 1 DC-DC conv
ISSCC 2019
Session 8
Power Management
A Fully Integrated Voltage Regulator in 14nm CMOS with
Christopher Schaef1, Nachiket Desai1, Harish Krishnamurthy1, Sheldon Weng1, Huong Do2, William Lambert2, Kaladhar Radhakrishnan2, Krishnan Ravichandran1, James Tschanz1, Vivek De1 Intel, Hillsboro, OR Intel, Chandler, AZ
ISSCC 2019
Session 8
Power Management
Fully Integrated Buck Converter with 78% Efficiency at 365mW Output Power Enabled by Switched-InductorCapacitor Topology and Inductor Current Reduction Technique
power consumption of system-on-chip by providing point-of-load regulation with dynamic voltage scaling [1]. As a core component of a buck converter, an inductor with large inductance and small resistance is desirable for
ISSCC 2019
Session 8
Power Management
A 10.9W 93.4%-Efficient (27W 97%-Efficient) FlyingInductor Hybrid DC-DC Converter Suitable for 1-Cell (2-Cell) Battery Charging Applications
The annual increase in performance and feature density of mobile products has driven the need for batteries with higher capacity and thus higher power-delivery solutions to maintain sensible charging times. The USB-C pow
ISSCC 2019
Session 8
Power Management
A Continuous-Input-Current Passive-Stacked Third-Order Buck Converter Achieving 0.7W/mm2 Power Density and 94% Peak Efficiency
The power density and efficiency of power-management integrated circuits (PMICs) is playing an increasingly important role in the miniaturization of modern computing platforms. Small inductors can be used to help miniatur
ISSCC 2019
Session 7
AI / ML
LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16
for energy-efficient deep learning (DL) acceleration [1-6]. Most prior DNN inference accelerators are trained in the cloud using public datasets; parameters are then downloaded to implement AI [1-5]. However, local DNN le
ISSCC 2019
Session 7
AI / ML
A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback
classifying handwritten digits, the learning rule can be directly adopted in general fully-connected networks with different network structures and hence can be extended to other applications. For example, the algorithm
ISSCC 2019
Session 7
AI / ML
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified NeuralNetwork Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1× Higher TOPS/mm2 and 6T HBST-TRAM-Based 2D Data-Reuse Architecture
Yung-Ning Tu2, Yi-Ju Chen2, Ao Ren3, Yanzhi Wang3, Meng-Fan Chang2, Xueqing Li1, Huazhong Yang1, Yongpan Liu1 Tsinghua University, Beijing, China National Tsing Hua University, Hsinchu, Taiwan 3 Northeastern University,
ISSCC 2019
Session 7
AI / ML
A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression
but also for action control, so that an autonomous system, such as the robot, can perform human-like behaviors and operations. Unlike recognition tasks, real-time operation is important in action control, and it is too s
ISSCC 2019
Session 7
AI / ML
An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration
University of Michigan, Ann Arbor, MI Simultaneous localization and mapping (SLAM) estimates an agent’s trajectory for all six degrees of freedom (6 DoF) and constructs a 3D map of an unknown surrounding. It is a fundame
ISSCC 2019
Session 7
AI / ML
A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications
Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa Toshiba Elect
ISSCC 2019
Session 7
AI / ML
An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC
widely applied for image and speech recognition. Response time, connectivity, privacy and security drive applications towards mobile platforms rather than cloud. For mobile systems-on-a-chip (SoCs), energyefficient neural
ISSCC 2019
Session 6
Wireline I/O
A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS
circuits (CDR) are ubiquitous in recent receiver designs as a means of lowering power consumption by sampling the data only once per UI. To further reduce power, prior works in pattern-based baud-rate PD
ISSCC 2019
Session 6
Wireline I/O
A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS
transmitters to operate at higher speeds. The applications of 400GbE also push the transmitter to be designed at 112Gb/s for a single lane [1-2]. However, the use of advanced processes (<16nm) hardly reduces the costs. T
ISSCC 2019
Session 6
Wireline I/O
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS
Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli IBM T. J. Watson Research Center, Yorktown Heights, NY The ever-increasing demand for higher bandwidth continues to fuel the need for faster and
ISSCC 2019
Session 6
Wireline I/O
A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET
F. Rad3, J. Riani3, J. Pernillo3, J. Sun1, J. Wong3, K. Abdelhalim2, K. Gopalakrishnan3, K. Kim2, L. Tse3, M. Davoodi2, M. Le2, M. Zhang3, M. Talegaonkar2, P. Prabha2, R. Mohanavelu3, S. Chong1, S. Forey4, S. Netto3, S.