ISSCC 2020
Session 22
Memory
A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme
So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sanguhn Cha, Donghak Shin, Jungyu Lee, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yongsik Park, Kijun Lee, Myung-Kyu Lee, Seungduk B
ISSCC 2020
Session 21
Digital Processors
A 5.69mm2 0.98nJ/Pixel Image-Processing SoC with 24b High-Dynamic-Range and Multiple Sensor Format Support for Automotive Applications
Chang-Hung Tsai, Ying-Jui Chen, TH Wu, Hue-Min Lin, Han-Liang Chou, Abrams Chen, Andy-HB Wang, WC Gu, Wayne Hsieh, Jing-Ying Chang, Shou-Chun Liao, CT Ho, Larry Chu, Sokonisa Wei, CH Wang, Kevin Jou MediaTek, Hsinchu, Ta
ISSCC 2020
Session 21
Digital Processors
A 1.5µJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots
Autonomous micro robots have been deployed for various applications, ranging from unmanned package delivery to smart aerial surveillance. These robots possess intelligence for perception, make decisions based on the coll
ISSCC 2020
Session 21
Digital Processors
A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing
Chao-Yang Yu3, Nian-Shyang Chang3, Ling-Chien Chen3, Jia-Rong Chang3, Chun-Pin Lin3, Hung-Lieh Chen3, Chi-Shi Chen3, Jui-Hung Hung2, Chia-Hsiang Yang1 National Taiwan University, Taipei, Taiwan National Chiao Tung Univer
ISSCC 2020
Session 20
Power Management
3D Surgical Alignment with 100µm Resolution Using Magnetic-Field Gradient-Based Localization
Arian Hashemi Talkhooncheh, Minwo Wang, Mikhail G. Shapiro, Azita Emami California Institute of Technology, Pasadena, CA Substantial advances in the field of surgery have taken place in recent years, which aim at decreas
ISSCC 2020
Session 20
Power Management
A 4.0×3.7×1.0mm3-MEMS CMOS Integrated E-Nose with
Si Hoon Lee1, Kwangmin Park1, Jaeheung Lim1, Minchul Lee1, Jeongho Park1, Hyun Kim1, Young Ok Lee2, Hyun Su Ahn2, Eunseok Shin1, Hyungjong Ko1, Seoungjae Yoo1, Hyunsurk Ryu1, Yongin Park1, Joonseok Kim1, Long Yan1 Samsun
ISSCC 2020
Session 20
Power Management
A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC
China 1 2 IoT devices usually operate in random-sparse-event scenarios (Fig. 20.2.1). To avoid missing events, traditionally a periodic-wake-up frequency [1] must be orders of magnitude higher than the average event rate
ISSCC 2020
Session 20
Power Management
A 28µW IoT Tag That Can Communicate with Commodity WiFi Transceivers via a Single-Side-Band QPSK Backscatter Communication Technique
San Diego, CA 1 2 Nearly all IoT devices require wireless connectivity, and to keep costs down and deployment opportunities up, communication should ideally occur with widely deployed commodity hardware such as WiFi. How
ISSCC 2020
Session 2
Digital Processors
IBM z15: A 12-Core 5.2GHz Microprocessor
John Isakson3, Ofer Geva1, Brian Deskin4, Mark Cichanowski3, Dina Hamid1, Chris Cavitt1, Gregory Fredeman1, Anthony Saporito1, Ashutosh Mishra5, Alper Buyuktosunoglu6, Tobias Webel7, Preetham Lobo5, Pradeep Parashurama5,
ISSCC 2020
Session 2
Digital Processors
A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded
VLIW DSP, Embedded Vision and Imaging Acceleration Rama Venkatasubramanian1, Don Steiss1, Greg Shurtz2, Tim Anderson1, Kai Chirca1, Raghavendra Santhanagopal1, Niraj Nandan1, Anish Reghunath1, Hetul Sanghvi1, Daniel Wu1,
ISSCC 2020
Session 2
Digital Processors
A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.
Gordon Gammie1, Hsinchen Chen1, Lee-Kee Yong1, Manzur Rahman1, Jenny Wiedemeier1, Ramu Madhavaram1, Alex Chiou2, Blundt Li2, Vincent Lin2, Rory Huang2, Michael Yang2, Achuta Thippana1, Osric Su2, SA Huang2 MediaTek, Aust
ISSCC 2020
Session 2
Digital Processors
A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU
Jae Geun Song, Jinook Song, Hyeokman Kwon, Jaeyoung Lee, Jaesu Jung, Myungjin Kang, Jaehun Jeong, Yoonjoo Kwon, Nak Hee Seong Samsung Electronics, Hwaseong, Korea Mobile application processors (APs) must be extremely pow
ISSCC 2020
Session 2
Digital Processors
A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm
which is finally delivered to the chiplet through a micro-bump face-to-face power grid (Fig. 2.3.7). The SCVR input voltage (up to 2.5V) reduces total input current and the required number of power IOs in the package. Ea
ISSCC 2020
Session 2
Digital Processors
AMD Chiplet Architecture for High-Performance Server and Desktop Products
AMD, Austin, TX 1 2 AMD’s “Rome” and “Matisse” are second-generation AMD Infinity Fabric-based SoCs using 3 unique hybrid process technology chiplets to achieve leading performance, performance/$ and performance/W, targe
ISSCC 2020
Session 2
Digital Processors
Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core
design, fabricated in an energy-efficient TSMC 7nm FinFET process. Similar to AMD’s prior-generation core, codenamed “Zen” [1], the Core Complex Unit (CCX) with 4 cores in this version (Fig. 2.1.1) is used across a wide
ISSCC 2020
Session 19
Quantum & Photonics
A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications
generation is required for the control electronics of quantum computers. To avoid limiting the performance of quantum bits, the frequency noise of a PLL should be <1.9kHzrms [1]. However, it is challenging for RF oscilla
ISSCC 2020
Session 19
Quantum & Photonics
A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot
Marcos Zurita1, Yvain Thonnart1, Maud Vinet1, Marc Sanquer2, Romain Maurand2, Aloysius G. M. Jansen2, Gaël Pillonnet1 CEA-LETI-MINATEC, Grenoble, France CEA-IRIG, Grenoble, France 1 2 To reach quantum supremacy, quantum
ISSCC 2020
Session 19
Quantum & Photonics
A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers
Andrea Corna1, Xiao Xue1, Charles Jeon2, Farhana Sheikh2, Esdras Juarez-Hernandez3, Brando Perez Esparza3, Huzaifa Rampurawala2, Brent Carlton2, Nodar Samkharadze4, Surej Ravikumar2, Carlos Nieva2, Sungwon Kim2, Hyung-Ji
ISSCC 2020
Session 18
AI / ML
A Fully-Generic-Process Galvanic Isolator for Gate Driver with 123mW 23% Power Transfer and Full-Triplex 21/14/0.5Mb/s Bidirectional Communication Utilizing Reference-Free Dual-Modulation FSK DATA2 is transferred in the same manner as DATA1 through another transformer. Almost all the circuits excluding the DATA1 driver and I/O buffer operate at 1.5V supply to support sufficiently high operating speed. The driver operates with 5.5V supply to transfer power by the same transformer, and the rectifier placed in parallel with the DATA1 receiver extracts the received power.
Thanks to the VCO synchronization, demodulation can be realized by a delaybased digital frequency counting normalized by the oscillation period (tVCO). But there is a challenge in that the received signal edge is not per
ISSCC 2020
Session 18
Power Management
A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics
Increased switching frequency of power devices for power electronics allows for compact and lightweight circuit implementations for variety of applications, including power factor corrections, DC/DC converters, and motor
ISSCC 2020
Session 18
Power Management
A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor
Samsung Electronics, Hwaseong, Korea 1 2 Demand for DC-DC voltage conversion from a 48V input has been on the rise due to proliferation of server and automotive applications with a 48V intermediate bus and 48V batteries,
ISSCC 2020
Session 18
Power Management
ZVS Flyback-Converter ICs Optimizing USB Power Delivery for Fast-Charging Mobile Devices to Achieve 93.5% Efficiency
standard as a charging solution for mobile devices [1]. Moreover, the extended specification includes programmable power supply (PPS) which is suitable for fast charging mobile devices by allowing the power source to dyn
ISSCC 2020
Session 18
Power Management
An 11MHz Fully Integrated 5kV Isolated DC-DC Converter Without Cross-Isolation-Barrier Feedback
University of Electronic Science and Technology of China, Chengdu, China 1 2 Galvanic isolation greatly enhances system safety and reliability in applications such as medical devices and sensor interfaces. In these appli
ISSCC 2020
Session 18
Power Management
A 120mA Non-Isolated Capacitor-Drop AC/DC Power Supply
meters, appliances, smoke alarms to ground fault detectors require a non-isolated DC supply that is powered directly from the AC mains. These applications typically require the ability to handle up to 305VAC,rms at the i
ISSCC 2020
Session 18
Power Management
A Monolithic E-Mode GaN 15W 400V Offline Self-Supplied Hysteretic Buck Converter with 95.6% Efficiency
Texas Instruments, Freising, Germany, 3 Texas Instruments, Dallas, TX 1 2 Due to superior figures-of-merit (FoMs), gallium nitride (GaN) high-electron mobility transistors (HEMTs) offer a huge potential for high-voltage
ISSCC 2020
Session 18
Power Management
A Self-Health-Learning GaN Power Converter Using OnDie Logarithm-Based Analog SGD Supervised Learning and Online TJ-Independent Precursor Measurement
As GaN technology proliferates in modern power electronics, reliability of GaNbased circuits has become the biggest hurdle for commercialization. Sustaining largest voltage and current stresses in power circuits, power d
ISSCC 2020
Session 17
Clocking & PLLs
A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz
Chao Fan , Jun Yin , Chee-Cheow Lim , Pui-In Mak , Rui P. Martins 1 1 1 1 1,2 University of Macau, Macau, China University of Lisboa, Lisbon, Portugal 1 2 Low-power mm-wave sensors using an FMCW radar technology are open
ISSCC 2020
Session 17
Clocking & PLLs
A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth
continuous-wave (FMCW) radars are a viable solution for high-resolution indoor localization and tracking applications. The fast saw-tooth FMCW chirp needs to be synthesized with a short ramp time, large chirp bandwidth (
ISSCC 2020
Session 17
Clocking & PLLs
A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM
Ireland 1 2 Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1,2] due to their ability to achieve ultra-low jitter (<100fs). How
ISSCC 2020
Session 17
Clocking & PLLs
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
oscillators for 5G wireless transceivers require rms integrated jitter below 100fs to enable spectrally efficient modulation schemes, such as high-order quadrature amplitude modulation (QAM), at millimeter-wave carrier f
ISSCC 2020
Session 17
Clocking & PLLs
A 18.6-to-40.1GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting
The development of millimeter-wave (mmW) multiple-band systems for the 5G wireless and point-to-point backhaul communication requires ultra-wideband signal sources with low phase noise. However, with increasing parasitic
ISSCC 2020
Session 17
Clocking & PLLs
A 66fsrms Jitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking
substantial increase in mobile data-rates, enabled by the 5G standard, calls for significantly lower integrated jitter of the local oscillator with respect to previous generations, with requirements below 90fs rms for mi
ISSCC 2020
Session 16
Data Converters
A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS
A low-power, wide-bandwidth, and high-dynamic-range (DR) ADC is one of the critical building blocks in a wireless receiver design, in which a continuous-time delta-sigma modulator (CT DSM) has become a popular choice. Ho
ISSCC 2020
Session 16
Data Converters
An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter
Donald Paterson4, Asha Ganesan1, Yunzhi Dong4, Wenhua Yang4, Yue"Yin1, Zhao Li1, Prawal Shrestha4, Athreya Gopal5, Aathreya Bhat4, Shanthi Pavan6 Analog Devices, Toronto, Canada, 2Analog Devices, San Diego, CA Analog Dev
ISSCC 2020
Session 16
Data Converters
A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation
University of Texas, Austin, TX 1 2 As with any ADC with a front-end S/H, the SAR ADC suffers from a fundamental SNR challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor has to be suffi
ISSCC 2020
Session 16
Data Converters
A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme
With the increasing demand for next-generation communication, the trend of developing wide-bandwidth, high-resolution ADCs has emerged, where pipelined SAR (PIPE-SAR) ADCs [1-2] have become popular owing to their excelle
ISSCC 2020
Session 16
Data Converters
A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation
Chi-Hang Chan1, Jan Craninckx2, Rui P. Martins1,3 University of Macau, Macau, China imec, Leuven, Belgium 3 University of Lisboa, Lisbon, Portugal 1 2 Multi-GS/s ADCs are key blocks for ADC-based serial links and mm-wave
ISSCC 2020
Session 16
Data Converters
A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input
University of Lisboa, Lisbon, Portugal 1 2 The ever-increasing data traffic in wireline communication systems has led to the demand for high-speed ADCs with a large input BW. Time-interleaved SAR ADCs with a large interl
ISSCC 2020
Session 16
Data Converters
A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration
consumption enable direct RF sampling, more integration, flexibility and lower cost for communication, instrumentation and other applications. The state of the art of interleaved RF converters enables up to 10GS/s with 1
ISSCC 2020
Session 15
AI / ML
A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips multiplication results (PL"="IN[1:0]"⋅ W) to HGBLB.
Jing-Hong Wang1, Ta-Wei Liu1, Ssu-Yen Wu1, Ruhui Liu1, Yen-Chi Chou1, Zhixiao Zhang1, Syuan-Hao Sie1, Wei-Chen Wei1, Yun-Chen Lo1, Tai-Hsing Wen1, Tzu-Hsiang Hsu1, Yen-Kai Chen1, William Shih1, Chung-Chuan Lo1, Ren-Shuo
ISSCC 2020
Session 15
AI / ML
A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices
Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang,
ISSCC 2020
Session 15
AI / ML
A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications
computations and reduces off-chip weight access to reduce energy consumption and latency, specifically for AI edge devices. Prior CIM approaches demonstrated tradeoffs for area, noise margin, process variation and weight
ISSCC 2020
Session 15
AI / ML
A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips
Wei-Hsing Huang1, Yung-Ning Tu1, Ruhui Liu1, Pei-Jung Lu1, Ta-Wei Liu1, Jing-Hong Wang1, Zhixiao Zhang1, Hongwu Jiang3, Shanshi Huang3, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Shyh-Shyuan Sheu
ISSCC 2020
Session 15
AI / ML
A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and ChargeSharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications
Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li TSMC, Hsinchu, Taiwan Despite recent advances, low-voltage operation remains one of the key approaches for
ISSCC 2020
Session 14
AI / ML
A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse
University, Hsinchu, Taiwan 1 2 Computing-in-Memory (CIM) is a promising solution for energy-efficient neural network (NN) processors. Previous CIM chips [1-4] mainly focus on the memory macro itself, lacking insight on
ISSCC 2020
Session 14
AI / ML
A 65nm 24.7µJ/Frame 12.3mW Activation-SimilarityAware Convolutional Neural Network Video Processor
Zhe Yuan1,2, Yixiong Yang1, Jinshan Yue1,2, Ruoyang Liu1, Xiaoyu Feng1, Zhiting Lin3, Xiulong Wu3, Xueqing Li1, Huazhong Yang1, Yongpan Liu1 Tsinghua University, Beijing, China Pi2star Technology, Beijing, China 3 Anhui
ISSCC 2020
Session 14
AI / ML
A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS
is a strong requirement for always-on speech interfaces in wearable and mobile devices, such as Voice Activity Detection (VAD) and Keyword Spotting (KWS) [1-5]. A KWS system is used to detect specific wake-up words by sp
ISSCC 2020
Session 13
Memory
A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs
Sanad Bushnaq1, Takuyo Kodama1, Yuki Ishizaki1, Yoko Deguchi1, Akio Sugahara1, Akihiro Imamoto1, Norichika Asaoka1, Ryosuke Isomura1, Takaya Handa1, Junichi Sato2, Hiromitsu Komai1, Atsushi Okuyama1, Naoaki Kanagawa1, Ya
ISSCC 2020
Session 13
Memory
A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices
Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Meng-Fan Chang National Tsing Hua University, Hsinchu, Taiwan Many security-aware mobile devices, using the secure hash
ISSCC 2020
Session 13
Memory
A 22nm 32Mb Embedded STT-MRAM with 10ns Read
Interference Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Chieh-Pu Lo, Meng-Chun Shih, Kuei-Hung Shen, Harry Chuang, Tsung-Yung Jonathan Chang TSMC, Hsinchu, Taiwan STT-MRA