ISSCC 2020
Session 29
RF & Wireless
Sub-THz CMOS Molecular Clock with 43ppt Long-Term Stability Using High-Order Rotational Transition Probing and Slot-Array Couplers
Future ultra-broadband and low-latency radio access networks pose stringent specifications for time synchronizations. For 5G base stations, inter-site timing error should be <130ns for carrier aggregation and <10ns for h
ISSCC 2020
Session 29
RF & Wireless
High-Performance Isolators and Notch Filters Based on N-Path Negative Transresistance
circuits are used for a variety of functions, including the realization of oscillators and loss compensation. Active negative-resistance circuits, such as cross-coupled gm cells, can provide power gain but, when used for
ISSCC 2020
Session 29
RF & Wireless
Non-Magnetic 0.18µm SOI Circulator with Multi-Watt Power Handling Based on Switched-Capacitor Clock Boosting
There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically-time-varying (LPTV) circuits [1-5]. Nevertheless, integrated circulators still require
ISSCC 2020
Session 29
RF & Wireless
A 0.59THz Beam-Steerable Coherent Radiator Array with 1mW Radiated Power and 24.1dBm EIRP in 40nm CMOS
In THz imaging systems, signal sources are needed to provide illumination of objects. In several reported imaging systems working at 0.3THz, 0.62THz, and 0.81THz, an output power around 1mW is required to achieve an acce
ISSCC 2020
Session 29
RF & Wireless
A 0.42THz 9.2dBm 64-Pixel Source-Array SoC with Spatial Modulation Diversity for Computational Terahertz Imaging
Computational THz Imaging (CTI) is the process of indirectly forming images using algorithms that rely on a significant amount of computing. Unlike focalplane arrays (FPAs), a single-pixel camera (SPC) uses spatially pat
ISSCC 2020
Session 28
Medical & Bio
A CMOS Multimodality In-Pixel Electrochemical and Impedance Cellular Sensing Array for Massively Paralleled Synthetic Exoelectrogen Characterization current/charge-transfer with CV and CA tests. The generated current from cell samples is integrated on the feedback capacitor (50 to 150fF) of the in-pixel capacitive-TIA (CTIA), and 2-point measurements extract the output integration slope to remove flicker noise and fixed pattern noise.
Sara Tejedor Sanz3, Sandra Grijalva4, Adam Wang1, Sensen Li1, Hee Cheol Cho4, Caroline Ajo-Franklin5, Hua Wang1 The complex cellular impedance sensing circuit is illustrated in Fig. 28.4.3. The two WEs in each pixel oper
ISSCC 2020
Session 28
Medical & Bio
A 5.2Mpixel 88.4dB-DR 12in CMOS X-Ray Detector with 16b Column-Parallel Continuous-Time ΔΣ ADCs
a full image depth even for a specific region of interest, and require high resolution, low noise, and wide DR in a wafer-scale detector [1-4]. To achieve a wide DR, a large integration capacitor is required within the p
ISSCC 2020
Session 28
Medical & Bio
A 51dB-SNR 120Hz-Scan-Rate 32×18 Segmented-VCOM LCD In-Cell Touch-Display-Driver IC with 96-Channel Compact Shunt-Sensing Self-Capacitance Analog Front-End
display implementation have been undertaken in recent years, with several being successfully delivered to the industry and market. As a result, in-cell touch-display solutions that offer low-profile formfactor, low modul
ISSCC 2020
Session 28
Medical & Bio
A Capacitive Touch Chipset with 33.9dB ChargeOverflow Reduction Using Amplitude-Modulated Multi-Frequency Excitation and Wireless Power and Data Transfer to an Active Stylus
systems (CTSs), several driving methods have been reported [1-5]. However, when excitation circuits simultaneously send excitation signals (VEXTs) to multiple TX electrodes in order to increase frame rate, the readout ci
ISSCC 2020
Session 27
Hardware Security
Physically Unclonable Function in 28nm FDSOI Technology Achieving High Reliability for AEC-Q100 Grade 1 and ISO26262 ASIL-B
Physically Unclonable Functions (PUFs) are considered a secure method for security key generation because they generate responses that exist only during operation. A challenge regarding the use of PUFs is to achieve high
ISSCC 2020
Session 27
Hardware Security
EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation
Shovan Maity1, Baibhab Chatterjee1, Donghyun Seo1, Muya Chang2, Avinash Varna3, Harish Krishnamurthy4, Sanu Mathew4, Santosh Ghosh4, Arijit Raychowdhury2, Shreyas Sen1 Purdue University, West Lafayette, IN Georgia Instit
ISSCC 2020
Session 27
Hardware Security
M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power
Jonas Svedas1, Matthew J Walker1, Supreet Jeloka2, Philex Ming-Yan Fan1, Fernando García-Redondo1, Thanusree Achuthan1, James Myers1 ARM, Cambridge, United Kingdom, 2ARM, Austin, TX 1 Recent research has shown subthresho
ISSCC 2020
Session 27
Hardware Security
A 65nm Energy-Harvesting ULP SoC with 256kB CortexM0 Enabling an 89.1µW Continuous Machine Health Monitoring Wireless Self-Powered System
Kyle Craig2, Greg Glennon2, Kuo-Ken Huang3, Christopher J. Lukas2, William Moore3, Richard K. Sawyer2, Yousef Shakhsheer2,4, Farah B. Yahya2, Alice Wang3, Nathan E. Roberts2, David D. Wentzloff1, Benton H. Calhoun2 Evera
ISSCC 2020
Session 26
Medical & Bio
A 0.19×0.17mm2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry
Paras R. Patel1, Parag G. Patil1, Sechang Oh1, Inhee Lee1, Hun-Seok Kim1, Dennis Sylvester1, David Blaauw1, Cynthia A. Chestek1, Jamie Phillips1, Taekwang Jang2 University of Michigan, Ann Arbor, MI ETH Zürich, Zürich, S
ISSCC 2020
Session 26
Medical & Bio
A Trimodal Wireless Implantable Neural Interface System-on-Chip
5Bionic Sciences, Atlanta, GA 1 3 Implantable biomedical devices (IMDs) capable of injecting a designated current into target neural tissue to modulate neural activity have been proven therapeutically effective. The next
ISSCC 2020
Session 26
Medical & Bio
A 280µW 108dB DR Readout IC with Wireless Capacitive Powering Using a Dual-Output Regulating Rectifier for Implantable PPG Recording
The development of advanced neuroprostheses for restoration of function after spinal cord injury (SCI) is one of the most rapidly growing directions for neuroengineering research. Among the most exciting solutions is a n
ISSCC 2020
Session 26
Medical & Bio
A 6.5µW 10kHz-BW 80.4dB-SNDR Continuous-Time ΔΣ Modulator with Gm-Input and 300mVpp Linear Input Range for Closed-Loop Neural Recording
Kwandong University International St. Mary’s Hospital, Incheon, Korea 1 2 Closed-loop neural recording requires a front-end with a wide DR to record small neural signals without distortion in the presence of a DC electro
ISSCC 2020
Session 26
Medical & Bio
A 20µW Heartbeat Detection System-on-Chip Powered by Human Body Heat for Self-Sustaining Wearable Healthcare
*Equally-Credited Authors (ECAs) Wearable devices are expanding beyond consumer and entertainment applications, including continuous monitoring of vital signs for medical diagnostics, due to extended ambulatory measureme
ISSCC 2020
Session 26
Medical & Bio
A Cell-Capacitance-Insensitive CMOS Sample-and-Hold Chronoamperometric Sensor for Real-Time Measurement of Small Molecule Drugs in Whole Blood exponential model). Most of the signal-of-interest lies within the first 10ms after the potential stepping, indicating that the ADC can be further powered off during the other 90ms. The sensor front-end is configured to perform SWV calibration every few tens of minutes to track drift in the redox potential.
with a tail current of 320µA are employed in the DAC reference buffer, the current conveyor, and the potentiostat. The Miller-compensated RC network in the potentiostat is removed to avoid instability. To minimize leakag
ISSCC 2020
Session 26
Medical & Bio
A Closed-Loop Neuromodulation Chipset with 2-Level Classification Achieving 1.5Vpp CM Interference
Aerosemi Technology, Xi'an, China 1 2 In closed-loop neuromodulators for epilepsy patients, nonidealities such as common-mode interference (CMI), stimulation artifacts (SA), electrode DC offset (DCO) and 1/f noise bring
ISSCC 2020
Session 26
AI / ML
A Neuromorphic Multiplier-Less Bit-Serial WeightMemory-Optimized 1024-Tree Brain-State Classifier and Neuromodulation SoC with an 8-Channel Noise-Shaping SAR ADC Array
Camilo Tejeiro1, Maged ElAnsary1, Chenxi Tang1, Homeira Moradi2, Prajay Shah1, Taufik A. Valiante3, Roman Genov1 University of Toronto, Toronto, Canada Krembil Neuroscience Center, Toronto, ON, Canada 3 Toronto Western H
ISSCC 2020
Session 25
Digital Circuits
Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for HighPerformance Processors with Wide Voltage-Frequency Operating Range
Raghavan Kumar, H. Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De Intel, Hillsboro, OR The clock frequency of high-performance processo
ISSCC 2020
Session 25
Digital Circuits
A Near-Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain UltraLow-Power System-on-a-Chip
demand a new system-on-a-chip (SoC) that is ultra-low power (mW or even sub-mW level) but highly robust. Such an SoC typically integrates heterogeneous building blocks for supporting a range of features, each ideally ope
ISSCC 2020
Session 25
Digital Circuits
Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS
Gregory Chen1, Monodeep Kar1, Raghavan Kumar1, Huseyin Sumbul1, Phil Knag1, Himanshu Kaul1, Sanu Mathew1, Mahesh Kumashikar2, Ram Krishnamurthy1, Vivek De1 Intel, Hillsboro, OR Intel, Bangalore, India 1 2 Flip-flops (FFs
ISSCC 2020
Session 25
Digital Circuits
A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique are generated from the reference frequency, to perform a frequency-shaping SSPD, the associated switch size needs to be minimized to avoid additional spurs at the output.
These PLLs exhibit features like small area, large tuning range, and multiple output phases. However, their jitter performance is worse than that in LC-oscillator-based PLLs. Although a wider PLL bandwidth can reduce the
ISSCC 2020
Session 25
Digital Circuits
A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS
Intel, Hillsboro, OR errors, which are compensated by the DTC-gain-correction loop. Each delay stage uses tristate inverter-based multiplexer (MUX) and switched capacitor banks to realize coarse and fine delays, respecti
ISSCC 2020
Session 25
Digital Circuits
A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing
Power-supply noise (PSN) is a key consideration that determines the performance, as well as functionality of ICs, especially for modern SoCs with significantly increased scale, level of integration, and sophisticated vol
ISSCC 2020
Session 25
Digital Circuits
A 65nm Edge-Chasing Quantizer-Based Digital LDO Featuring 4.58ps-FoM and Side-Channel-Attack Resistance
Low-Dropout Regulators (LDOs) are commonly desired for fine-grained power management in SoCs because of their compact area, high current efficiency, and small output ripple. Digital LDOs (DLDOs) are increasingly adopted
ISSCC 2020
Session 25
Digital Circuits
A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector
intellectual properties (IPs) for better energy efficiency in a system-on-chip design
ISSCC 2020
Session 25
Digital Circuits
A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS
regulation for digital IP blocks. A distributed LDO architecture, where a number of dispersed LDO units supply a single domain with shared power delivery network (PDN), has been recently proposed for point-of-load regula
ISSCC 2020
Session 24
RF & Wireless
A W-Band Power Amplifier with Distributed CommonSource GaN HEMT and 4-Way Wilkinson-Lange Combiner Achieving 6W Output Power and 18% PAE at 95GHz
Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing, China 1 2 W-band power amplifiers (PAs) play an important role in Gb/s-data-rate wireless communication, imaging, and radar applic
ISSCC 2020
Session 24
RF & Wireless
A 15dBm 12.8%-PAE Compact D-Band Power Amplifier with Two-Way Power Combining in 16nm FinFET CMOS
The drive for higher data-rates has led to the allocation of the spectrum above 100GHz for D-band communication. A high level of integration in a nm-CMOS technology is necessary to keep the cost low and allow for efficie
ISSCC 2020
Session 24
RF & Wireless
An Instantaneously Broadband Ultra-Compact Highly Linear PA with Compensated Distributed-Balun Output Network Achieving >17.8dBm P1dB and >36.6% PAEP1dB over 24 to 40GHz and Continuously Supporting 64-/256-QAM 5G NR Signals over 24 to 42GHz
5G communication promises 10× to 100× data-rate increase to radically change future wireless connectivity. Millimeter-wave (mm-wave) bands can potentially deliver extreme data rates and capacity compared to low-GHz bands
ISSCC 2020
Session 24
AI / ML
A 15b Quadrature Digital Power Amplifier with Transformer-Based Complex-Domain Power-Efficiency Enhancement
law to provide compact die area, better interface to digital back-end, and higher power efficiency due to the faster switching nature of core devices even in face of reduced supply voltages. Moreover, the integration of
ISSCC 2020
Session 24
RF & Wireless
A Watt-Level Multimode Multi-Efficiency-Peak Digital Polar Power Amplifier with Linear Single-Supply ClassG Technique
Signals for next-generation communication systems typically have high peak-toaverage power ratios (PAPR) (e.g., 10 to 13dB), forcing operation at deep output power backoff (PBO). A good efficiency at PBO is required to m
ISSCC 2020
Session 24
RF & Wireless
A 28GHz Current-Mode Inverse-Outphasing Transmitter Achieving 40%/31% PA Efficiency at Psat/6dB PBO and Supporting 15Gbit/s 64-QAM for 5G Communication
As mm-wave offers broader spectra and proportionate capacity increase, it will be extensively employed in 5G-and-beyond communication systems to address the exponentially growing data-rate demand. Viable mm-wave TX or PA
ISSCC 2020
Session 24
RF & Wireless
A Reconfigurable Series/Parallel Quadrature-CouplerBased Doherty PA in CMOS SOI with VSWR Resilient Linearity and Back-Off PAE for 5G MIMO Arrays
reconfigurations remain the same. In addition, the Main/Aux-PAs role exchange for series/parallel Doherty operation is enabled by setting the bias of two adaptive biasing circuits. Naga Sasikanth Mannem, Min-Yu Huang, Tz
ISSCC 2020
Session 24
AI / ML
A 24-to-30GHz Watt-Level Broadband Linear Doherty Power Amplifier with Multi-Primary Distributed-ActiveTransformer Power-Combining Supporting 5G NR FR2 64-QAM with >19dBm Average Pout and >19% Average PAE
The continuous worldwide demand for multi-Gb/s data-rate has driven the rapid development and standardization of 5G New Radio (NR) specifications in the mmwave bands [1-3]. As a result, there is a surge of interest in hi
ISSCC 2020
Session 23
Analog Circuits
A 41µW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation
performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlin
ISSCC 2020
Session 23
Analog Circuits
A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication
Interfacing with high-impedance sensors, such as dry-contacted electrodes and accelerometers requires high CMRR with sufficient input impedance concurrently. From the system point of view, the total CMRR (TCMRR) is deter
ISSCC 2020
Session 23
Analog Circuits
A 2pA/√Hz Transimpedance Amplifier for Miniature Ultrasound Probes with 36dB Continuous-Time Gain Compensation
ultrasound probes, such as the intra-cardiac echography (ICE) probe shown in Fig. 23.6.1, increasingly employ in-probe ASICs to interface with the elements of an ultrasound transducer array to improve signal quality and
ISSCC 2020
Session 23
Analog Circuits
A 0.41mA Quiescent Current, 0.00091% THD+N ClassD Audio Amplifier with Frequency Equalization for PWMResidual-Aliasing Reduction
a pulse-width-modulation (PWM) modulator and a switching power stage is commonly adopted since it effectively suppresses the power-stage nonlinearity to improve total harmonic distortion plus noise (THD+N). However, unle
ISSCC 2020
Session 23
Analog Circuits
A 28W -108.9dB/-102.2dB THD/THD+N Hybrid ΔΣ-PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission around two-stage feedforward OTAs which together draw 1.8mA from a 1.8V supply. This combination of multilevel quantization together with a high fS results in a loop gain of >76dB (26dB higher than [6]) in the audio band irrespective of process spread, thus ensuring high linearity.
Lucien Breems2, Marco Berkhout3, Qinwen Fan1, Kofi A.A. Makinwa1 The fully differential H-bridge output stage is shown in Fig. 23.4.1. It consists of four identical N-LDMOS devices (MH and ML) with an RON of ~100m$, whic
ISSCC 2020
Session 23
Analog Circuits
A 0-to-60V-Input VCM Coulomb Counter with SignalDependent Supply Current and ±0.5% Gain Inaccuracy from -50°C to 125°C Caspar van Vroonhoven
charge, (SOC). A straightforward way to determine SOC is to keep track of the current flowing in and out of a battery, a method known as coulomb counting. Compared to other methods such as voltage or impedance monitoring
ISSCC 2020
Session 23
Analog Circuits
A 70µW 1.19mm2 Wireless Sensor with 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver
Emerging wireless multi-channel resistive and capacitive (RC) sensor interface circuits provide opportunities for various applications such as environmental monitoring [1], wearable [2] and human-computer interaction [3]
ISSCC 2020
Session 23
Analog Circuits
A 4GS/s 80dB DR Current-Domain Analog Front-End for Phase-Coded Pulse-Compression Direct Time-of-Flight Automotive LiDAR
Ken Wojciechowski, Christoph Lang Robert Bosch, Sunnyvale, CA LiDARs enable long-distance ranging at high spatial resolution and moderate computational effort. Pulsed-LiDARs measuring the direct-time-of-flight (dTOF) per
ISSCC 2020
Session 22
Memory
A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface
paths also increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins because of the reduced timing budget. However, phase errors between multiphase clocks, due to device mismatch, degrade
ISSCC 2020
Session 22
Memory
An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique
Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyoung-Hoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park Samsung Electronics, Hwaseong, Korea Recent emerging a
ISSCC 2020
Session 22
Memory
A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor
Single-ended transceivers that can deliver high-data rates at reduced supply voltages are required to meet the ever-growing demands of future memory interfaces. The performance of conventional non-return-to-zero (NRZ) li
ISSCC 2020
Session 22
Memory
A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo
Dong Uk Lee, Ho Sung Cho, Jihwan Kim, Young Jun Ku, Sangmuk Oh, Chul Dae Kim, Hyun Woo Kim, Woo Young Lee, Tae Kyun Kim, Tae Sik Yun, Min Jeong Kim, SeungGyeon Lim, Seong Hee Lee, Byung Kuk Yun, Jun Il Moon, Ji Hwan Park