ISSCC 2018
Session 18
Digital Circuits
A Fully Integrated 40pF Output Capacitor BeatFrequency-Quantizer-Based Digital LDO with Built-In Adaptive Sampling and Active Voltage Positioning
University of Minnesota, Minneapolis, MN Cisco Systems, San Jose, CA 1 2 Integrated voltage regulators with a wide output current/voltage dynamic range are required to support fast dynamic voltage and frequency scaling (
ISSCC 2018
Session 18
Digital Circuits
A 0.4V 430nA Quiescent Current NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28nm CMOS
University of Electronic Science and Technology of China, Chengdu, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal the number of registers. The fine loop contains an 8b SR, controlling eight 1×s
ISSCC 2018
Session 18
Digital Circuits
A 2.5µW 0.0067mm2 Automatic Back-Biasing Compensation Unit Achieving 50% Leakage Reduction in FDSOI 28nm over 0.35-to-1V VDD Range
STMicroelectronics, Crolles, France 1 2 Worst-case design and post-silicon tuning are well established digital design practices reducing timing violations in presence of process, temperature, aging and voltage variations
ISSCC 2018
Session 18
Digital Circuits
A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor
Naveen John, Visvesh S. Sathe University of Washington, Seattle, WA Integrated Voltage Regulation (IVR) using buck converters enables efficient, finegrained supply-voltage control in modern SoC domains [1]. However, exis
ISSCC 2018
Session 18
Digital Circuits
Droop Mitigation Using Critical-Path Sensors and an On-Chip Distributed Power Supply Estimation Engine in the z14TM Enterprise Processor
Preetham Lobo3, Richard Rizzolo4, Tobias Webel2, Pawel Owczarczyk4, Alper Buyuktosunoglu1, Ramon Bertran1, David Hui4, Susan M. Eickhoff4, Michael Floyd5, Gerard Salem6, Sean Carey4, Stelios G. Tsapepas4, Phillip J. Rest
ISSCC 2018
Session 17
Digital Processors
A Recursive-Memory Brain-State Classifier with 32-Channel Track-and-Zoom Δ2Σ ADCs and Charge-Balanced Programmable Waveform Neurostimulators
David Groppe2, Taufik A. Valiante3, Naveen Verma4, Roman Genov1 University of Toronto, Toronto, Canada Krembil Neuroscience Center, Toronto, Canada 3 Toronto Western Hospital, Toronto, Canada 4 Princeton University, Prin
ISSCC 2018
Session 17
Digital Processors
A 665μW Silicon Photomultiplier-Based NIRS/EEG/EIT Monitoring ASIC for Wearable Functional Brain Imaging
Hyunsoo Ha1, Roland van Wegberg1, Erfan Sheikhi1, Massimo Mazzillo3, Giorgio Fallica3, Walter De Raedt2, Chris Van Hoof2,4, Nick Van Helleputte2 imec - Holst Centre, Eindhoven, The Netherlands; 2imec, Leuven, Belgium 3 S
ISSCC 2018
Session 17
Digital Processors
A 330μm×90μm Opto-Electronically Integrated Wireless System-on-Chip for Recording of Neural Activities
Paul L. McEuen, Alyosha C. Molnar Cornell University, Ithaca, NY Recording neural activity in live animals in vivo poses several challenges. Electrical techniques typically require electrodes to be tethered to the outsid
ISSCC 2018
Session 17
Digital Processors
A 200Mb/s Inductively Coupled Wireless Transcranial Transceiver Achieving 5e-11 BER and 1.5pJ/b Transmit Energy Efficiency
Inphi, Santa Clara, CA 1 2 Recent advancements in medical neural science and brain research have enabled the potential of uninterrupted simultaneous recording of thousands of neurons. To minimize the risk of infection to
ISSCC 2018
Session 17
Digital Processors
50nW 5kHz-BW Opamp-Less ΔΣ Impedance Analyzer for Brain Neurochemistry Monitoring
Suzie Dufou1,2, Peter L. Carlen1,2, Michael Thompson1, Roman Genov1 University of Toronto, Toronto, Canada Toronto Western Hospital, Toronto, Canada 1 2 Potassium (K+) and sodium (Na+) ions are the main signal carriers i
ISSCC 2018
Session 17
Digital Processors
A 0.28mΩ-Sensitivity 105dB-Dynamic-Range Electrochemical Impedance Spectroscopy SoC for Electrochemical Gas Detection
Colin Lyden3, Yincai Liu1, Junbiao Ding4, Dennis Dempsey2, Leicheng Chen1, Donal Bourke3, Shurong Gu1, Jun Gao1, Lizhu Lu1, Li Wang1, Xuemin Li1, Hongxing Li5, Chao Chu1, Ling Yang1 Analog Devices, Beijing, China; 2Analo
ISSCC 2018
Session 17
Digital Processors
A 0.3V Biofuel-Cell-Powered Glucose/Lactate Biosensing System Employing a 180nW 64dB SNR Passive ΔΣ ADC and a 920MHz Wireless Transmitter
Itthipon Jeerapan, Joseph Wang, Patrick P. Mercier University of California, San Diego, La Jolla, CA Wearable physiochemical biosensors offer an exciting opportunity to monitor the concentration of ions and metabolites i
ISSCC 2018
Session 17
Digital Processors
4-Camera VGA-Resolution Capsule Endoscope with 80Mb/s Body-Channel Communication Transceiver and Sub-cm Range Capsule Localization
alternative to the cable-attached endoscopes since not only mitigating pain and fear of patients but also acquiring additional information about unexplained lesions for accurate diagnoses. Nevertheless, their applicabili
ISSCC 2018
Session 16
Wireline I/O
A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
Taiwan 4 National Chiao Tung University, Hsinchu, Taiwan 1 2 Contactless chip-to-chip or board-to-board proximity (~1mm) communications have been realized by using either wireless transmission [1-3], or inductive/capacit
ISSCC 2018
Session 16
Wireline I/O
A 1.17pJ/b 25Gb/s/pin Ground-Referenced SingleEnded Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator
Xi Chen2, Sudhir S. Kudva2, Sanquan Song2, Stephen G. Tell1, Nikola Nedovic2, Wenxu Zhao1a, Sunil R. Sudhakaran2, C. Thomas Gray1, William J. Dally2 Nvidia, Durham, NC; 2Nvidia, Santa Clara, CA 1 a now with Broadcom, Irv
ISSCC 2018
Session 16
Wireline I/O
A 126mW 56Gb/s NRZ Wireline Transceiver for Synchronous Short-Reach Applications in 16nm FinFET
Pedro Neto1, Mayank Raj2, Scott McLeod3, Hongtao Zhang2, Arianne Roldan2, Hongyuan Zhao4, Ping-Chuan Chiang4, Haibing Zhao4, KeeHian Tan4, Yohan Frans2, Ken Chang2 Xilinx, Cork, Ireland Xilinx, San Jose, CA 3 Acacia Comm
ISSCC 2018
Session 16
Wireline I/O
A 7.8Gb/s/pin 1.96pJ/b Compact Single-Ended TRX and CDR with Phase-Difference Modulation for Highly Reflective Memory Interfaces
strongly demanded by the memory industry. Although discontinuous reflective channels like multi-drop DRAM interfaces are less suitable for high data rates than continuous point-to-point channels, their great advantages i
ISSCC 2018
Session 16
Wireline I/O
A 20Gb/s Transceiver with Framed-Pulsewidth Modulation in 40nm CMOS
interference (ISI), which necessitates the enhancement of spectral efficiency. Recently, various modulation schemes including pulse amplitude modulation (PAM) [1], pulsewidth modulation (PWM) [2], permutation modulation
ISSCC 2018
Session 16
Wireline I/O
A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS
Christian Menolfi1, Matthias Braendli1, Thomas Morf1, Dan Kuchta3, Lukas Kull1, Marcel Kossel1, Danny Luu1, Mounir Meghelli3, Yusuf Leblebici2, Thomas Toifl1 IBM Research, Ruschlikon, Switzerland EPFL, Lausanne, Switzerl
ISSCC 2018
Session 16
Wireline I/O
A 28Gb/s Transceiver with Chirp-Managed EDC for DML Systems
medium-reach optical links owing to their simplicity and cost effectiveness. However, the chirp phenomenon under direct modulation limits the reach (2-10km) in a standard single-mode fiber (SMF). Although diverse optical
ISSCC 2018
Session 15
AI / ML
An 82-to-108GHz -181dB-FOMT ADPLL Employing a DCO with Split-Transformer and Dual-Path SwitchedCapacitor Ladder and a Clock-Skew-Sampling DeltaSigma TDC
the W-band. At 100GHz, DCOs become more sensitive to parasitics resulting in low frequency resolution. A high-resolution delta-sigma TDC is used to reduce quantization noise by noise-shaping in [2], but it suffers from l
ISSCC 2018
Session 15
RF & Wireless
A Dividerless Reference-Sampling RF PLL with -253.5dB Jitter FOM and <-67dBc Reference Spurs
In the recent past, there have been exciting advances in dividerless PLLs, such as sub-sampling PLLs (SSPLLs) [1,2] and injection-locked clock multipliers (ILCMs) [3] that substantially reduce loop noise to cross the -25
ISSCC 2018
Session 15
RF & Wireless
A 0.01mm2 4.6-to-5.6GHz Sub-Sampling Type-I Frequency Synthesizer with –254dB FOM
Power consumption, Performance in terms of phase noise and integrated jitter, and Area (PPA) are three design metrics that have driven countless research efforts in CMOS frequency-synthesizer design. Design limitations a
ISSCC 2018
Session 15
RF & Wireless
A Digital Frequency Synthesizer with Dither-Assisted Pulling Mitigation for Simultaneous DCO and Reference Path Coupling
Injection pulling on frequency synthesizers has become a critical design challenge for high-performance wireless transceivers, especially in highly integrated multiradio platforms, imposing stringent constraints on syste
ISSCC 2018
Session 15
RF & Wireless
A Low-Phase-Noise Digital Bang-Bang PLL with Fast Lock Over a Wide Lock Range
power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolu
ISSCC 2018
Session 15
RF & Wireless
A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS Fractional-N FMCW Chirp Synthesizer PLL with a Continuous-Time Bandpass Delta-Sigma Time-to-Digital Converter rotation allows us to emulate the divider-ratio step size of 8/32 = 1/4. Since the phase rotation occurs ahead of the final divider stage, we perform only one phase shift per divider output cycle to retain the step size of 1/4 for the entire divider chain. A 2nd-order ΔΣ modulator controls the phase rotation for fractional-N division. Finally, on-chip chirp control logic modulates the PLL division ratio to generate the desired FMCW waveform profile.
Broadcom, Irvine, CA 1 Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-di
ISSCC 2018
Session 15
RF & Wireless
A 23GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Saw-Tooth Chirp Modulation
with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems
ISSCC 2018
Session 15
RF & Wireless
A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FOM of -246dB for IoT Applications in 65nm CMOS
ultra-lowpower (ULP) transceivers (TRX) will be key elements in a variety of short-range network applications. The RF PLL in a TRX needs a significant amount of power due to the phase noise and spurious requirement. Comp
ISSCC 2018
Session 14
Data Converters
A Signal-Independent Background-Calibrating 20b 1MS/s SAR ADC with 0.3ppm INL and calibration noise (the larger μe, the faster calibration but higher calibration noise).
Derek Hummerston3, Naveed Naeem1 The ADC core, which implements this technique, is shown in Fig. 14.7.3. The framework is a pipelined SAR ADC architecture [3] to extend the acquisition time. The first stage has 11b resol
ISSCC 2018
Session 14
Data Converters
A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator
With advanced DAC switching [1-3] and low-power comparator [4] techniques, the successive-approximation register (SAR) ADC demonstrates convincing performance with technology development for internet-of-everything (IoE)
ISSCC 2018
Session 14
Data Converters
A 280μW Dynamic-Zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW
Robert Van Veldhoven2, Kofi A. A. Makinwa1 Delft University of Technology, Delft, The Netherlands NXP Semiconductors, Eindhoven, The Netherlands 1 2 Micro-power ADCs with high linearity and dynamic range (DR) are require
ISSCC 2018
Session 14
Data Converters
A 1.1mW 200kS/s Incremental ΔΣ ADC with a DR of 91.5dB Using Integrator Slicing for Dynamic Power Reduction
Nyquist-rate ADCs with high resolution are needed in many applications where, for example, multiplexed operation is needed as for multichannel sensor readout. For various tasks such as averaging-based analysis or lock-in
ISSCC 2018
Session 14
Data Converters
A 13-ENOB 2nd-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using an Error-Feedback Structure
The noise-shaping (NS) SAR ADC is an emerging hybrid architecture that achieves high resolution and power-efficiency simultaneously by combining the merits of the SAR ADC and the ΔΣADC, making it attractive to sensor rea
ISSCC 2018
Session 14
Data Converters
A 15.2-ENOB Continuous-Time ΔΣ ADC for a 7.3μW 200mVpp-Linear-Input-Range Neural Recording Front-End
Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to advance deep brain stimulation (DBS) therapies. However, stimulation generates large artifacts (~100mV) at the recording sites that satu
ISSCC 2018
Session 14
Data Converters
A 50MHz-BW Continuous-Time ΔΣ ADC with Dynamic Error Correction Achieving 79.8dB SNDR and 95.2dB SFDR
MediaTek, Woburn, MA 1 2 Continuous-time ΔΣ modulators (CTDSMs) are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requi
ISSCC 2018
Session 13
AI / ML
A 232-to-1996KS/s Robust Compressive-Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring
Compressive sensing (CS) techniques enable new reduced-complexity designs for sensor nodes and help reduce overall transmission power in wireless sensor network [1-2]. Prior CS reconstruction chip designs have been descr
ISSCC 2018
Session 13
AI / ML
A 1.8Gb/s 70.6pJ/b 128×16 Link-Adaptive Near-Optimal Massive MIMO Detector in 28nm UTBB-FDSOI
Lund University, Lund, Sweden data movements using holding buffers to maximize data reuse. The data reuse is especially advantageous in our design, as it requires a relatively long 28b data bit width to support a wide ra
ISSCC 2018
Session 13
AI / ML
An Always-On 3.8μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28nm CMOS
latency, bandwidth, and privacy has created demand for low-energy deep convolutional neural networks (CNNs). The single-layer classifier in [1] achieves sub-nJ operation, but is limited to moderate accuracy on low-comple
ISSCC 2018
Session 13
AI / ML
A 9.02mW CNN-Stereo-Based Real-Time 3D Hand-Gesture Recognition Processor for Smart Mobile Devices
Recently, 3D hand-gesture recognition (HGR) has become an important feature in smart mobile devices, such as head-mounted displays (HMDs) or smartphones for AR/VR applications. A 3D HGR system in Fig. 13.4.1 enables user
ISSCC 2018
Session 13
AI / ML
UNPU: A 50.6TOPS/W Unified Deep Neural Network Accelerator with 1b-to-16b Fully-Variable Weight Bit-Precision
deep learning algorithms from face recognition to emotion recognition in mobile or embedded environments [3]. However, most works accelerate only the convolutional layers (CLs) or fully-connected layers (FCLs), and diffe
ISSCC 2018
Session 13
AI / ML
QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS
Shinya Takamaeda-Yamazaki1, Junichiro Kadomoto2, Tomoki Miyata2, Mototsugu Hamada2, Tadahiro Kuroda2, Masato Motomura1 Hokkaido University, Sapporo, Japan Keio University, Yokohama, Japan 1 2 A key consideration for deep
ISSCC 2018
Session 12
Memory
A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with Improved Power Distribution and Repair Strategy
Kwidong Kim, Kyeongtae Kim, Sangho Lee, Jinhoon Hyun, Insung Koh, Joonhong Park, Minjeong Kim, Sunhye Shin, Dongha Lee, Yunyoung Lee, Sangah Hyun, Wonjohn Choi, Dain Im, Dongheon Lee, Jieun Jang, Sangho Lee, Junhyun Chun
ISSCC 2018
Session 12
Memory
A 16Gb/s/pin 8Gb GDDR6 DRAM with Bandwidth Extension Techniques for High-Speed Applications
Dae-Han Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-Young Jang, Seung-Hun Lee, Yong-Suk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh, Jinkook Ki
ISSCC 2018
Session 12
Memory
A 1.2V 64Gb 341GB/s HBM2 Stacked DRAM with Spiral Point-to-Point TSV Structure and Improved Bank Group Data Control
Heat Bit Park, Chunseok Jeong, Myeong-Jae Park, Seung Geun Baek, Seokwoo Choi, Byung Kuk Yoon, Young Jae Choi, Kyo Yun Lee, Daeyong Shim, Jonghoon Oh, Jinkook Kim, Seok-Hee Lee SK hynix, Gyeonggi, Korea With the recent i
ISSCC 2018
Session 12
Memory
A 16Gb LPDDR4X SDRAM with an NBTI-Tolerant
Technique, an Adaptive Gear-Down Scheme and a Metastable-Free DQS Aligner in a 10nm Class DRAM Process Ki Chul Chun, Yong-Gyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Juhwan K
ISSCC 2018
Session 12
Memory
A 16Gb 18Gb/s/pin GDDR6 DRAM with Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hu
ISSCC 2018
Session 11
Memory
A 5GHz 7nm L1 Cache Memory Compiler for High-Speed Computing and Mobile Applications
will typically determine the maximum frequency (fMAX) of the processor core. Companies that mass produce high-performance microprocessors commonly have the L1 cache consist of fully-custom macros: to ensure that the perf
ISSCC 2018
Session 11
Memory
A 7nm FinFET SRAM Using EUV Lithography with Dual Write-Driver-Assist Circuitry for Low-Voltage Applications
Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, JaeSeung Choi, Jong Shik Yoon Samsung Electronics, Hwaseong, Korea SRAM plays an integral role in the power, performance,
ISSCC 2018
Session 11
Memory
A 23.6Mb/mm2 SRAM in 10nm FinFET Technology with Pulsed PMOS TVC and Stepped-WL for Low-Voltage Applications
accompanied by a sustained growth of battery-powered mobile devices, continues to drive the importance of energy and area efficient CPU and SoC designs. Low-voltage operation remains one of the primary approaches for act
ISSCC 2018
Session 10
Sensors
A 100mK-NETD 100ms-Startup-Time 80×60 MicroBolometer CMOS Thermal Imager Integrated with a 0.234mm2 1.89μVrms Noise 12b Biasing DAC
Ji-Su Choi1, Min-Woo Ko1, Jeong-hyun Cho1, Sangjin Lim1, Hyung-Min Lee2, Hyun-Sik Kim3, Kwyro Lee1, Gyu-Hyeong Cho1 KAIST, Daejeon, Korea; 2Korea University, Seoul, Korea Dankook University, Cheonan, Korea 1 3 A micro-bo