ISSCC 2018
Session 10
AI / ML
A 0.3ppm Dual-Resonance Transformer-Based DriftCancelling Reference-Free Magnetic Sensor for Biosensing Applications
Cost-efficient, point-of-use diagnostics are critical for early disease detection. Traditionally, the majority of lab-based analysis equipment utilizes fluorescent markers for biodetection assays. However, magnetic-based
ISSCC 2018
Session 10
Sensors
Single-Chip Reduced-Wire Active Catheter System with Programmable Transmit Beamforming and Receive Time-Division Multiplexing for Intracardiac Echocardiography
Coskun Tekes1, David M. J. Cowell2, Steven Freear2, F. Levent Degertekin1, Maysam Ghovanloo1 Georgia Institute of Technology, Atlanta, GA University of Leeds, Leeds, United Kingdom 1 2 Intracardiac echocardiography (ICE)
ISSCC 2018
Session 10
Sensors
A 0.91mW/Element Pitch-Matched Front-End ASIC with Integrated Subarray Beamforming ADC for Miniature 3D Ultrasound Probes
Mingliang Tan1, Hendrik J. Vos1,2, Johan G. Bosch2, Martin D. Verweij1,2, Nico de Jong1,2, Michiel A. P. Pertijs1 Delft University of Technology, Delft, The Netherlands Erasmus MC, Rotterdam, The Netherlands 1 2 Data acq
ISSCC 2018
Session 10
Sensors
A Noise-Immune Stylus Analog Front-End Using Adjustable Frequency Modulation and LinearInterpolating Data Reconstruction for Both Electrically Coupled Resonance and Active Styluses
Hyung-Jong Ko1, San-Ho Byun1, Jin-Chul Lee1, Yong-Hoon Lee1, Yeong-Cheol Rhee1, Yoon-Kyung Choi1, Byung-Hoon Kang2, Chang-Byung Park2, Sungsoo Park2, Taesung Kim2 Samsung Electronics, Hwaseong, Korea Samsung Electronics,
ISSCC 2018
Session 10
Sensors
Multi-Way Interactive Capacitive Touch System with Palm Rejection of Active Stylus for 86" Touch Screen Panels
Jae-Hun Ye4, Seung-Hwan Lee1, Ji-Yong Jeong1, Jung Soo Kim1, Kwang-Hyun Baek3, Ki-Seok Chung1, Seong-Kwan Hong1, Oh-Kyong Kwon1 Hanyang University, Seoul, Korea; 2Leading UI, Anyang, Korea Chung-Ang University, Seoul, Ko
ISSCC 2018
Session 10
Sensors
Personal Inertial Navigation System Employing MEMS Wearable Ground Reaction Sensor Array and Interface ASIC Achieving a Position Accuracy of 5.5m Over 3km Walking Distance Without GPS
Cleveland, OH 1 2 An accurate personal inertial navigation system under GPS-denied environment is highly critical for demanding applications such as firefighting, rescue missions, and military operations. Location-aware
ISSCC 2018
Session 10
Sensors
Chopped Rate-to-Digital FM Gyroscope with 40ppm Scale Factor Accuracy and 1.2dph Bias
Present implementations of MEMS gyroscopes measure rate indirectly by first converting it to a displacement [1,2]. In this case, the scale factor is a complex function of the transducer and readout circuits. Changes of a
ISSCC 2018
Session 1
Plenary
50 years of Computer Architecture: From the Mainframe CPU to the Domain-Specific TPU and the Open RISC-V Instruction Set
Each had its own unique instructionset architecture (ISA); I/O system; system software (assemblers, compilers, libraries); and market niches (business, scientific, real time). IBM engineers bet that they could invent a s
ISSCC 2018
Session 1
Plenary
Future Mobility- Enhanced Society Enabled by Semiconductor Technology
1. Introduction The automotive industry is in the midst of a once-in-a-century transformation. The industry began adopting semiconductors in the 1960s, starting with rectifier diodes for alternators. Then, the spread of
ISSCC 2018
Session 1
Plenary
Brain-Inspired Technologies: Towards Chips that Think?
Abstract The advent of the Internet-of-Things has introduced a new paradigm that supports a decentralized and hierarchical communication architecture, where a great deal of analytics processing occurs at the edge and at
ISSCC 2018
Session 1
Plenary
Semiconductor Innovation: Is the party over, or just getting started?
Semiconductor Innovation Trends: The hardware paradigm underpinning the Information and Communications Technology (ICT) industry has experienced three major shifts over the past 60 years - the mainframe era, the personal
ISSCC 2017
Session 9
Sensors
A 0.6nm Resolution 19.8mW Eddy-Current Displacement Sensor Interface with 126MHz Excitation
Kofi A. A. Makinwa1, Stoyan Nihtianov1 Delft University of Technology, Delft, The Netherlands Catena Microelectronics, Delft, The Netherlands DC gain and >1GHz GBW (≈ 8*fmix) with a 1pF capacitive load. The OTA consists
ISSCC 2017
Session 9
Sensors
An Energy-Efficient 3.7nV/√Hz Bridge-Readout IC with a Stable Bridge Offset Compensation Scheme
Wheatstone bridge sensors are often used in precision instrumentation and measurement systems, e.g., for μK-resolution temperature sensing in wafer steppers [1] and mPa-resolution differential pressure sensing in precisi
ISSCC 2017
Session 9
Sensors
A 6.9mW 120fps 28×50 Capacitive Touch Sensor with 41.7dB SNR for 1mm Stylus Using Current-Driven ΔΣ ADCs
Capacitive touch sensors are essential for the user interfaces of smartphones and tablet PCs. Large touch-screen panels (TSPs) require high-quality touch features, resulting in an increased number of sensing channels as
ISSCC 2017
Session 9
Sensors
A 3.9kHz-Frame-Rate Capacitive Touch System with Pressure/Tilt Angle Expressions of Active Stylus Using Multiple-Frequency Driving Method for 65" 104×64 Touch Screen Panel
Young-Hwan Kim2, Han-Hee Hong2, Jae-Hun Ye4, Sung-Jin Jung1, Seung-Hwan Lee1, Ji-Yong Jeong1, Kwang-Hyun Baek3, Seong-Kwan Hong1, Oh-Kyong Kwon1 Hanyang University, Seoul, Korea Leading UI, Anyang, Korea 3 Chung-Ang Univ
ISSCC 2017
Session 9
Sensors
A 1.8V True-Differential 140dB SPL Full-Scale Standard CMOS MEMS Digital Microphone Exhibiting 67dB SNR
share in consumer applications such as mobile phones and hearing aids. The consumer market is demanding improved quality for audio recording, while also being capable of suppressing high-energy disturbers, e.g., wind noi
ISSCC 2017
Session 9
Sensors
A 27μW 0.06mm2 Background Resonance Frequency Tuning Circuit Based on Noise Observation for a 1.71mW CT-ΔΣ MEMS Gyroscope Readout System with 0.9°/h Bias Instability
closed-loop configuration (CL) to satisfy the demand for high-performance and stable inertial sensors [1]. Due to the higher complexity and power consumption compared to open-loop solutions, these systems have usually be
ISSCC 2017
Session 9
Sensors
A BJT-Based Temperature Sensor with a PackagingRobust Inaccuracy of ±0.3°C (3σ) from -55°C to +125°C After Heater-Assisted Voltage Calibration
This paper presents a BJT-based temperature sensor, which can be accurately trimmed in both ceramic and plastic packages, on the basis of purely electrical measurements at room temperature. This is achieved by combining
ISSCC 2017
Session 9
Sensors
A 0.6nJ -0.22/+0.19°C Inaccuracy Temperature Sensor Using Exponential Subthreshold Oscillation Dependence
features in IoT devices to monitor either environmental or system/chip conditions. An accurate temperature sensor usually requires carefully calibrated, high-accuracy ADCs, which prevents their use in ultra-low-power sen
ISSCC 2017
Session 9
Sensors
A Resistor-Based Temperature Sensor with a 0.13pJ·K2 Resolution FOM
temperature compensation of frequency references [1-5]. High resolution and energy efficiency are then critical requirements, the former to minimize jitter and the latter to minimize power dissipation in a given conversi
ISSCC 2017
Session 8
Digital Circuits
A 0.0047mm2 Highly Synthesizable TDC- and DCOLess Fractional-N PLL with a Seamless Lock Range of fREF to 1GHz
develop methodologies for fully automated digital design of key analog building blocks. The phase-locked loop (PLL) is a block for which an all-digital implementation has been sought recently. There have been several app
ISSCC 2017
Session 8
Digital Circuits
A 2.5-to-5.75GHz 5mW 0.3psrms-Jitter Cascaded Ring-Based Digital Injection-Locked Clock Multiplier in 65nm CMOS
traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter r
ISSCC 2017
Session 8
Digital Circuits
A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO
(ILPLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core l
ISSCC 2017
Session 8
Digital Circuits
A 2.5ps 0.8-to-3.2GHz Bang-Bang Phase- and Frequency-Detector-Based All-Digital PLL with Noise Self-Adjustment
their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, such as mismatch, process, supply voltage, a
ISSCC 2017
Session 8
Digital Circuits
A 553F2 2-Transistor Amplifier-Based Physically Unclonable Function (PUF) with 1.67% Native Instability
Physically Unclonable Functions (PUFs) are among the most promising security primitives for low cost solutions of key storage, chip authentication, and supply chain protection. Two types of PUFs exist in literature [1-6]
ISSCC 2017
Session 8
Digital Circuits
8Mb/s 28Mb/mJ Robust True-Random-Number Generator in 65nm CMOS Based on Differential Ring Oscillator with Feedback Resistors
On-chip true random number generators (TRNG) have been gaining attention as an important component for building secure systems [1]. CMOS TRNGs typically exploit device-level noise, such as thermal or flicker noise to gen
ISSCC 2017
Session 8
Digital Circuits
Improved Power-Side-Channel-Attack Resistance of an AES-128 Core via a Security-Aware Integrated Buck Voltage Regulator
g. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), are major threats to the security of crypto engines in SoC platforms. Circuit-level SCA countermeasures to achieve dataindependent supply current
ISSCC 2017
Session 7
Wireless
A 118mW 23.3GS/s Dual-Band 7.3GHz and 8.7GHz Impulse-Based Direct RF Sampling Radar SoC in 55nm CMOS
Sumit Bagga1, Håkon A. Hjortland1, Mats Risopatron Knutsen1, Tor Sverre Lande2, Dag T. Wisland1,2 Novelda AS, Oslo, Norway University of Oslo, Oslo, Norway 1 2 Radar sensors find use in a wide range of applications [1–4]
ISSCC 2017
Session 7
Wireless
A +8dBm BLE/BT Transceiver with Automatically Calibrated Integrated RF Bandpass Filter and -58dBc TX HD2
Internet-of-Things (IoT) applications, highly integrated ultra-low-power (ULP) RF transceivers are essential, and numerous solutions have been proposed [3,4]. These architectures address the less-stringent Bluetooth Low-
ISSCC 2017
Session 7
Wireless
A TCXO-Less 100Hz-Minimum-Bandwidth Transceiver for Ultra-Narrow-Band Sub-GHz IoT Cellular Networks
Christophe Fourtet2, Laurent Ouvry1, Florent Lepin1, Eric Mercier1, Steve Hamard2, Lionel Zirphile2, Sébastien Thuries1, Fabrice Chaix1 CEA-LETI-MINATEC, Grenoble, France Sigfox, Labège, France 1 2 Ultra-narrow-band (UNB
ISSCC 2017
Session 7
Wireless
A 915MHz Asymmetric Radio Using Q-Enhanced Amplifier for a Fully Integrated 3×3×3mm3 Wireless Sensor Node with 20m Non-Line-of-Sight Communication
Zhiyoong Foo1,2, Gyouho Kim1,2, Yejoong Kim1,2, Anthony Grbic1, David Wentzloff1, Hun-Seok Kim1, David Blaauw1 University of Michigan, Ann Arbor, MI CubeWorks, Ann Arbor, MI 1 2 Enabling long range (>10m) wireless commun
ISSCC 2017
Session 7
Wireless
A 40nm Low-Power Transceiver for LTE-A Carrier Aggregation
Chung-Yun Chou1, Sheng-Che Tseng1, Chih-Hsien Shen1, Yu-Tsung Lu1, Hsinhung Chen1, Song-Yu Yang1, Yen-Tso Chen1, Guang-Kaai Dehng1, Yangjian Chen2, Christophe Beghein2, Dimitris Nalbantis2, Manel Collados2, Bernard Tenbr
ISSCC 2017
Session 7
Wireless
A 28GHz 32-Element Phased-Array Transceiver IC with Concurrent Dual Polarized Beams and 1.4 Degree Beam-Steering Resolution for 5G Communication
Scott Reynolds1, Örjan Renström3, Kristoffer Sjögren2, Olov Haapalahti3, Nadav Mazor4, Bo Bokinge3, Gustaf Weibull2, Håkan Bengtsson3, Anders Carlinger3, Eric Westesson5, Jan-Erik Thillberg3, Leonard Rexberg3, Mark Yeck1
ISSCC 2017
Session 7
Wireless
An 802.11ac Dual-Band Reconfigurable Transceiver Supporting up to Four VHT80 Spatial Streams with 116fsrms-Jitter Frequency Synthesizer and Integrated LNA/PA Delivering 256QAM 19dBm per Stream Achieving 1.733Gb/s PHY Rate
Ming-Chung Liu1, Po-Yu Chang1, Chia-Jen Liang1, Yi-Chu Chen1, Hsi-Liang Lu1, Jian-Yu Ding1, Chin-Chung Wang1, Yu-Li Hsueh1, Jen-Che Tsai1, Min-Shun Hsu1, Yuan-Hung Chung1, George Chien2 MediaTek, Hsinchu, Taiwan; 2MediaT
ISSCC 2017
Session 6
Wireline I/O
A 28Gb/s Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance
(CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes th
ISSCC 2017
Session 6
Wireline I/O
A 22.5-to-32Gb/s 3.2pJ/b Referenceless Baud-Rate Digital CDR with DFE and CTLE in 28nm CMOS
circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received data only once per UI [1,2]. This reduces the number of front-end comparators and
ISSCC 2017
Session 6
Wireline I/O
A 1.8pJ/b 56Gb/s PAM-4 Transmitter with Fractionally Spaced FFE in 14nm CMOS
As data rates in electrical links rise to 56Gb/s, standards are gravitating towards PAM-4 modulation to achieve higher spectral efficiency. Such approaches are not without drawbacks, as PAM-4 signaling results in reduced
ISSCC 2017
Session 6
Wireline I/O
A 64Gb/s PAM-4 Transmitter with 4-Tap FFE and 2.26pJ/b Energy Efficiency in 28nm CMOS FDSOI
Walter Audoglio1, Augusto Andrea Rossi1, Simone Erba1, Matteo Bassi2, Andrea Mazzanti2 STMicroelectronics, Pavia, Italy University of Pavia, Pavia, Italy 1 2 Electrical link migration requires serial interfaces to operat
ISSCC 2017
Session 6
Wireline I/O
A 40-to-56Gb/s PAM-4 Receiver with 10-Tap Direct Decision-Feedback Equalization in 16nm FinFET
Adam Chou1, Tim Cronin1, Kevin Geary3, Scott McLeod1, Lei Zhou1, Ian Zhuang1, Jaeduk Han4, Sen Lin4, Parag Upadhyaya1, Geoff Zhang1, Yohan Frans1, Ken Chang1 Xilinx, San Jose, CA Xilinx, Singapore, Singapore 3 Xilinx, Co
ISSCC 2017
Session 6
Wireline I/O
A 60Gb/s 288mW NRZ Transceiver with Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65nm CMOS Technology
Qualcomm Atheros, San Jose, CA 1 2 The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decr
ISSCC 2017
Session 6
Wireline I/O
A 56Gb/s PAM-4/NRZ Transceiver in 40nm CMOS
Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/dese
ISSCC 2017
Session 5
Analog Circuits
An 18.75μW Dynamic-Distributing-Bias Temperature Sensor with 0.87°C(3σ) Untrimmed Inaccuracy and 0.00946mm2 Area
The overall system mismatch will be averaged out through the lowpass digital counter, and the stable output codes can be obtained. The measured differences between the cases with and without the DEM are shown in Fig. 5.9
ISSCC 2017
Session 5
Analog Circuits
A 9.3nW All-in-One Bandgap Voltage and Current Reference Circuit
have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various intern
ISSCC 2017
Session 5
Analog Circuits
A 19nV/√Hz-Noise 2μV-Offset 75μA Low-Drift Capacitive-Gain Amplifier with Switched-Capacitor ADC Driving Capability
(CGA) with amplifier common-mode sampling (CMS) and switched-capacitor driving capability, compatible with many conventional switched-capacitor ADC inputs (SCAI) such as delta-sigma modulators or SAR ADCs. CGAs are popul
ISSCC 2017
Session 5
Analog Circuits
A 0.68nW/kHz Supply-Independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C Stability
are attractive for integrated clock sources compared to LC and ring oscillators (RO), as LC oscillators pose integration challenges and RO designs have limited voltage and temperature (V-T) stability. RxOs generate a clo
ISSCC 2017
Session 5
Analog Circuits
A Quadrature Relaxation Oscillator with a ProcessInduced Frequency-Error Compensation Loop
wearable and implantable technologies, there has been growing demand on development of key enabling circuits for ultra-low-power sensor interface SoCs. As a reference-frequency generation block for clock management of th
ISSCC 2017
Session 5
Analog Circuits
Frequency-Locked-Loop Ring Oscillator with 3ns Peak-to-Peak Accumulated Jitter in 1ms Time Window for High-Resolution Frequency Counting
Many sensing applications require a high-resolution frequency measurement. These applications include measurement of pressure, acceleration and eddycurrent sensing. In these applications the sensor is part of an oscillat
ISSCC 2017
Session 5
Analog Circuits
A 95μW 24MHz Digitally Controlled Crystal Oscillator for IoT Applications with 36nJ Start-Up Energy and >13× Start-Up Time Reduction Using A FullyAutonomous Dynamically-Adjusted Load
g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce the overall system power consumption [1]. This requires swift start-up behavior of the transceiver. The crystal oscillator (
ISSCC 2017
Session 5
Analog Circuits
An 8Ω 10W 91%-Power-Efficiency 0.0023%-THD+N Multi-Level Class-D Audio Amplifier with Folded PWM
Yeunhee Huh, Kye-Seok Yoon, Jong-Beom Baek, Yong-Min Ju, Gibbeum Lee, Homin Park, Hyeon-Min Bae, Gyu-Hyeong Cho KAIST, Daejeon, Korea As the portable device market tries to enhance user experience, high-power audio syste
ISSCC 2017
Session 5
Analog Circuits
A 65nm Inverter-Based Low-Dropout Regulator with Rail-to-Rail Regulation and over -20dB PSR at 0.2V Lowest Supply Voltage
Ultra-low-voltage operation is highly demanded in a system that adopts the DVFS scheme, e.g., a portable device that sustains days-long standby with a tiny battery. Such a system usually embeds modules that have specific