ISSCC 2017
Session 5
Analog Circuits
A 1A LDO Regulator Driven by a 0.0013mm2 Class-D Controller
Marvell, Santa Clara, CA A low-dropout (LDO) regulator generates a DC supply for electronic systems. Today’s high-throughput wireless system-on-chips (SOCs) require large dynamic range of supply current, which demands a
ISSCC 2017
Session 5
Analog Circuits
A 5×80W 0.004% THD+N Automotive Multiphase Class-D Audio Amplifier with Integrated Low-Latency ΔΣ ADCs for Digitized Feedback after the Output Filter problem, a special low-latency ΔΣ ADC (LLADC) is proposed with lowpass filtering DACs (FIRDACs) in its feedback path. By giving the digital filter the same transfer function as the FIRDAC, the overall signal transfer function (STF) becomes approximately flat with little phase shift, while HF quantization noise is reduced.
Remko van Heeswijk1, Marto-Jan Koerts1, Eric van Iersel1, Daniel Groeneveld2, Gertjan van Holland1, Patrick Zeelen1, Derk-Jan Hissink1, Martin Pos1, Paul Wielage1, Fre Jorritsma1, Marc Klein Middelink1 The ADC core (Fig.
ISSCC 2017
Session 4
Image Sensors
A 1ms High-Speed Vision Chip with 3D-Stacked 140GOPS Column-Parallel PEs for Spatio-Temporal Image Processing
Masatsugu Kobayashi1, Sayaka Shida1, Masaki Odahara2, Kenichi Takamiya2, Yasuaki Hisamatsu2, Shizunori Matsumoto2, Leo Miyashita3, Yoshihiro Watanabe3, Takashi Izawa1, Yoshinori Muramatsu1, Masatoshi Ishikawa3 Sony Semic
ISSCC 2017
Session 4
Image Sensors
A 0.44e-rms Read-Noise 32fps 0.5Mpixel HighSensitivity RG-Less-Pixel CMOS Image Sensor Using Bootstrapping Reset
noise level, particularly, deep sub-electron read noise (less than 0.5e-rms), have been reported. Such an ultra-low noise level is realized with a reduced floating diffusion (FD) node capacitance for attaining the high p
ISSCC 2017
Session 4
Image Sensors
A 2.1Mpixel Organic-Film Stacked RGB-IR Image Sensor with Electrically Controllable IR Sensitivity
Masaaki Yanagida, Takayoshi Yamada, Masumi Izuchi, Yoshiaki Sato, Yasuo Miyake, Manabu Nakata, Masashi Murakami, Mitsuru Harada, Yasunori Inoue Panasonic, Osaka, Japan The use of infrared (IR) imaging to view scenes othe
ISSCC 2017
Session 4
Image Sensors
A 1/2.3inch 20Mpixel 3-Layer Stacked CMOS Image Sensor with DRAM
Taku Umebayashi1, Hiroshi Takahashi1, Kazuo Taniguchi1, Masami Kuroda1, Hiroshi Sumihiro1, Koji Enoki1, Takatsugu Yamasaki2, Katsuya Ikezawa1, Atsushi Kitahara1, Masao Zen1, Masafumi Oyama1, Hiroki Koga1, Hidenobu Tsugaw
ISSCC 2017
Session 4
Image Sensors
A 1.8e-rms Temporal Noise Over 110dB Dynamic Range 3.4μm Pixel Pitch Global Shutter CMOS Image Sensor
Masahiro Kobayashi, Yusuke Onuki, Kazunari Kawabata, Hiroshi Sekine, Toshiki Tsuboi, Yasushi Matsuno, Hidekazu Takahashi, Toru Koizumi, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue, Takeshi Ichikawa Canon, Kanag
ISSCC 2017
Session 4
Image Sensors
A Sub-nW 80mlx-to-1.26Mlx Self-Referencing Light-to-Digital Converter with AlGaAs Photodiode
Wearable sensors are increasingly common and continue to grow more diverse in their sensing modalities, ranging from glucose to heart rate monitoring. One compelling sensing modality for wearable sensors is cumulative li
ISSCC 2017
Session 4
Image Sensors
A Programmable Sub-Nanosecond Time-Gated 4-Tap Lock-In Pixel CMOS Image Sensor for Real-Time Fluorescence Lifetime Imaging Microscopy
effective methods in life science and medicine. Among others, fluorescence lifetime imaging microscopy (FLIM) is one of the representative measurement techniques for biomedical applications. Recently, advanced all-solid-
ISSCC 2017
Session 4
Image Sensors
A Fully Integrated CMOS Fluorescence Biochip for Multiplex Polymerase Chain-Reaction (PCR) Processes
Bob Kuimelis, Sara Bolouki, Pejman Naraghi-Arani, Kirsten Johnson, Mark McDermott, Nicholas Wood, Piyush Savalia, Nader Gamini InSilixa, Sunnyvale, CA Integration and miniaturization of bio-molecular detection systems in
ISSCC 2017
Session 4
Image Sensors
A 640×480 Dynamic Vision Sensor with a 9μm Pixel and 300Meps Address-Event Representation
Changwoo Shin1, Keunju Park1, Kyoobin Lee1, Jinman Park1, Jooyeon Woo1, Yohan Roh1, Hyunku Lee1, Yibing Wang2, Ilia Ovsiannikov2, Hyunsurk Ryu1 Samsung Advanced Institute of Technology, Suwon, Korea Samsung Electronics,
ISSCC 2017
Session 3
Digital Processors
A 1920×1080 30fps 2.3TOPS/W Stereo-Depth Processor for Robust Autonomous Navigation
realizing autonomous navigation on micro-aerial vehicles (MAVs). The state-of-the-art semi-global matching (SGM) algorithm has become favored for its high accuracy. In particular, it effectively handles low texture regio
ISSCC 2017
Session 3
Digital Processors
A 60pJ/b 300Mb/s 128×8 Massive MIMO Precoder-Detector in 28nm FD-SOI
Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohi
ISSCC 2017
Session 3
Digital Processors
A 40nm Flash Microcontroller with 0.80μs FieldOriented-Control Intelligent Motor Timer and Functional Safety System for Next-Generation EV/HEV
Ryosaku Kobayashi2, Masayuki Utsuno1, Fumitake Takami1, Sugako Otani1, Masayuki Ito1, Yasuhisa Shimazaki1, Naoki Yada1, Hiroyuki Kondo1 Renesas Electronics, Tokyo, Japan Renesas System Design, Tokyo, Japan 1 2 Electric V
ISSCC 2017
Session 3
Digital Processors
A 10nm FinFET 2.8GHz Tri-Gear Deca-Core CPU Complex with Optimized Power-Delivery Network for Mobile SoC Performance
Sumanth Gururajarao1, Rolf Lagerquist1, Jin Son1, Gordon Gammie1, Gordon Lin2, Achuta Thippana1, Kent Li1, Manzur Rahman1, Wuan Kuo2, David Yen2, Yi-Chang Zhuang2, Ue Fu2, Hung-Wei Wang2, Mark Peng3, Cheng-Yuh Wu2, Taner
ISSCC 2017
Session 3
Digital Processors
A 14nm 1GHz FPGA with 2.5D Transceiver Integration
Kok Hong Chan1, Andy Tong1, Sean Atsatt1, Dana How1, Peter McElheny1, Keith Duwel1, Jeffrey Schulz1, Darren Faulkner3, Gopal Iyer1, George Chen1, Hee Kong Phoon4, Han Wooi Lim4, Wei-Yee Koay4, Ty Garibay3 Intel, San Jose
ISSCC 2017
Session 3
Digital Processors
Zen: A Next-Generation High-Performance x86 Core
Shane Southard1, Hugh McIntyre3, Amy Novak1, Stephen Kosonocky2, Ravi Jotwani1, Alex Schaefer1, Edward Chang2, Joshua Bell1, Michael Co1 AMD, Austin, TX AMD, Fort Collins, CO 3 AMD, Sunnyvale, CA 1 2 Codenamed “Zen”, AMD
ISSCC 2017
Session 3
Digital Processors
POWER9TM: A Processor Family Optimized for Cognitive Computing with 25Gb/s Accelerator Links and 16Gb/s PCIe Gen4
Rahul Rao3, Jose Paredes2, Michael Floyd2, Michael Sperling4, Ryan Kruse2, Vinod Ramadurai2, Ryan Nett2, Saiful Islam2, Juergen Pille5, Donald Plass4 IBM, Yorktown Heights, NY IBM, Austin, TX 3 IBM, Bangalore, India 4 IB
ISSCC 2017
Session 29
Wireline I/O
A 2.5GHz Injection-Locked ADPLL with 197fsrms Integrated Jitter and -65dBc Reference Spur Using Time-Division Dual Calibration
7.3 shows the implemented schematic of the TDDC. The ILO is based on a pseudo-differential 4-stage ring oscillator, whose frequency is controlled by the 10b FCW. The frequency resolution is 100kHz/LSB. The FEPMD controls
ISSCC 2017
Session 29
Wireline I/O
A 3-to-10Gb/s 5.75pJ/b Transceiver with Flexible Clocking in 65nm CMOS
This 2-step truncation and cancellation method provides higher order modulation while avoiding -1 to 1 and 1 to -1 jumps, which limits the needed DCDL range to 1 cycle of CKHF, independent of output frequency/data rate.
ISSCC 2017
Session 29
Wireline I/O
12Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling with 100% Data Payload and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces
29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery
ISSCC 2017
Session 29
Wireline I/O
A 16Gb/s 3.6pJ/b Wireline Transceiver with Phase Domain Equalization Scheme: Integrated Pulse Width Modulation (iPWM) in 65nm CMOS
Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FF
ISSCC 2017
Session 29
Wireline I/O
A 40Gb/s PAM-4 Transmitter Based on a RingResonator Optical DAC in 45nm SOI CMOS
Milos A. Popovic5, Vladimir Stojanovic1 University of California, Berkeley, CA Ayar Labs, San Francisco, CA 3 ETH Zurich, Zurich, Switzerland 4 Massachusetts Institute of Technology, Cambridge, MA 5 Boston University, Bo
ISSCC 2017
Session 29
Wireline I/O
A Transmitter and Receiver for 100Gb/s Coherent Networks with Integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS
Mehdi Khanpour, Kangmin Hu, Tamer Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz Broadcom, Irvine, CA At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated wit
ISSCC 2017
Session 29
Wireline I/O
A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET
Christian Menolfi1, Thomas Morf1, Matthias Brandli1, Dan Kuchta2, Lukas Kull1, Jon Proesel2, Marcel Kossel1, Danny Luu1, Benjamin Lee2, Fuad Doany2, Mounir Meghelli2, Yusuf Leblebici3, Thomas Toifl1 IBM Research, Rueschl
ISSCC 2017
Session 28
Data Converters
A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique
g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and highresolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the b
ISSCC 2017
Session 28
Data Converters
A 78.5dB-SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating up to 75MS/s with 24.9mW Power Consumption in 65nm CMOS
Irvine, CA 4 Southern Methodist University, Dallas, TX 1 2 High-resolution, low-power radiation-tolerant ADCs are under great demand from medical, aerospace and high-energy physics applications. In the ATLAS Liquid Argon
ISSCC 2017
Session 28
Data Converters
A 10b 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET
Alessandro Cevrero1, Ilter Ozkaya1, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland ETH Zurich, Zurich, Switzerland 1 2 High-speed SAR ADCs became popular with modern CMOS technologies because of t
ISSCC 2017
Session 28
Data Converters
A 12b 330MS/s Pipelined-SAR ADC with PVTStabilized Dynamic Amplifier Achieving <1dB SNDR Variation
Texas Instruments, Dallas, TX 1 2 In high-speed pipeline or pipelined-SAR ADCs, conventional opamp-based residue amplifiers consume significant amounts of power due to stringent settling speed and accuracy requirements.
ISSCC 2017
Session 28
Data Converters
A 125MHz-BW 71.9dB-SNDR VCO-Based CT ΔΣ ADC with Segmented Phase-Domain ELD Compensation in 16nm CMOS
MediaTek, Woburn, MA High-BW continuous-time ΔΣ modulators (CTDSMs), which directly inject excess loop delay compensation (ELDC) at the quantizer input, suffer from the over-range issue due to the 1+αz-1 transfer functio
ISSCC 2017
Session 28
Data Converters
An 11.4mW 80.4dB-SNDR 15MHz-BW CT Delta-Sigma Modulator Using 6b Double-Noise-Shaped Quantizer
Quantizers are key building blocks in both continuous-time (CT) and discrete-time (DT) delta-sigma modulators (DSMs). Among various types of quantizers, noiseshaping quantizers such as VCO-based quantizers and noise-shap
ISSCC 2017
Session 28
Data Converters
A 0.46mW 5MHz-BW 79.7dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter
The successive approximation register (SAR) ADC is the most energy efficient architecture with moderate conversion rate and resolution. However, its comparator noise limits its resolution without sacrificing power effici
ISSCC 2017
Session 27
Medical & Bio
Fully Integrated Optical Spectrometer with 500-to-830nm Range in 65nm CMOS
Next-generation IoT systems are expected to be enabled by compact, low-cost, low-power, smart sensing devices that provide a wealth of information to build new applications and capabilities. Among sensing modalities, opt
ISSCC 2017
Session 27
Medical & Bio
A 30.5mm3 Fully Packaged Implantable Device with Duplex Ultrasonic Data and Power Links Achieving 95kb/s with <10-4 BER at 8.5cm Depth
invasive miniaturized solutions that operate reliably at large depths, provide duplex communication for closed-loop therapies, and enable multi-access for a network of implants to gather information or provide systemic i
ISSCC 2017
Session 27
Medical & Bio
Single-Chip 3072ch 2D Array IC with RX Analog and All-Digital TX Beamformer for 3D Ultrasound Imaging
Tatsuo Nakagawa2, Yasuyuki Okuma3, Yohei Nakamura2, Takahide Terada2, Yutaka Igarashi1, Taizo Yamawaki2, Toru Yazaki1, Yoshihiro Hayashi2, Kazuhiro Amino2, Takuya Kaneko2, Hiroki Tanaka2 Hitachi, Yokohama, Japan Hitachi,
ISSCC 2017
Session 27
Medical & Bio
A Pixel-Pitch-Matched Ultrasound Receiver for 3D Photoacoustic Imaging with Integrated Delta-Sigma Beamformer in 28nm UTBB FDSOI
in medical ultrasound rely on 3D volumetric imaging, calling for dense 2D transducer arrays with thousands of elements. Due to this high channel count, the traditional per-element cable interface used for 1D arrays is no
ISSCC 2017
Session 27
Medical & Bio
A Sub-1dB NF Dual-Channel On-Coil CMOS Receiver for Magnetic Resonance Imaging
Jonas Reber2, Josip Marjanovic2, Thomas Burger1, David O. Brunner2, Klaas P. Prüssmann2, Gerhard Tröster1, Qiuting Huang1 ETH Zurich, Zurich, Switzerland University and ETH Zurich, Zurich, Switzerland 1 2 Magnetic Resona
ISSCC 2017
Session 27
Medical & Bio
All-Wireless 64-Channel 0.013mm2/ch Closed-Loop Neurostimulator with Rail-to-Rail DC Offset Removal
M. Tariqus Salam3, Peter Carlen2,4, Jose Luiz Perez Velazquez2, Roman Genov2 York University, Toronto, Canada University of Toronto, Toronto, Canada 3 GSK (GlaxoSmithKline), Stevenage, United Kingdom 4 Toronto Western Ho
ISSCC 2017
Session 27
Medical & Bio
A 25.2mW EEG-NIRS Multimodal SoC for Accurate Anesthesia Depth Monitoring
monitoring of the quantitative anesthesia (ANES) depth level for safe surgery [1]. However, the current ANES depth monitoring approach, bispectral index (BIS) [3], uses only EEG from the frontal lobe, and it shows critic
ISSCC 2017
Session 27
Medical & Bio
A 2.8µW 80mVpp-Linear-Input-Range 1.6GΩ-Input Impedance Bio-Signal Chopper Amplifier Tolerant to Common-Mode Interference up to 650mVpp
Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to administer therapy in patients suffering from drug-resistant neurological ailments. However, stimulation generates large artifacts at th
ISSCC 2017
Session 26
Digital Processors
Adaptive Clocking in the POWER9TM Processor for Voltage Droop Protection
Pawel Owczarczyk3, Eric J. Fluhr1, Joshua Friedrich1, Paul Muench3, Timothy Diemoz3, Pierce Chuang2, Christos Vezyrtzis2 IBM, Austin, TX IBM, Yorktown Heights, NY 3 IBM, Poughkeepsie, NY 1 2 Increasing transistor counts
ISSCC 2017
Session 26
Digital Processors
A 0.4-to-1V 1MHz-to-2GHz Switched-Capacitor Adiabatic Clock Driver Achieving 55.6% Clock Power Reduction
Clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactanc
ISSCC 2017
Session 26
Digital Processors
Reconfigurable Clock Networks for Random Skew Mitigation from Subthreshold to Nominal Voltage
Clock network optimization is substantially affected by the operating voltage VDD, as the clock skew is dominated by different mechanisms and has a different balance between wire and repeater delay at different VDD (Fig.
ISSCC 2017
Session 26
Digital Processors
Power Supply Noise in a 22nm z13TM Microprocessor
Richard Rizzolo3, Tobias Webel4, Thomas Strach4, Otto Torreiter4, Preetham Lobo5, Alper Buyuktosunoglu1, Ramon Bertran1, Michael Floyd6, Malcolm Ware6, Gerard Salem7, Sean Carey8, Phillip Restle1 IBM Research, Yorktown H
ISSCC 2017
Session 25
Other
A 500Mb/s 200pJ/b Die-to-Die Bidirectional Link with 24kV Surge Isolation and 50kV/μs CMR using Resonant Inductive Coupling in 0.18μm CMOS
Kumar Anurag Shrivastava1, Madhulatha Bonu1, Benjamin Sutton2, Venugopal Gopinathan1, Ganesan Thiagarajan1, Abhijit Patki1, Jhankar Malakar1, Nagendra Krishnapura3 Texas Instruments, Bangalore, India Texas Instruments, D
ISSCC 2017
Session 25
Other
A 1.3A Gate Driver for GaN with Fully Integrated Gate Charge Buffer Capacitor Delivering 11nC Enabled by High-Voltage Energy Storing
The MN1 control and supply circuit (Fig. 25.3.2 bottom) turns on MN1 via MN2, controlled by level shifter LS. D2 prevents discharging of the MN2 gate capacitance, when node GMN1 rises. D3 ensures 5V-over-voltage protecti
ISSCC 2017
Session 25
Other
A 10MHz 3-to-40V VIN Tri-Slope Gate Driving GaN DC-DC Converter with 40.5dBμV Spurious Noise Compression and 79.3% Ringing Suppression for Automotive Applications
applications, DC-DC converters are widely employed [1]. However, size and thermal limits have made it challenging to continue using standard CMOS-based converters. Gallium Nitride (GaN) FETs, on the other hand, have a mu
ISSCC 2017
Session 25
Other
A 50.7% Peak Efficiency Subharmonic Resonant Isolated Capacitive Power Transfer System with 62mW Output Power for Low-Power Industrial Sensor Interfaces
industrial system reliability in hostile environments. They are exposed to destructive surge voltages, which are caused by ground current spikes from operation transitions of machinery and motor drives, endangering circu
ISSCC 2017
Session 24
Wireless
A 128-QAM 60GHz CMOS Transceiver for IEEE802.11ay with Calibration of LO Feedthrough and I/Q Imbalance
Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Ru
ISSCC 2017
Session 24
Wireless
A 14nm Fractional-N Digital PLL with 0.14psrms Jitter and -78dBc Fractional Spur for Cellular RFICs
Haoyang Li1, Kunal Godbole1, Yongrong Zuo1, Sangsoo Ko2, Nam-Seog Kim2, Sangwook Han2, Ikkyun Jo2, Joonhee Lee2, Juyoung Han2, Daehyeon Kwon2, Chulho Kim2, Shinwoong Kim2, Sang Won Son1, Thomas Byunghak Cho2 Samsung Semi