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ISSCC 2017 Session 19 Clocking & PLLs

A 50-to-66GHz 65nm CMOS All-Digital Fractional-N PLL with 220fsrms Jitter

Ahmed Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh

Digital-PLL frequency synthesizers for wireless applications have become popular in the sub-10GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the integer-N type [1]. This is due to li

Carnegie Mellon University, Pittsburgh, PA

ISSCC 2017 Session 19 Clocking & PLLs

A PVT-Robust -39dBc 1kHz-to-100MHz IntegratedPhase-Noise 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop Using the Averages of Phase Deviations for mm-Band 5G Transceivers

Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi

have an ultra-wide bandwidth in a mm-wave band. A big challenge of a 5G transceiver is to generate ultra-low-PN (phase noise) local-oscillator (LO) signals to suppress integrated PN (IPN) over such an extremely wide band

Ulsan National Institute of Science and Technology, Ulsan, Korea To me

ISSCC 2017 Session 19 Clocking & PLLs

A Fundamental-Frequency 114GHz Circular-Polarized

Radiating Element with 14dBm EIRP, -99.3dBc/Hz, Phase-Noise at 1MHz Offset and 3.7% Peak Efficiency

viable choice for imaging/sensing applications by offering faster scan time and robust source-detector alignment compared to linear radiation [1]. Power-efficient generation of a low-noise, highpower mm-wave/THz circular

Peyman Nazari, Saman Jafarlou, Payam Heydari University of California,

ISSCC 2017 Session 18 Wireless

A Single-Port Duplex RF Front-End for X-Band SingleAntenna FMCW Radar in 65nm CMOS

Yu-Hsien Kao1, Hao-Chung Chou1, Chun-Chieh Peng1, Yu-Jiu Wang2,

Frequency-modulated continuous-wave (FMCW) radars can provide high resolution and superior sensitivity for wireless sensing [1-3]. Radar signals, whose frequency increases or decreases linearly with time, are transmitted

Borching Su3, Ta-Shun Chu1 National Tsing Hua University, Hsinchu, Tai

ISSCC 2017 Session 18 Wireless

Highly-Linear Integrated Magnetic-Free CirculatorReceiver for Full-Duplex Wireless

Negar Reiskarimian, Mahmood Baraani Dastjerdi, Jin Zhou, Harish Krishnaswamy

implementation of low-cost, small-form-factor, integrated shared-antenna (ANT) interfaces with low loss, low noise, high TX-RX isolation, and large TX power handling. Providing more TX-RX isolation in the ANT interface t

Columbia University, New York, NY A fundamental challenge of full-dupl

ISSCC 2017 Session 18 Wireless

A 1.7-to-2.2GHz Full-Duplex Transceiver System with >50dB Self-Interference Cancellation over 42MHz Bandwidth

Tong Zhang, Ali Najafi, Chenxin Su, Jacques C. Rudell

Full-duplex (FD) radio communication potentially doubles the spectral efficiency in the densely occupied RF spectrum (100MHz to 5GHz). However, significant challenges remain, particularly the presence of a strong transmi

University of Washington, Seattle, WA

ISSCC 2017 Session 17 Wireline I/O

A 105Gb/s 300GHz CMOS Transmitter

Kyoya Takano1, Shuhei Amakawa1, Kosuke Katayama1, Shinsuke Hara2,

Ruibing Dong2, Akifumi Kasamatsu2, Iwao Hosako2, Koichi Mizuno3, Kazuaki Takahashi3, Takeshi Yoshida1, Minoru Fujishima1 Hiroshima University, Higashihiroshima, Japan National Institute of Information and Communications

ISSCC 2017 Session 17 Wireline I/O

A Compact 130GHz Fully Packaged Point-to-Point Wireless System with 3D-Printed 26dBi Lens Antenna Achieving 12.5Gb/s at 1.55pJ/b/m detection using mixers, which are power hungry. With the choice of an optimum current density for maximum gain (enhanced nonlinearity regime), and device size to fulfill the NF requirement based on input power, the ED consumes only 750μW, with NF<15dB at input sensitivity levels.

Nemat Dolatsha1, Baptiste Grave1,2, Mahmoud Sawaby1, Cheng Chen1,

Afshin Babveyh1, Siavash Kananian1, Aimeric Bisognin3,4, Cyril Luxey3, Frederic Gianesello4, Jorge Costa5,6, Carlos Fernandes7, Amin Arbabian1 To address the stringent link requirements, and also to utilize spatial degre

ISSCC 2017 Session 17 Wireline I/O

A Packaged 90-to-300GHz Transmitter and 115-to325GHz Coherent Receiver in CMOS for Full-Band Continuous-Wave mm-Wave Hyperspectral Imaging

Taiyun Chi, Min-Yu Huang, Sensen Li, Hua Wang

Millimeter-wave/THz hyperspectral imaging has numerous applications in security, non-destructive evaluation, material characterization, and medical diagnostics [1]. Unlike single-frequency imaging, hyperspectral imaging

Georgia Institute of Technology, Atlanta, GA

ISSCC 2017 Session 17 Wireline I/O

Rapid and Energy-Efficient Molecular Sensing Using Dual mm-Wave Combs in 65nm CMOS: A 220-to-320GHz Spectrometer with 5.2mW Radiated Power and 14.6-to-19.5dB Noise Figure

Cheng Wang, Ruonan Han

Millimeter-wave/terahertz rotational spectroscopy offers ultra-wide-detection range of gas molecules for chemical and biomedical sensing. Therefore, wideband, energy-efficient, and fast-scanning CMOS spectrometers are in

Massachusetts Institute of Technology, Cambridge, MA

ISSCC 2017 Session 17 Wireline I/O

An Intrinsically Linear Wideband Digital Polar PA Featuring AM-AM and AM-PM Corrections Through

Nonlinear Sizing, Overdrive-Voltage Control, and, Multiphase RF Clocking

Mohsen Hashemi1, Yiyu Shen1, Mohammadreza Mehrpoo1, Mustafa Acar2, René van Leuken1, Morteza S. Alavi1, Leonardus de Vreede1 Delft University of Technology, Delft, The Netherlands Ampleon, Nijmegen, The Netherlands 1 2 T

ISSCC 2017 Session 17 Wireline I/O

A Sub-mW Antenna-Impedance Detection Using Electrical Balance for Single-Step On-Chip Tunable Matching in Wearable/Implantable Applications

Chuang Lu, Ao Ba, Yao-Hong Liu, Xiaoyan Wang, Christian Bachmann, Kathleen Philips

g., heart-rate-monitor straps and implanted wireless sensors, need to be ultra-low-power (ULP), compact, and also robust against the proximity effect, which can significantly degrade the antenna and frontend performance

Holst Centre / imec, Eindhoven, The Netherlands Wearable/implantable d

ISSCC 2017 Session 17 Wireline I/O

A 60GHz On-Chip Linear Radiator with Single-Element 27.9dBm Psat and 33.1dBm Peak EIRP Using Multifeed Antenna for Direct On-Antenna Power Combining

Taiyun Chi, Fei Wang, Sensen Li, Min-Yu Huang, Jong Seok Park, Hua Wang

links, e.g., for the 5G communication, is to provide large transmitter (Tx) output power (Pout) with high energy efficiency and linearity from a limited supply voltage, so that the high path loss and limited link budget

Georgia Institute of Technology, Atlanta, GA A major challenge for low

ISSCC 2017 Session 17 Wireline I/O

A 28GHz Magnetic-Free Non-Reciprocal Passive CMOS Circulator Based on Spatio-Temporal Conductance Modulation

Tolga Dinc, Harish Krishnaswamy

A significant challenge for silicon-based mm-wave systems is a low-loss sharedantenna (ANT) interface with high linearity, isolation (ISO) and bandwidth (BW). Shared ANT interfaces with simultaneous transmit and receive

Columbia University, New York, NY

ISSCC 2017 Session 17 Wireline I/O

A 318-to-370GHz Standing-Wave 2D Phased Array in 0.13μm BiCMOS

Hossein Jalili, Omeed Momeni

Fully integrated implementation of mm-wave/THz radiators and phased arrays presents new potentials for applications like spectroscopy, imaging, and high data-rate communication. These applications demand sufficient radia

University of California, Davis, CA

ISSCC 2017 Session 17 Wireline I/O

A Digitally Assisted CMOS WiFi 802.11ac/11ax FrontEnd Module Achieving 12% PA Efficiency at 20dBm Output Power with 160MHz 256-QAM OFDM Signal

Yuen Hui Chee1, Fatih Golcuk1, Toru Matsuura1, Christopher Beale2,

James F. Wang1, Osama Shanaa1 MediaTek, San Jose, CA, 2MediaTek, Kent, United Kingdom 1 Front-end modules (FEM) typically employ expensive III-V or SiGe technologies to provide relatively higher PA output power and lower

ISSCC 2017 Session 16 Data Converters

A 12b 10GS/s Interleaved Pipeline ADC in 28nm CMOS Technology

Siddharth Devarajan1, Larry Singer1, Dan Kelly1, Steve Kosic2, Tao Pan1,

Jose Silva1, Janet Brunsilius2, Daniel Rey-Losada2, Frank Murden3, Carroll Speir3, Jeff Bray2, Eric Otte1, Nevena Rakuljic2, Phil Brown3, Todd Weigandt2, Qicheng Yu1, Donald Paterson1, Corey Petersen2, Jeffrey Gealow1 An

ISSCC 2017 Session 16 Data Converters

A 10b DC-to-20GHz Multiple-Return-to-Zero DAC with >48dB SFDR

Lucas Duncan1, Brian Dupaix1, Jamin McCue1, Brandon Mathieu1,

towards mm-wave frequencies has increased the demand for UWB DACs with minimal spurious emissions. At mm-wave, intra-DAC dynamic timing and data errors consume a significant portion of the clock period, degrading SFDR. P

Matthew LaRue1, Mesfin Teshome2, Myung-Jun Choe2, Waleed Khalil1 Ohio

ISSCC 2017 Session 16 Data Converters

An 8GS/s Time-Interleaved SAR ADC with Unresolved Decision Detection Achieving -58dBFS Noise and 4GHz Bandwidth in 28nm CMOS

John P. Keane1, Nathaniel J. Guilar1, Dusan Stepanovic1,2,

Bernd Wuppermann1, Charles Wu1, Cheongyuen W. Tsang1,3, Robert Neff1, Ken Nishimura1 Keysight Technologies, Santa Clara, CA 1 now with Apple, Cupertino, CA 3 now with Adecco, Mountain View, CA compared using an XNOR gate

ISSCC 2017 Session 16 Data Converters

A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration

Chi-Hang Chan1, Yan Zhu1, Iok-Meng Ho1, Wai-Hong Zhang1,

Wireless communication systems and Ethernet networks call for moderateresolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardwar

Seng-Pan U1,2, Rui Paulo Martins1,3 University of Macau, Macao, China

ISSCC 2017 Session 16 Data Converters

A 330mW 14b 6.8GS/s Dual-Mode RF DAC in 16nm FinFET Achieving -70.8dBc ACPR in a 20MHz Channel at 5.2GHz

Christophe Erdmann, Edward Cullen, Damien Brouard, Roberto Pelliconi,

Bob Verbruggen, John Mcgrath, Diarmuid Collins, Marites De La Torre, Pierrick Gay, Patrick Lynch, Peng Lim, Anthony Collins, Brendan Farley Xilinx, Dublin, Ireland Direct-RF synthesis has gained increasing attention in r

ISSCC 2017 Session 16 Data Converters

A 9GS/s 1GHz-BW Oversampled Continuous-Time Pipeline ADC Achieving -161dBFS/Hz NSD

Hajime Shibata1, Victor Kozlov1, Zexi Ji1, Asha Ganesan2, Haiyang Zhu2, Donald Paterson2

front-end by a switchedcapacitor circuit and all internal signals are processed in discrete-time (DT) even though the front-end sampler introduces artifacts such as aliasing, noise folding, and high-peak ADC driving curr

Analog Devices, Toronto, Canada Analog Devices, Wilmington, MA 1 2 In

ISSCC 2017 Session 16 Data Converters

A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Asynchronous Pipelined-SAR ADC

Bruno Vaz1, Adrian Lynam1, Bob Verbruggen1, Asma Laraba2,

Conrado Mesadri1, Ali Boumaalif3, John Mcgrath3, Umanath Kamath1, Ronnie De Le Torre1, Alvin Manlapat1, Daire Breathnach3, Christophe Erdmann1, Brendan Farley1 Xilinx, Dublin, Ireland Xilinx, San Jose, CA 3 Xilinx, Cork,

ISSCC 2017 Session 15 Other

An Integrated Optical Physically Unclonable Function Using Process-Sensitive Sub-Wavelength Photonic Crystals in 65nm CMOS power meter to characterize the incident power, while the other half of the laser light shines uniformly on the chip under test. This setup is used to characterize the spectral responsivity of the photonic crystal, but is not required to generate responses for the PUF signature. The photonic structure itself serves as a linear polarizer that rejects incoming light in other polarization.

Xuyang Lu, Lingyu Hong, Kaushik Sengupta

Physical unclonable function (PUF) is regarded as an emerging solution for reliable cryptography. Rather than storing secret keys in memories, the information of a PUF is extracted through amplification of the physically

Princeton University, Princeton, NJ

ISSCC 2017 Session 15 Other

A Permanent Digital Archive System Based on 4F2 X-Point Multi-Layer Metal Nano-Dot Structure

Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata

Data is saved by the presence of a metal nano-dot at a x-point of interconnects. This passive storage node works as a permanent memory cell with >1,000-years endurance. No transistor is used in the cell, enabling multi-l

Kobe University, Kobe, Japan A 4F2 permanent digital archive system is

ISSCC 2017 Session 15 Other

Heterogeneous Integrated CMOS-Graphene Sensor Array for Dopamine Detection

Bayan Nasri, Ting Wu, Abdullah Alharbi, Mayank Gupta,

for advancing our knowledge of pathological disorders such as drug addiction, Parkinson’s disease, and schizophrenia. Currently, fast-scan cyclic voltammetry (FSCV) with carbon microfiber (CMF) electrodes is the method o

Ramkumar RanjitKumar, Sunit Sebastian, Yue Wang, Roozbeh Kiani, Davood

ISSCC 2017 Session 15 Other

A 30-to-80MHz Simultaneous Dual-Mode Heterodyne Oscillator Targeting NEMS Array Gravimetric Sensing Applications with a 300zg Mass Resolution

Guillaume Gourlat, Marc Sansa, Patrick Villard, Gilles Sicard,

scale physical variations has led to the breakthrough development of NEMS-based mass spectrometry systems capable of measuring a single molecule [1]. Parallel sensing using thousands of devices will help to circumvent th

Guillaume Jourdan, Issam Ouerghi, Gérard Billiot, Sébastien Hentz CEA-

ISSCC 2017 Session 15 Other

Cryo-CMOS Circuits and Systems for Scalable Quantum Computing

Edoardo Charbon1,2,3, Fabio Sebastiano1, Masoud Babaie1,

Andrei Vladimirescu4,5, Mina Shahmohammadi1, Robert Bogdan Staszewski1, Harald A.R. Homulle1, Bishnu Patra1, Jeroen P.G. van Dijk1, Rosario M. Incandela1, Lin Song1,6, Bahador Valizadehpasha1 Delft University of Technolo

ISSCC 2017 Session 15 Other

A 1024-Element Scalable Optical Phased Array in 0.18µm SOI CMOS

SungWon Chung, Hooman Abediasl, Hossein Hashemi

Self-driving cars, drones, and other autonomous systems rely on a number of sensors such as cameras, radars, and ultrasonic detectors to observe their surrounding environments. Light detection and ranging (lidar), where

University of Southern California, Los Angeles, CA

ISSCC 2017 Session 15 Other

An a-IGZO Asynchronous Delta-Sigma Modulator on Foil Achieving up to 43dB SNR and 40dB SNDR in 300Hz Bandwidth 3.4kHz and increases robustness against batch to batch variations. At the comparator output a source follower drives the current DAC. This is composed of a current source and four switches, implemented as double gate TFTs with gate and TG connected together.

Carmine Garripoli1, Jan-Laurens P. J. van der Steen2, Edsger Smits2,

Gerwin H. Gelinck2, Arthur H. M. Van Roermund1, Eugenio Cantatore1 Figure 15.3.3 shows the measured ADSM output spectrum for a 100Hz IIN with -7dBFS amplitude: the fundamental, the limit cycle fundamental at 2kHz and its

ISSCC 2017 Session 15 Other

A Flexible ISO14443-A Compliant 7.5mW 128b Metal-Oxide NFC Barcode Tag with Direct Clock Division Circuit from 13.56MHz Carrier

Kris Myny1, Yi-Cheng Lai2, Nikolaos Papadopoulos1, Florian De Roose1,3,

Marc Ameys1, Myriam Willegems1, Steve Smout1, Soeren Steudel1, Wim Dehaene1,3, Jan Genoe1,3 imec, Heverlee, Belgium AU Optronics, Hsinchu, Taiwan 3 KU Leuven, Leuven, Belgium 1 2 Flexible low-cost RFID/NFC tags have grea

ISSCC 2017 Session 15 Other

Large-Scale Acquisition of Large-Area Sensors Using an Array of Frequency-Hopping ZnO Thin-Film-Transistor Oscillators

Yasmin Afsar, Tiffany Moy, Nicholas Brady, Sigurd Wagner,

James C. Sturm, Naveen Verma Princeton University, Princeton, NJ Hybrid systems combine Large-Area Electronics (LAE) and silicon CMOS ICs for sensing and computation, respectively. Such systems are limited in number of s

ISSCC 2017 Session 14 Digital Processors

A 135mW Fully Integrated Data Processor for Next-Generation Sequencing

Yi-Chung Wu1, Jui-Hung Hung2, Chia-Hsiang Yang1,2

National Chiao Tung University, Hsinchu, Taiwan 1 2 DNA sequencing is the process of determining the precise order of nucleotides (A, C, G, T) within a DNA molecule and is now indispensable for genetics and medical resea

National Taiwan University, Taipei, Taiwan

ISSCC 2017 Session 14 Digital Processors

A 288μW Programmable Deep-Learning Processor with 270KB On-Chip Weight Storage Using Non-Uniform Memory Hierarchy for Mobile Intelligence

Suyoung Bang1, Jingcheng Wang1, Ziyun Li1, Cao Gao1, Yejoong Kim1,2,

Qing Dong1, Yen-Po Chen1, Laura Fick1, Xun Sun1, Ron Dreslinski1, Trevor Mudge1, Hun Seok Kim1, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI CubeWorks, Ann Arbor, MI 1 2 Deep learning has proven

ISSCC 2017 Session 14 Digital Processors

A 0.62mW Ultra-Low-Power Convolutional-NeuralNetwork Face-Recognition Processor and a CIS Integrated with Always-On Haar-Like Face Detector

Kyeongryeol Bong, Sungpill Choi, Changhyeon Kim, Sanghoon Kang,

for the next-generation UI/UX of wearable devices. A FR system, shown in Fig. 14.6.1, was developed as a life-cycle analyzer or a personal black box, constantly recording the people we meet, along with time and place inf

Youchang Kim, Hoi-Jun Yoo KAIST, Daejeon, Korea Recently, face recogni

ISSCC 2017 Session 14 AI / ML

ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI

Bert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst

ConvNets, or Convolutional Neural Networks (CNN), are state-of-the-art classification algorithms, achieving near-human performance in visual recognition

KU Leuven, Leuven, Belgium

ISSCC 2017 Session 14 Digital Processors

A Scalable Speech Recognizer with Deep-NeuralNetwork Acoustic Models and Voice-Activated Power Gating

Michael Price1,2, James Glass1, Anantha P. Chandrakasan1

Analog Devices, Cambridge, MA 1 Previous work such as [4] provided micropower VADs that can be used in quiet environments or in applications that tolerate false alarms. In our application, false alarms will unnecessarily

Massachusetts Institute of Technology, Cambridge, MA

ISSCC 2017 Session 14 Digital Processors

A 28nm SoC with a 1.2GHz 568nJ/Prediction Sparse Deep-Neural-Network Engine with >0.1 Timing Error Rate Tolerance for IoT Applications

Paul N. Whatmough, Sae Kyu Lee, Hyunkwang Lee, Saketh Rama,

(IoT) devices with the capability to interpret the complex, noisy real-world data arising from sensorrich systems. Achieving sufficient energy efficiency to execute ML workloads on an edge-device necessitates specialized

David Brooks, Gu-Yeon Wei Harvard University, Cambridge, MA Machine Le

ISSCC 2017 Session 14 AI / ML

DNPU: An 8.1TOPS/W Reconfigurable CNN-RNN Processor for General-Purpose Deep Neural Networks

Dongjoo Shin, Jinmook Lee, Jinsu Lee, Hoi-Jun Yoo

Recently, deep learning with convolutional neural networks (CNNs) and recurrent neural networks (RNNs) has become universal in all-around applications. CNNs are used to support vision recognition and processing, and RNNs

KAIST, Daejeon, Korea

ISSCC 2017 Session 14 AI / ML

A 2.9TOPS/W Deep Convolutional Neural Network SoC in FD-SOI 28nm for Intelligent Embedded Systems

Giuseppe Desoli1, Nitin Chawla2, Thomas Boesch3, Surinder-pal Singh2,

Elio Guidetti1, Fabio De Ambroggi4, Tommaso Majo1, Paolo Zambotti4, Manuj Ayodhyawasi2, Harvinder Singh2, Nalin Aggarwal2 STMicroelectronics, Cornaredo, Italy STMicroelectronics, Greater Noida, India 3 STMicroelectronics