ISSCC 2017
Session 12
Memory
Gsearch/s 2Mb/mm2 TCAM Using Two-PhasePrecharge ML Sensing and Power-Grid PreConditioning to Reduce Ldi/dt Power-Supply Noise by 50%
Van Butler1,2, Raymond Kim3, Ramon Rodriguez1, Tom Maffitt4, Joseph J. Oler1, John Goss1, Christopher Parkinson5,6, Michael A. Ziegerhofer1, Steven Burns1 Globalfoundries, Essex Junction, VT Green Mountain Semiconductor,
ISSCC 2017
Session 12
Memory
A Low-Power and High-Performance 10nm SRAM Architecture for Mobile Applications
Johnny Yang2, Hau-Tai Hsieh2, Frank Wu2, Jung-Ping Yang2, Atul Katoch3, Arun Achyuthan3, Donald Mikan1, Bryan Sheffield1, Jonathan Chang2 TSMC Design Technology, Austin, TX TSMC Design Technology, Hsinchu, Taiwan 3 TSMC
ISSCC 2017
Session 12
Memory
A 7nm FinFET SRAM Macro Using EUV Lithography for Peripheral Repair Analysis
Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Ch
ISSCC 2017
Session 12
Memory
A 7nm 256Mb SRAM in High-K Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications
Hank Cheng1, Hidehiro Fujiwara1, Jih-Yu Lin1, Kao-Cheng Lin1, John Hung1, Robin Lee1, Hung-Jen Liao1, Jhon-Jhy Liaw2, Quincy Li2, Chih-Yung Lin2, Mu-Chi Chiang2, Shien-Yang Wu2 TSMC Design Technology, Hsinchu, Taiwan TSM
ISSCC 2017
Session 11
Memory
A 512Gb 3b/cell 64-Stacked WL 3D V-NAND Flash Memory
Doo-Hyun Kim, Daewoon Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-lo Ahn, Jiyoung Lee, Jong-hoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jonghoo
ISSCC 2017
Session 11
Memory
A 10nm 32Kb Low-Voltage Logic-Compatible Anti-Fuse One-Time-Programmable Memory with Anti-Tampering Sensing Scheme
breakdown as a programming scheme is fabricated and characterized. The antifuse OTP bitcell is composed of an NMOS as antifuse element and as a select transistor. Characterization shows that this solution is a viable tec
ISSCC 2017
Session 11
Memory
A 1Mb Embedded NOR Flash Memory with 39μW Program Power for mm-Scale High-Temperature Sensor Nodes
Jingcheng Wang1, Kaiyuan Yang1, Yen-Po Chen1, Junjie Dong1, Minchang Cho1, Gyouho Kim1, Wei-Keng Chang2, Yun-Sheng Chen2, Yu-Der Chih2, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI TSMC, Hsinchu
ISSCC 2017
Session 11
Memory
A 512Gb 3b/Cell Flash Memory on 64-Word-LineLayer BiCS Technology
Toshio Yamamura2, Hiroyuki Mizukoshi1, Shingo Zaitsu1, Minoru Yamashita1, Shunichi Toyama1, Norihiro Kamae1, Juan Lee1, Shuo Chen1, Jiawei Tao1, William Mak1, Xiaohua Zhang1, Ying Yu1, Yuko Utsunomiya2, Yosuke Kato1, Man
ISSCC 2017
Session 10
Power Management
A 25MHz 4-Phase SAW Hysteretic DC-DC Converter with 1-Cycle APC Achieving 190ns tsettle to 4A Load Transient and Above 80% Efficiency in 96.7% of the Power Range
Switching power converters with fast load transients are crucial for application processors (APs) to facilitate system-level power adaptability with high current slew rate. While current-mode hysteretic control has been
ISSCC 2017
Session 10
Power Management
A 30MHz Hybrid Buck Converter with 36mV Droop and 125ns 1% Settling Time for a 1.25A/2ns Load Transient
Fast load-transient responses are crucial for DC-DC converters to cope with the demands of modern highly integrated system-on-chip (SoC) designs. Various techniques have been proposed to improve transient responses by en
ISSCC 2017
Session 10
Power Management
A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage in such devices, stacked MOSFET structures with a three-level technology are commonly employed. The stacked structure can
ISSCC 2017
Session 10
Power Management
A Hybrid Inductor-Based Flying-Capacitor-Assisted Step-Up/Step-Down DC-DC Converter with 96.56% Efficiency
Each mobile device is usually equipped with a Li-ion battery having voltage that varies from a minimum of 2.7V to a maximum of 4.2V. Therefore, as the battery voltage decreases with time, a DC-DC converter is required fo
ISSCC 2017
Session 10
Power Management
A 94.2%-Peak-Efficiency 1.53A Direct-Battery-HookUp Hybrid Dickson Switched-Capacitor DC-DC Converter with Wide Continuous Conversion Ratio in 65nm CMOS
University of Illinois, Urbana, IL Owing to the need for low power consumption, portable and wearable electronics operate at low voltages, typically below 1V, with recent designs in near- and subthreshold operation resul
ISSCC 2017
Session 10
Power Management
A Digitally Controlled 94.8%-Peak-Efficiency Hybrid Switched-Capacitor Converter for Bidirectional Balancing and Impedance-Based Diagnostics of Lithium-Ion Battery Arrays
Intel, Hillsboro, OR 3 Hive Battery, Seattle, WA 1 2 With the growing adoption of electrified transportation and need for active storage in the electrical grid, electrochemical energy storage has become increasingly impo
ISSCC 2017
Session 10
Power Management
A 1.1W/mm2-Power-Density 82%-Efficiency Fully Integrated 3:1 Switched-Capacitor DC-DC Converter in Baseline 28nm CMOS Using Stage Outphasing and Multiphase Soft-Charging
Over the past years, delivering power to integrated circuits has become increasingly difficult. With the current intake of many modern-day applications growing each new process generation, the Power Delivery Network (PDN
ISSCC 2017
Session 1
Plenary
Quantum Computing – The Next Challenge in Circuit and System Design Lieven Vandersypen
1. Overview Quantum computers have the potential to tackle problems in materials science, chemistry, and mathematics that are well beyond the reach of supercomputers. Their power derives from the use of quantum bits, whi
ISSCC 2017
Session 1
Plenary
February 6, 2017 / 10:45 AM The Development of High-Speed DNA Sequencing:
that biological information was encoded in DNA as a sequence of chemical building-block “letters”, developing technology for reading (or “sequencing”) this chemical code has been fundamental to advances in biology and me
ISSCC 2017
Session 1
Plenary
Dynamics of Exponentials in Circuits and Systems
1.1 Introduction Scaling of CMOS, the technology that has driven our industry for 45 years and prompted unprecedented innovations in device, circuit, and manufacturing, is coming to an end. There is no unanimous agreemen
ISSCC 2017
Session 1
Plenary
A Smart Design Paradigm for Smart Chips Cliff Hou
Industry application trends have seen important usage-model shifts from the PC era to the mobile-computing era, where individuals have moved from possessing one device to multiple devices that connect them to people [1].
ISSCC 2016
Session 9
Wireless
Receiver with Integrated Magnetic-Free N-Path-Filter-Based Non-Reciprocal Circulator and Baseband Self-Interference Cancellation for Full-Duplex Wireless
Full-duplex (FD) is an emergent wireless communication paradigm where the transmitter (TX) and the receiver (RX) operate at the same time and at the same frequency. The fundamental challenge with FD is the tremendous amo
ISSCC 2016
Session 9
Wireless
A Self-Calibrated 10Mb/s Phase Modulator
-246.6dB-FOM, Fractional-N Subsampling PLL Nereo Markulic1,2, Kuba Raczkowski1, Ewout Martens1, Pedro Emiliano Paro Filho1,2, Benjamin Hershberg1, Piet Wambacq1,2, Jan Craninckx1 imec, Leuven, Belgium, Vrije Universiteit
ISSCC 2016
Session 9
Wireless
A Dual-Band Digital-WiFi 802.11a/b/g/n Transmitter SoC with Digital I/Q Combining and Diamond Profile Mapping for Compact Die Area and Improved Efficiency in 40nm CMOS
Dimitris Papadopoulos1, Bryan Huang1, Ray Chen1, Hua Wang1, WH Hsu2, CH Wu2, Osama Shanaa1 MediaTek, San Jose, CA, MediaTek, Hsinchu, Taiwan 1 2 Digital transmitters (DTX) have gained interest in the past few years becau
ISSCC 2016
Session 9
Wireless
A 2×2 WLAN and Bluetooth Combo SoC in 28nm CMOS with On-Chip WLAN Digital Power
Renaldi Winoto1, Ashkan Olyaei1, Mohammad Hajirostam1, Wai Lau1, Xiang Gao1, Arnab Mitra1, Ovidiu Carnu1, Philip Godoy1, Luns Tee1, Hao Li1, Erdem Erdogan1, Alden Wong1, Qiang Zhu1, Timothy Loo1, Fan Zhang1, Liwei Sheng1
ISSCC 2016
Session 9
Wireless
A Very-Low-Noise Frequency-Translational Quadrature-Hybrid Receiver for Carrier Aggregation
To meet the demands of ever-increasing data throughput, carrier aggregation (CA) across frequency bands is becoming necessary. Different regional spectrum allocations lead to a large number of band combinations and chall
ISSCC 2016
Session 9
Wireless
A Scalable 0.1-to-1.7GHz Spatio-SpectralFiltering 4-Element MIMO Receiver Array with Spatial Notch Suppression Enabling Digital Beamforming
Oregon State University, Corvallis, OR 1 2 Multiple-antenna receivers offer numerous advantages over single-antenna receivers, including sensitivity improvement, ability to reject interferers spatially and enhancement of
ISSCC 2016
Session 9
Wireless
A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO Base-Station Transceiver SoC with 200MHz RF Bandwidth
S. Uppathil1, S. Kaylor1, A. Akour1, V. Wang1, M. Fares1, F. Dulger1, A. Frank1, D. Ghosh1, S. Madhavapeddi1, H. Safiri1, J. Mehta1, A. Jain1, H. Choo1, E. Zhang1, C. Sestok1, C. Fernando1, Rajagopal K.A. 2, S. Ramakrish
ISSCC 2016
Session 8
Digital Circuits
iRazor: 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R4 Processor
M. Alioto2, D. Blaauw1, D. Sylvester1 University of Michigan, Ann Arbor, MI, National University of Singapore, Singapore, Singapore 1 2 It is well known that technology scaling has led to increasing process/voltage/tempe
ISSCC 2016
Session 8
Digital Circuits
Physically Unclonable Function for Secure Key Generation with a Key Error Rate of 2E-38 in 45nm Smart-Card Chips
keys or chip IDs based on intrinsic properties of each chip itself [1-2]. PUFs are a step forward to improve the security level compared to traditional NVM (nonvolatile memory) solutions (FUSEs, EEPROM/FLASH, etc.) becau
ISSCC 2016
Session 8
Digital Circuits
A 6.5-to-23.3fJ/b/mm Balanced ChargeRecycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
Stephen G. Tell1, Thomas H. Greer III1, C. Thomas Gray1, William J. Dally2 Nvidia, Durham, NC, 2Nvidia, Santa Clara, CA 1 Signaling over chip-scale global interconnect is consuming a larger fraction of total power in lar
ISSCC 2016
Session 8
Digital Circuits
A 60%-Efficiency 20nW-500μW Tri-Output Fully Integrated Power Management Unit with Environmental Adaptation and Load-Proportional Biasing for IoT Systems
Seokhyeon Jeong1, Kaiyuan Yang1, Myungjoon Choi1, ZhiYoong Foo1, Suyoung Bang1, Sechang Oh1, Dennis Sylvester1, David Blaauw1 University of Michigan, Ann Arbor, MI, 2Korea University, Seoul, Korea 1 As Internet-of-Things
ISSCC 2016
Session 8
Digital Circuits
Post-Silicon Voltage-Guard-Band Reduction in a 22nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
circuits to lower intrinsic VMIN, retention flops to reduce leakage power during stall periods, and a fully integrated hybrid digital LDO/SCVR regulator to provide a cost-effective means to realize autonomous DVFS under
ISSCC 2016
Session 8
Digital Circuits
A 200mA Digital Low-Drop-Out Regulator with Coarse-Fine Dual Loop in Mobile Application Processors
Tae-Hwang Kong2, Dae-Yong Kim2, Kwang-Ho Kim2, Sang-Ho Kim2, Jae-Jin Park2, Ho-Jin Park2, Gyu-Hyeong Cho1 KAIST, Daejeon, Korea, Samsung Electronics, Hwaseong, Korea 1 2 A modern mobile application processor (AP) require
ISSCC 2016
Session 8
Digital Circuits
Fully Integrated Low-Drop-Out Regulator Based on Event-Driven PI Control
Modern SoC designs employ a number of power domains, many of which are often implemented by low-drop-out (LDO) regulators. The key overhead of the existing LDO design is the large off-chip output capacitor (Cout) for com
ISSCC 2016
Session 8
Digital Circuits
A 4×4×2 Homogeneous Scalable 3D Network-on-Chip Circuit with 326MFlit/s 0.66pJ/b Robust and Fault-Tolerant Asynchronous 3D Links
Christian Bernard1, Florian Darve1, Didier Lattard1, Ivan Miro-Panades1, Cristiano Santos1, Fabien Clermidy1, Severine Cheramy1, Frederic Petrot2, Eric Flamand3, Jean Michailos4 CEA-LETI-MINATEC, Grenoble, France, Tima L
ISSCC 2016
Session 7
Memory
A 768Gb 3b/cell 3D-Floating-Gate NAND Flash Memory
Koichi Kawai1, Jae-Kwan Park2, Shigekazu Yamada1, Feng Pan2, Yuichi Einaga1, Ali Ghalam2, Toru Tanzawa1, Jason Guo2, Takaaki Ichikawa1, Erwin Yu2, Satoru Tamada1, Tetsuji Manabe1, Jiro Kishimoto1, Yoko Oikawa1, Yasuhiro
ISSCC 2016
Session 7
Memory
A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175°C
Takashi Hashimoto2, Hideaki Yamakoshi2, Shinichiro Abe2, Takashi Kono1, Yasuhiko Taito1, Takashi Ito1, Takashi Krafuji1, Kenji Noguchi1, Hideto Hidaka1, Tadaaki Yamauchi1 Renesas Electronics, Kodaira, Japan, Renesas Elec
ISSCC 2016
Session 7
Memory
A 128Gb 2b/cell NAND Flash Memory in 14nm Technology with tPROG=640μs and 800MB/s I/O Rate
Sung-won Yun, Min-su Kim, Jong-hoon Lee, Minseok Kim, Kangbin Lee, Taeeun Kim, Byungkyu Cho, Dooho Cho, Sangbum Yun, Jung-no Im, Hyejin Yim, Kyung-hwa Kang, Suchang Jeon, Sungkyu Jo, Yang-lo Ahn, Sung-Min Joe, Suyong Kim
ISSCC 2016
Session 7
Memory
A 256b-Wordlength ReRAM-based TCAM with 1ns Search-Time and 14× Improvement in WordLength-EnergyEfficiency-Density Product using 2.5T1R cell
Yen-Ning Chiang1, Hsiang-Jen Tsai3, Geng-Hau Yang3, Ya-Chin King1, Chrong Jung Lin1, Tien-Fu Chen3, Meng-Fan Chang1 National Tsing Hua University, Hsinchu, Taiwan, TSMC, Hsinchu, Taiwan, 3 National Chiao Tung University,
ISSCC 2016
Session 7
Memory
A Resistance-Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage-Class Memory Applications
Tzu-Hsiang Su1,3, Keng-Hao Yang3, Tien-Fu Chen3, Tien-Yen Wang1, Hsiang-Pang Li1, Matthew BrightSky4, SangBum Kim4, Hsiang-Lam Lung1, Chung Lam4 Macronix International, Hsinchu, Taiwan, National Tsing Hua University, Hsi
ISSCC 2016
Session 7
Memory
4Mb STT-MRAM-Based Cache with MemoryAccess-Aware Power Optimization and WriteVerify-Write / Read-Modify-Write Scheme
Keiichi Kushida1, Atsushi Kawasumi1, Hiroyuki Hara1, Keiko Abe1, Naoharu Shimomura1, Junichi Ito1, Shinobu Fujita1, Takashi Nakada2, Hiroshi Nakamura2 Toshiba, Kawasaki, Japan, University of Tokyo, Tokyo, Japan 1 2 Two p
ISSCC 2016
Session 7
Memory
256Gb 3b/Cell V-NAND Flash Memory with 48 Stacked WL Layers
Yong Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Jeong-Don Ihm, Doogon Kim, Young-Sun Min, Moo-Sung Kim, An-Soo Park, Jae-Ick Son, I
ISSCC 2016
Session 6
Image Sensors
A 1.1µm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analogto-Digital Converters
Hiroshi Shimamoto1, Tomohiko Kosugi2, Sungwook Jun2, Satoshi Aoyama2, Ming-Chieh Hsu3, Yuichiro Yamashita3, Hirofumi Sumi3, Shoji Kawahito2,4 NHK Science & Technology Research Laboratories, Tokyo, Japan, Brookman Technol
ISSCC 2016
Session 6
Image Sensors
A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias
image sensors. In addition, 3D stacking separates pixel array and peripheral circuits. As such, computational imaging blocks (stereo vision, array camera, reconfigurable instruction cell array, etc.) can integrate with s
ISSCC 2016
Session 6
Image Sensors
A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA
2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a
ISSCC 2016
Session 6
Image Sensors
A 1280×720 Single-Photon-Detecting Image Sensor with 100dB Dynamic Range Using a Sensitivity-Boosting Technique
sensors such as camcorders, digital still cameras, mobile phones, and surveillance cameras. Even though leading-edge image sensors have reached the noise floor of a few electrons [1,2], a thrust towards darker levels sti
ISSCC 2016
Session 6
Image Sensors
A 64×64-Pixel Digital Silicon Photomultiplier Direct ToF Sensor with 100MPhotons/s/pixel Background Rejection and Imaging/Altimeter Mode with 0.14% Precision up to 6km for Spacecraft Navigation and Landing
Recent technology surveys identified flash light detection and ranging technology as the best choice for the navigation and landing of spacecrafts in extraplanetary missions, working from single-point altimeter to range-
ISSCC 2016
Session 6
Image Sensors
An APS-H-Size 250Mpixel CMOS Image Sensor Using Column Single-Slope ADCs with Dual-Gain Amplifiers
Daisuke Yoshida, Yasushi Matsuno, Masanobu Ohmura, Hidekazu Takahashi, Katsuhito Sakurai, Takeshi Ichikawa, Hiroshi Yuzurihara, Shunsuke Inoue Canon, Kawasaki, Japan Recently, there has been strong demand for high-resolu
ISSCC 2016
Session 6
Image Sensors
105×65mm2 391Mpixel CMOS Image Sensor with >78dB Dynamic Range for Airborne Mapping Applications
Bart Ceulemans, Guy Meynants, Navid Sarhangnejad, Gavril Arsinte, Victor Statescu, Sonja van der Groen CMOSIS NV, Antwerp, Belgium In today’s airborne mapping applications, there is a strong push towards higher-resolutio
ISSCC 2016
Session 6
Image Sensors
210ke- Saturation Signal 3µm-Pixel VariableSensitivity Global-Shutter Organic Photoconductive Image Sensor for Motion Capture
in-vehicle cameras, and surveillance cameras require a global shutter (GS) function. GS functions are an increasingly powerful technology driver, not only for solving imaging problems caused by rolling shutter distortion
ISSCC 2016
Session 6
Image Sensors
An Over 120dB Simultaneous-Capture WideDynamic-Range 1.6e- Ultra-Low-Reset-Noise Organic-Photoconductive-Film CMOS Image Sensor
Masaaki Yanagida, Tokuhiko Tamaki, Masayuki Takase, Hidenari Kanehara, Masashi Murakami, Yasunori Inoue Panasonic, Moriguchi, Japan Image sensors are increasingly becoming key devices for various applications (in-vehicle