ISSCC 2016
Session 5
Analog Circuits
A 24MHz Crystal Oscillator with Robust Fast Start-Up Using Dithered Injection
Wireless nodes in Internet-of-Everything (IoE) applications achieve low power consumption by operating the radio at very low duty cycles. The wireless node spends most of its time in sleep, waking only occasionally to tr
ISSCC 2016
Session 5
Analog Circuits
A 4.7nW 13.8ppm/°C Self-Biased Wakeup Timer Using a Switched-Resistor Scheme
under restricted battery capacity due to their size [1]. Due to low duty cycles in many sensing applications, sleep-mode power can dominate the total energy budget. Wakeup timers are a key always-on component in such sle
ISSCC 2016
Session 5
Analog Circuits
A 39.25MHz 278dB-FOM 19µW LDO-Free Stacked-Amplifier Crystal Oscillator (SAXO) Operating at I/O Voltage
frequency of 12Hz. The active resistor of 27MΩ with a size of 1800μm2 is achieved with a multiplication of RBIAS (= 80kΩ) by (W/L)M1 / (W/L)M3. 500pF is achieved with a multiplication of CLPF (= 50pF) by the gain (≈ 10)
ISSCC 2016
Session 5
Analog Circuits
A 420μW 100GHz-GBW CMOS ProgrammableGain Amplifier Leveraging the Cross-Coupled Pair Regeneration
Cross-coupled pairs are certainly among the most widely adopted fundamental circuits still in use today. This elegant device arrangement yields broadband positive feedback with high gain and low power, desirable features
ISSCC 2016
Session 5
Analog Circuits
A 2µW 40mVpp Linear-Input-Range ChopperStabilized Bio-Signal Amplifier with Boosted Input Impedance of 300MΩ and Electrode-Offset Filtering
Modern neuromodulation requires closed-loop functionality, where neural recordings are used to adapt stimulation patterns in real time. A closed-loop system requires the neural sensing front-end to record small neural si
ISSCC 2016
Session 5
Analog Circuits
A Sub-μW 36nV/√Hz Chopper Amplifier for Sensors Using a Noise-Efficient Inverter-Based 0.2V-Supply Input Stage
In low-bandwidth, low-noise applications of wireless sensor nodes, the sensor front-end amplifier presents a power-consumption bottleneck since its current draw is noise-limited and cannot be scaled with the low data-rat
ISSCC 2016
Session 5
Analog Circuits
A 2×70W Monolithic Five-Level Class-D Audio Power Amplifier
Thomas Holm Hansen1, Allan Nogueras Nielsen1,2, Hans Hasselby-Andersen1 Merus Audio, Herlev, Denmark, Now at Knowles Corporation, Roskilde, Denmark 1 2 The consumer electronics trends of miniaturization and portability h
ISSCC 2016
Session 5
Analog Circuits
A 118dB-PSRR 0.00067%(-103.5dB) THD+N and 3.1W Fully Differential Class-D Audio Amplifier with PWM Common-Mode Control
A high power-supply rejection ratio (PSRR) and high-linearity Class-D audio amplifier (CDA) becomes important as the CDA is directly connected to a battery supply for efficiency considerations in mobile phone application
ISSCC 2016
Session 5
Analog Circuits
A 1.4V 10.5MHz Swing-Boosted Differential Relaxation Oscillator with 162.1dBc/Hz FOM and 9.86psrms Period Jitter in 0.18μm CMOS
Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea, 3 Nanyang Technological University, Singapore, Singapore 1 2 Relaxation oscillators have a profound scope as on-chip reference clock sources or sensor fr
ISSCC 2016
Session 5
Analog Circuits
A 10MHz-Bandwidth 4µs-Large-Signal-Settling 6.5nV/√Hz-Noise 2µV-Offset Chopper Operational Amplifier
Low-offset and low-noise operational amplifiers (OpAmps) are essential for precision measurement systems. Applications such as precision weigh scales, sensor front-ends, bridge transducers, interfaces for thermocouple se
ISSCC 2016
Session 4
Digital Processors
A 65nm ReRAM-Enabled Nonvolatile Processor with 6× Reduction in Restore Time and 4× Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logic
Zhe Yuan1, Chien-Chen Lin2, Qi Wei1, Yu Wang1, Ya-Chin King2, Chrong-Jung Lin2, Pedram Khalili3, Kang-Lung Wang3, Meng-Fan Chang2, Huazhong Yang1 Tsinghua University, Beijing, China, National Tsing Hua University, Hsinch
ISSCC 2016
Session 4
Digital Processors
A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster
many application areas, such as IoT and wearables. While for some applications, integer and fixed-point processor instructions suffice, others (e.g. simultaneous localization and mapping – SLAM, stereo vision, nonlinear
ISSCC 2016
Session 4
Digital Processors
A 16nm FinFET Heterogeneous Nona-Core SoC Complying with ISO26262 ASIL-B: Achieving 10-7 Random Hardware Failures per Hour Reliability
car information systems (commonly referred to as car infotainment) is expanding from dedicated navigation systems to joint car-cockpit systems, including the dashboard meter, telematics for the internet/cloud, and advanc
ISSCC 2016
Session 4
Digital Processors
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC for Car Information Systems
Chi Lan Phuong Nguyen2, Tetsuya Shibayama1, Kenichi Iwata1, Katsuya Mizumoto1, Takahiro Irita3, Hirotaka Hara3, Toshihiro Hattori1 Renesas System Design, Tokyo, Japan, Renesas Design Vietnam, Ho Chi Minh City, Vietnam, 3
ISSCC 2016
Session 4
Digital Processors
A 20nm 2.5GHz Ultra-Low-Power Tri-Cluster CPU Subsystem with Adaptive Power Allocation for Optimal Mobile SoC Performance
C.J. Chung1, Sumanth Gururajarao1, Ping Kao2, Anand Rajagopalan1, Anirban Saha3, Amit Jain4, Ericbill Wang2, Shichin Ouyang5, Huajun Wen1, Achuta Thippana1, HsinChen Chen1, Syed Rahman1, Minh Chau1, Anshul Varma1, Brian
ISSCC 2016
Session 4
Digital Processors
Increasing the Performance of a 28nm x86-64 Microprocessor Through System Power Management
Ravinder Rachala1, Sriram Sambamurthy1, Steven Liepe2, Miguel Rodriguez2, Tom Burd3, Adam Clark4, Michael Austin1, Samuel Naffziger2 AMD, Austin, TX, AMD, Fort Collins, CO, 3 AMD, Sunnyvale, CA, 4 AMD, Markham, ON, Canad
ISSCC 2016
Session 4
Digital Processors
14nm 6th-Generation Core Processor SoC with Low Power Consumption and Improved Performance
Muhammad Abozaed, Yair Talker, Ziv Shmuely, Saher Abu Rahme transitions in the victim neighborhood circuits should not exceed a crosstalk limit during normal operation. Another parameter that must be factored is reliabil
ISSCC 2016
Session 3
Wireline I/O
A 40-to-64Gb/s NRZ Transmitter with SupplyRegulated Front-End in 16nm FinFET
Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang Xilinx, San Jose, CA Due to increasing bandwidth demand in data centers and telecommunication infrastructures, the maximum data-rate of wireline transceivers i
ISSCC 2016
Session 3
Wireline I/O
A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
electrical link technology to support 400Gb/s standards is underway [1-5]. Physical constraints paired to the small area available to dissipate heat, impose limits to the maximum number of serial interfaces and therefore
ISSCC 2016
Session 3
Wireline I/O
A 56Gb/s NRZ-Electrical 247mW/lane Serial-Link Transceiver in 28nm CMOS
Yasufumi Sakai1, Hiroki Miyaoka2, Futoshi Terasawa2, Masahiro Kudo2, Hideki Kano2, Atsushi Matsuda2, Shigeaki Kawai2, Tomoyuki Arai2, Hirohito Higashi2, Naoaki Naka2, Hisakatsu Yamaguchi1, Toshihiko Mori1, Yoichi Koyanag
ISSCC 2016
Session 3
Wireline I/O
A 40/50/100Gb/s PAM-4 Ethernet Transceiver in 28nm CMOS
Arun Tiruvur1, Belal Helal1, Chang-Feng Loi2, Chris Jiang1, Halil Cirit1, Irene Quek2, Jamal Riani1, James Gorecki1, Jennifer Wu1, Jorge Pernillo1, Lawrence Tse1, Michael Le3, Mohammad Ranjbar1, Pui-Shan Wong1, Pulkit Kh
ISSCC 2016
Session 3
Wireline I/O
A 25Gb/s Multistandard Serial Link Transceiver for 50dB-Loss Copper Cable in 28nm CMOS
Naohiro Kohmu1, Fumio Yuki1, Norio Nakajima2, Takashi Muto2, Junya Nasu2, Takemasa Komori2, Hideki Koba2, Tatsunori Usugi2, Tomofumi Hokari2, Tsuneo Kawamata2, Yuichi Ito2, Seiichi Umai2, Masatoshi Tsuge2, Takeo Yamashit
ISSCC 2016
Session 3
Wireline I/O
A 320mW 32Gb/s 8b ADC-Based PAM-4 Analog Front-End with Programmable Gain Control and Analog Peaking in 28nm CMOS
introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance fo
ISSCC 2016
Session 3
Wireline I/O
A 25Gb/s ADC-Based Serial Line Receiver in 32nm CMOS SOI
Thomas Toifl2, Yong Liu3, Ankur Agrawal1, Peter Buchmann2, Alexander Rylyakov4, Michael Beakes1, Benjamin Parker1, Mounir Meghelli1 IBM T. J. Watson Reseach Center, Yorktown Heights, NY, IBM Zurich Research Laboratory, R
ISSCC 2016
Session 28
Medical & Bio
CMOS Monolithic Airborne-Particulate-Matter Detector Based on 32 Capacitive Sensors with a Resolution of 65zF rms
matter (PM) is well known [1]. Although optical and gravimetric instruments are available to detect PM, they lack portability, have poor potential for miniaturization, and are not low cost. Instead, a better spatio-tempo
ISSCC 2016
Session 28
Medical & Bio
A ±50mV Linear-Input-Range VCO-Based NeuralRecording Front-End with Digital Nonlinearity Correction
tool for understanding the brain and driving the progress in neuroscience research and therapy. The local field potential (LFP) signals, which span from 3Hz to about 200Hz, serve as indicators of various neurological beh
ISSCC 2016
Session 28
Medical & Bio
A 0.6V 0.015mm2 Time-Based Biomedical Readout for Ambulatory Applications in 40nm CMOS
applications in personal healthcare require sensor SoCs with low area, low power and a high dynamic range. Design in small-scale technologies can reduce the power and area of digital processing. However, due to the accom
ISSCC 2016
Session 28
Medical & Bio
A Battery-Powered Efficient Multi-Sensor
Mario Konijnenburg1, Stefano Stanzione1, Long Yan2, Dong-Woo Jee2, Julia Pettine1, Roland van Wegberg1, Hyejung Kim2, Chris van Liempd1, Ram Fish3, James Schluessler3, Harmke de Groot1, Chris van Hoof1,2, Refet Firat Yaz
ISSCC 2016
Session 28
Medical & Bio
CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water with 120GHz and 60GHz Oscillator Arrays
are reduced to 0.07GHz (resp. 0.03GHz) if we exclude the 52 elements (resp. 44 elements) on the periphery that exhibit larger deviations due to the anisotropy of the layout. A selected 120GHz (resp. 60GHz) element draws
ISSCC 2016
Session 28
Medical & Bio
A 14GHz Battery-Operated Point-of-Care ESR Spectrometer Based on a 0.13µm CMOS ASIC
spatial distribution, and even dynamics of paramagnetic species, electron spin resonance (ESR) spectroscopy is one of the most powerful analytical techniques in modern life sciences. Recently, the method has gained signi
ISSCC 2016
Session 28
Medical & Bio
A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with B-Field Stabilization for Multi-Type Biological/Chemical Assays
Franco Maloberti2, Rui P. Martins1,4 University of Macau, Macau, China, University of Pavia, Pavia, Italy, 3 University of Glasgow, Glasgow, United Kingdom, 4 Instituto Superior Tecnico, Lisbon, Portugal 1 2 Point-of-use
ISSCC 2016
Session 27
Data Converters
A 0.076mm2 12b 26.5mW 600MS/s 4×-Interleaved Subranging SAR-ΔΣ ADC with On-Chip Buffer in 28nm CMOS switch, is parasitic sensitive. Scaling of the LSB capacitance is therefore dictated by the parasitic capacitance of a minimum size switch instead of kT/C noise requirements. In deep-submicron technologies, this usually leads to a significantly larger core area with respect to a CR-DAC.
competitive core area a segmented SAR-DAC architecture is adopted using a CSDAC for the 4 MSBs and a CR-DAC for the remaining 6 LSBs (Fig. 27.8.2). The parasitic insensitive 6 LSBs can be scaled down as in a conventional
ISSCC 2016
Session 27
Data Converters
A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration
Recent radio architectures, such as WiGig and 5G, require ADCs with bandwidth beyond 1GHz and ENOB of 6-to-8b while retaining excellent power efficiency for long battery life. Therefore, many time-interleaved SAR ADCs ar
ISSCC 2016
Session 27
Data Converters
A 4GS/s 13b Pipelined ADC with Capacitor and Amplifier Sharing in 16nm CMOS
Giuseppe Cusmai1, Sha-Ting Lin3, Cheng-Hsun Yang3, Gregory Unruh1, Sunny Raj Dommaraju1, Mo M. Zhang1, Po Tang Yang3, Wei-Ting Lin3, Xi Chen1, Dongsoo Koh1, Qingqi Dou1, H. Mohan Geddada1, Juo-Jung Hung1, Massimo Brandol
ISSCC 2016
Session 27
Data Converters
A 4GS/s Time-Interleaved RF ADC in 65nm CMOS with 4GHz Input Bandwidth
Phillip Elliott2, Bill Foley1, Roy Mason2, Vikas Singh3, Xuejin Wang2 Maxim Integrated Products, North Chelmsford, MA, Maxim Integrated Products, Fort Collins, CO, 3 Maxim Integrated Products, San Jose, CA 1 2 The perfor
ISSCC 2016
Session 27
Data Converters
A 0.35mW 12b 100MS/s SAR-Assisted Digital Slope ADC in 28nm CMOS Chun-Cheng Liu
In recent years, the operation speed of SAR ADCs has improved with the scaling of CMOS technology. SAR ADCs achieve a few hundreds of MS/s with 8-to-10b resolution. The SNR of high-speed SAR ADCs is mainly dominated by c
ISSCC 2016
Session 27
Data Converters
Area-Efficient 1GS/s 6b SAR ADC with ChargeInjection-Cell-Based DAC
To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is
ISSCC 2016
Session 27
Data Converters
An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS
The successive-approximation-register (SAR) architecture is well-known for its high power efficiency in medium-resolution A/D conversions. Together with time interleaving, it can challenge the regime of flash ADCs in hig
ISSCC 2016
Session 27
Data Converters
A 12b 2GS/s Dual-Rate Hybrid DAC with Pulsed Timing-Error Pre-Distortion and In-Band Noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS
A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its
ISSCC 2016
Session 26
Wireless
A 0.038mm2 SAW-less Multiband Transceiver Using an N-Path SC Gain Loop
Instituto Superior Tecnico, Lisbon, Portugal 1 2 N-path filtering has been intensely rekindled as a replacement of costly SAW filters, making possible of multiband blocker-tolerant receivers (RXs) at small area and power
ISSCC 2016
Session 26
Wireless
A 236nW -56.5dBm-Sensitivity Bluetooth Low-Energy Wakeup Receiver with Energy Harvesting in 65nm CMOS
Stuart N. Wooters1, Yousef Shakhsheer1, Benton H. Calhoun1, David D. Wentzloff2 PsiKick, Charlottesville, VA, 2PsiKick, Ann Arbor, MI 1 Batteryless operation and ultra-low-power (ULP) wireless communication will be two k
ISSCC 2016
Session 26
Wireless
A 10mm3 Syringe-Implantable Near-Field Radio System on Glass Substrate
system for ultra-low-power (ULP) healthcare sensor nodes. It is specifically designed for ‘syringe implantation’ which minimizes invasiveness of implantation. Designing a millimeter-scale wireless node for implanted heal
ISSCC 2016
Session 26
Wireless
A Programmable Receiver Front-End Achieving >17dBm IIP3 at <1.25×BW Frequency Offset
University of California, Los Angeles, CA, Silvus Technologies, Los Angeles, CA 1 2 Recent work on highly selective reconfigurable radios has focused on techniques such as DT analog signal processing [1], N-path filterin
ISSCC 2016
Session 26
Wireless
A 0.7V 1.5-to-2.3mW GNSS Receiver with 2.5-to-3.8dB NF in 28nm FD-SOI
Hitoshi Tomiyama1, Hideyuki Takano1, Fumitaka Kondo1, Yusuke Shinohe1, Hidenori Takeuchi1, Nobuhisa Ozawa1, Shingo Harada2, Shinichiro Eto2, Mari Kishikawa3, Daisuke Ide3, Hiroyasu Tagami3, Masayuki Katakura3, Norio Shoj
ISSCC 2016
Session 26
Wireless
A 160-to-960MHz ETSI Class-1-Compliant IoE
Niall Kearney1, Charley Billon1, Michael Deeney1, Eric Evans2, Kalim Khan1, Hongxing Li3, Siwen Liang2, Kenneth Mulvaney1, Keith A. O’Donoghue1, Shane O’Mahony1, Philip Quinlan1, Sivanendra Selvanayagam2, Sudarshan Onkar
ISSCC 2016
Session 26
Wireless
A 1.3nJ/b IEEE 802.11ah Fully Digital Polar Transmitter for IoE Applications
Benjamin Busze, Jordy Gloudemans, Peter Vis, Johan Dijkhuis, Christian Bachmann, Guido Dolmans, Kathleen Philips, Harmke de Groot Holst Centre / imec, Eindhoven, The Netherlands This paper presents an ultra-low-power (UL
ISSCC 2016
Session 26
Wireless
An Ultra-Low-Power Receiver Using TransmittedReference and Shifted Limiters for In-Band Interference Resilience
The coexistence of more and more wireless standards in the ISM bands increases the design difficulty of interference-robust receivers (RX), especially for Wireless Sensor Nodes because of their Ultra-Low-Power (ULP) budge
ISSCC 2016
Session 26
Wireless
A 5.5mW ADPLL-Based Receiver with HybridLoop Interference Rejection for BLE Application in 65nm CMOS
(BLE) have been developed for minimizing the RX power consumption. A PLL-based RX architecture [1] is very attractive to improve the energy efficiency. While the single-channel configuration without multi-bit ADC realize
ISSCC 2016
Session 25
mm-Wave
A 320GHz Subharmonic-Mixing Coherent Imager in 0.13μm SiGe BiCMOS
Crolles, France 1 2 Terahertz imaging has been gaining increasing attention for its emerging applications in security, biomedical and material characterization. Previous works have demonstrated terahertz imagers on silic
ISSCC 2016
Session 25
mm-Wave
A 0.43K-Noise-Equivalent-ΔT 100GHz Dicke-Free Radiometer with 100% Time Efficiency in 65nm CMOS
Jet Propulsion Laboratory, Pasadena, CA 1 2 Silicon based mm-Wave radiometers for sensing, passive imaging, and even biomedical imaging have become an emerging area with many excellent systems demonstrated up to W-band [