ISSCC 2016
Session 25
mm-Wave
A 40-to-330GHz Synthesizer-Free THz Spectroscope-on-Chip Exploiting Electromagnetic Scattering
The terahertz band (0.3 to 3.0THz) has been found to be spectroscopically rich with many substances possessing strong and unique absorption signatures useful for chemical and biomedical sensing applications [1-4]. Photon
ISSCC 2016
Session 25
mm-Wave
A 210-to-305GHz CMOS Receiver for Rotational Spectroscopy
sub-millimeter-wave frequency ranges are used in fast-scan rotational spectroscopy to detect gas molecules and measure their concentrations [1]. This technique can be used for indoor air quality monitoring, detection of
ISSCC 2016
Session 25
mm-Wave
A Fully Integrated 0.55THz Near-Field Sensor with a Lateral Resolution down to 8µm in 0.13µm SiGe BiCMOS
IHP, Frankfurt, Germany 1 2 Silicon technologies have already been employed in state-of-the-art THz imagers. However, their optical resolution was restricted to millimeters by the diffraction limit [1,2], and THz super-r
ISSCC 2016
Session 24
Analog Circuits
A 36.8 2b-TOPS/W Self-Calibrating GPS Accelerator Implemented Using Analog Calculation in 65nm LP CMOS
Dennis Sylvester2, David Blaauw2, David Fick1, Michael B. Henry1 Isocline, Austin, TX, 2University of Michigan, Ann Arbor, MI 1 Many signal processing applications involve manipulating a large amount of data to generate
ISSCC 2016
Session 24
Analog Circuits
A 2.5GHz 7.7TOPS/W Switched-Capacitor Matrix Multiplier with Co-designed Local Memory in 40nm
Matrix multiplication, enabled by multiply-and-accumulate hardware, is ubiquitous in signal processing, computer graphics, machine learning, and optimization. Many important applications with inherent robustness to reduc
ISSCC 2016
Session 24
Analog Circuits
A 0.6V 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired
devices, such as stereo and time-of-flight (ToF) cameras, measure distances to the observed points and generate a depth image where each pixel represents a distance to the corresponding location. The depth image can be c
ISSCC 2016
Session 23
Wireline I/O
A 40Gb/s 14mW CMOS Wireline Receiver
Reaching a power efficiency of 1mW/Gb/s has proven difficult for wireline transceivers operating at tens of gigabits per second. At 40Gb/s, recent receivers consume from 150mW [1] to 1W [2]. This paper describes a receiv
ISSCC 2016
Session 23
Wireline I/O
A 16Gb/s 1 IIR + 1 DT DFE Compensating 28dB Loss with Edge-Based Adaptation Converging in 5μs
I/O receivers routinely equalize ISI over 10 or more post-cursor UI. IIR DFEs are a low-power technique for canceling long post-cursor ISI tails, and have been demonstrated compensating over 20dB loss at fbit/2 up to 10G
ISSCC 2016
Session 23
Wireline I/O
A 30Gb/s 0.8pJ/b 14nm FinFET Receiver Data-Path
Marcel Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl IBM Zurich Research Laboratory, Rüshlikon, Switzerland The demand for energy-efficient I/O link transceive
ISSCC 2016
Session 23
Wireline I/O
A Dual 64Gbaud 10kΩ 5% THD Linear Differential Transimpedance Amplifier with Automatic Gain Control in 0.13μm BiCMOS Technology for Optical Fiber Coherent Receivers
Schwarz, Munich, Germany, 4 Finisar, Berlin, Germany, 5TU Berlin, Berlin, Germany 1 2 Long-haul optical links are experiencing a transition to coherent techniques because they enable the use of modulation techniques with
ISSCC 2016
Session 23
Wireline I/O
A 56Gb/s 300mW Silicon-Photonics Transmitter in 3D-Integrated PIC25G and 55nm BiCMOS Technologies
STMicroelectronics, Pavia, Italy, 2University of Pavia, Pavia, Italy 1 The ever-increasing data center IP traffic, up to 8.6 zettabytes per year by 2018 with nearly 3× growth since 2013 [1], requires power-efficient high
ISSCC 2016
Session 23
Wireline I/O
A 6Gb/s 3-Tap FFE Transmitter and 5-Tap DFE Receiver in 65nm/0.18µm CMOS for NextGeneration 8K Displays
Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong Samsung Semiconductor, San Jose, CA The continuous increase in the resolution, color depth and refresh rate
ISSCC 2016
Session 23
Wireline I/O
A 32Gb/s Bidirectional 4-Channel 4pJ/b Capacitively Coupled Link in 14nm CMOS for Proximity Communication
Proximity communication offers the convenience of a connector-less high-speed interface using energy-efficient mixed-signal transceivers [1-4]. Such interfaces are attractive for ultra-thin handheld/mobile devices with z
ISSCC 2016
Session 23
Wireline I/O
A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b Source Synchronous Transceiver Using DVFS and Rapid On/Off in 65nm CMOS
Seong-Joong Kim, Mrunmay Talegaonkar, Romesh Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu University of Illinois, Urbana-Champaign, IL Dynamic voltage and frequency scaling (DVFS) [1] and burst-mode
ISSCC 2016
Session 22
RF & Wireless
Multi-Functional Microelectrode Array System Featuring 59,760 Electrodes, 2048
Vijay Viswam, Jelena Dragas, Amir Shadmani, Yihui Chen, Alexander Stettler, Jan Müller, Andreas Hierlemann ETH Zurich, Basel, Switzerland Various CMOS-based micro-electrode arrays (MEAs) have been developed in recent yea
ISSCC 2016
Session 22
RF & Wireless
A 966-Electrode Neural Probe with 384 Configurable Channels in 0.13µm SOI CMOS
Bogdan Raducanu1,2, Marco Ballini1, Alexandru Andrei1, Simone Severi1, Marleen Welkenhuysen1, Chris Van Hoof1,2, Silke Musa1, Refet Firat Yazicioglu1 imec, Leuven, Belgium, 2KU Leuven, Heverlee, Belgium 1 In vivo recordi
ISSCC 2016
Session 22
RF & Wireless
A 22V Compliant 56µW Active Charge Balancer Enabling 100% Charge Compensation even in Monophasic and 36% Amplitude Correction in Biphasic Neural Stimulators
Cluster of Excellence, Freiburg, Germany 1 2 Functional electrical stimulation (FES) is a technique that stimulates nerves by electrical charge, but carries the risk of charge accumulation, voltage pile-up, electrode cor
ISSCC 2016
Session 22
RF & Wireless
A 0.5V 55µW 64×2-Channel Binaural Silicon Cochlea for Event-Driven Stereo-Audio Sensing
Event-driven DSPs have the advantage of activity-dependent power consumption
ISSCC 2016
Session 22
RF & Wireless
A 172µW Compressive Sampling Photoplethysmographic Readout with Embedded Direct Heart-Rate and Variability Extraction from Compressively Sampled Data
Long Yan1, Alper Bozkurt3, Chris Van Hoof1,2, Nick Van Helleputte1, Refet Firat Yazicioglu1, Marian Verhelst2 imec, Leuven, Belgium, 2KU Leuven, Leuven, Belgium, North Carolina State University, Raleigh, NC 1 3 Heart rat
ISSCC 2016
Session 22
RF & Wireless
A 141µW Sensor SoC on OLED/OPD Substrate for SpO2/ExG Monitoring Sticker
applications for broader light emission and low fabrication cost. In addition, Organic Photo Detector (OPD) and OLED can be fabricated on the same substrate with the same process and the OLED film itself can be used for
ISSCC 2016
Session 22
RF & Wireless
A 176-Channel 0.5cm3 0.7g Wireless Implant for Motor Function Recovery after Spinal Cord Injury
Brian Kim, Kuanfu Chen, Parag Gad, V. Reggie Edgerton, Wentai Liu University of California, Los Angeles, CA Epidural spinal stimulation has shown effectiveness in recovering the motor function of spinal cord transected r
ISSCC 2016
Session 21
Wireless
A 6.78MHz 6W Wireless Power Receiver with a 3-Level 1× / ½ × / 0× Reconfigurable Resonant Regulating Rectifier
devices to cut the last wire. Resonant wireless power transfer (R-WPT) using magnetic resonance emerges as a promising approach, as it provides spatial freedom and can charge multiple devices simultaneously. ISM-band fre
ISSCC 2016
Session 21
Wireless
A 1.2cm2 2.4GHz Self-Oscillating RectifierAntenna Achieving -34.5dBm Sensitivity for Wirelessly Powered Sensors
Ubiquitous Internet-of-Everything (IoE) applications require low-cost, miniature sensors with long lifetimes. Wirelessly-powered ICs that harvest energy from an RF beacon or from existing wireless signals can address cha
ISSCC 2016
Session 21
Wireless
A Current-Mode Wireless Power Receiver with Optimal Resonant Cycle Tracking for Implantable Systems
to miniature implantable sensor systems such as [1]. To recharge batteries of such systems, wireless power transfer is a popular option since it is non-invasive. However, there are two main challenges: 1) strict safety r
ISSCC 2016
Session 21
Wireless
A >78%-Efficient Light Harvester over 100-to100klux with Reconfigurable PV-Cell Network and MPPT Circuit
extend system lifetime for internet of everything (IoE) nodes. Ambient light is a common energy source that can be harvested by photovoltaic (PV) cells. However, light intensity varies widely depending on location, rangi
ISSCC 2016
Session 21
Wireless
A 200nA Single-Inductor Dual-Input-Triple-Output (DITO) Converter with Two-Stage Charging and Process-Limit Cold-Start Voltage for Photovoltaic and Thermoelectric Energy Harvesting
Analog Devices, Wilmington, MA, 3 Analog Devices, San Jose, CA 1 2 Energy harvesting has been considered to be a good solution to power many IoE applications [1-3]. Some applications require regulated supply voltage, whi
ISSCC 2016
Session 21
Wireless
A 4µW-to-1mW Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting of Periodic and
Improvement Daniel A. Sanchez1, Joachim Leicht1, Eduardas Jodka1, Elham Fazel1, Yiannos Manoli1,2 University of Freiburg - IMTEK, Freiburg, Germany, Hahn-Schickard, Villingen-Schwenningen, Germany 1 2 A piezoelectric ene
ISSCC 2016
Session 21
Wireless
A Single-Cycle MPPT Charge-Pump Energy Harvester Using a Thyristor-Based VCO Without Storage Capacitor
The switched-capacitor power converter, also called a charge pump (CP), features no off-chip components and is suitable for the monolithic smart nodes in the internet of everything (IoE) [1]. To reduce the inevitable cha
ISSCC 2016
Session 20
RF & Wireless
A 1.92mW Filtering Transimpedance Amplifier for RF Current Passive Mixers
Nowadays, current passive mixers represent the state of the art for signal downconversion in wireless receivers. In such kind of structures, noise, distortions and losses are strictly correlated to the performance of the
ISSCC 2016
Session 20
RF & Wireless
A Dual-Frequency 0.7-to-1GHz Balance Network for Electrical Balance Duplexers
seeks to address several key challenges of 4G and 5G mobile systems [1]. The basic principle is shown in Fig. 20.8.1. Duplexer isolation is achieved when the signals in paths 1 and 2 cancel and prevent the TX signal from
ISSCC 2016
Session 20
RF & Wireless
An RF-PA Supply Modulator Achieving 83% Efficiency and -136dBm/Hz Noise for LTE-40MHz and GSM 35dBm Applications
constant supply voltage, has raised interest in enhancing the overall SM-PA efficiency. In the average-powertracking (APT) method, a buck converter simply generates stair-case voltages for a PA according to its required
ISSCC 2016
Session 20
RF & Wireless
A 28GHz Efficient Linear Power Amplifier for 5G Phased Arrays in 28nm Bulk CMOS
driving fifthgeneration (5G) wireless standardization towards the deployment of gigabit-per-second mm-Wave technology by 2020. Paving the road to 5G, 200m coverage in non-line-of-sight (NLOS) urban cells was demonstrated
ISSCC 2016
Session 20
RF & Wireless
A 300GHz Wirelessly Locked 2×3 Array Radiating 5.4dBm with 5.1% DC-to-RF Efficiency in 65nm CMOS
CMOS technology innovations over the last decades opened doors to the possibility of designing fully integrated systems in CMOS at THz frequencies. Small antenna sizes at THz frequencies make CMOS and silicon attractive
ISSCC 2016
Session 20
RF & Wireless
An 86-to-94.3GHz Transmitter with 15.3dBm Output Power and 9.6% Efficiency in 65nm CMOS
Southeast University, Nanjing, China to the TA high gain, the detection inaccuracy of Δt due to the circuit mismatch in PD and CP2 becomes negligibly small. VCCP is designed as a voltage-controlled current source as show
ISSCC 2016
Session 20
RF & Wireless
A Frequency-Reconfigurable mm-Wave Power Amplifier with Active-Impedance Synthesis in an Asymmetrical Non-Isolated Combiner
A frequency-agile mm-Wave power amplifier capable of reconfiguring itself to operate near-optimally over a wide range of tunable frequencies, yet producing output power >22dBm with PAE>20%, is useful for a wide range of
ISSCC 2016
Session 20
RF & Wireless
A 68.1-to-96.4GHz Variable-Gain Low-Noise Amplifier in 28nm CMOS
To allow a maximum theoretical data-rate of 25Gb/s over a 1km distance using 64QAM, an E-Band system should feature a 20dBm-output-power TX and an RX with 10dB maximum noise figure (NF) over two bands of 5GHz from 71 to
ISSCC 2016
Session 20
RF & Wireless
A 300GHz 40nm CMOS Transmitter with 32-QAM 17.5Gb/s/ch Capability over 6 Channels
Shinsuke Hara2, Akifumi Kasamatsu2, Koichi Mizuno3, Kazuaki Takahashi3, Takeshi Yoshida1, Minoru Fujishima1 Hiroshima University, Hiroshima, Japan, National Institute of Information and Communications Technology, Koganei
ISSCC 2016
Session 2
RF & Wireless
A 2GHz 244fs-Resolution 1.2ps-Peak-INL EdgeInterpolator-Based Digital-to-Time Converter in 28nm CMOS
Universität München, Munich, Germany 1 4 Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2
ISSCC 2016
Session 2
RF & Wireless
A Mixed-Mode Injection Frequency-Locked Loop for Self-Calibration of Injection Locking Range and Phase Noise in 0.13μm CMOS
Virginia Tech, Blacksburg, VA Injection-locked oscillators (ILOs) are widely used to realize low-noise carrier sources, particularly at mm-Waves by leveraging harmonic injection, but only within a narrow locking range (Δ
ISSCC 2016
Session 2
RF & Wireless
A 0.003mm2 1.7-to-3.5GHz Dual-Mode TimeInterleaved Ring-VCO Achieving 90-to-150kHz 1/f3 Phase-Noise Corner
Instituto Superior Tecnico, Lisbon, Portugal 1 3 Ring-VCOs (RVCOs) [1] have been avoided for over a decade for highperformance RF systems due to their much lower FOM (<165dB [2]) than that of their LC counterparts from l
ISSCC 2016
Session 2
RF & Wireless
A 190.5GHz Mode-Switching VCO with 20.7% Continuous Tuning Range and Maximum Power of -2.1dBm in 0.13μm BiCMOS
Wideband mm-Wave and terahertz (THz) applications, including high data-rate communications, high-resolution radar and spectroscopy, require wideband signal sources. Nevertheless, low quality factor of varactors and lossy
ISSCC 2016
Session 2
RF & Wireless
A Complementary VCO for IoE that Achieves a 195dBc/Hz FOM and Flicker Noise Corner of 200kHz
An LC oscillator can achieve near optimal performance if the common-mode of the circuit is designed to resonate at twice the oscillation frequency [1-3]. Common-mode resonance can be accomplished with an explicit tail in
ISSCC 2016
Session 2
RF & Wireless
A 2-to-16GHz BiCMOS ΔΣ Fractional-N PLL Synthesizer with Integrated VCOs and Frequency Doubler for Wireless Backhaul Applications
STMicroelectronics, Catania, Italy The flourishing of ubiquitous wireless communication networks has pushed the development and deployment of complex RF telecom systems. Concurrently, the IC industry has been making an e
ISSCC 2016
Session 2
RF & Wireless
A 4.2μs-Settling-Time 3rd-Order 2.1GHz PhaseNoise-Rejection PLL Using a Cascaded TimeAmplified Clock-Skew Sub-Sampling DLL
tuning range compared with LC-VCO-based PLLs. However, they typically have higher jitter and larger frequency drift due to high sensitivity to PVT variations. Several PLL architectures were proposed to reject the phase n
ISSCC 2016
Session 2
RF & Wireless
A Scalable 28GHz Coupled-PLL in 65nm CMOS with Single-Wire Synchronization for LargeScale 5G mm-Wave Arrays
Demonstrations of mm-Wave arrays with >50 elements in silicon has led to an interest in large-scale mm-Wave MIMO arrays for 5G networks, which promise substantial improvements in network capacity [1,2]. Practical conside
ISSCC 2016
Session 2
RF & Wireless
An Integrated 0.56THz Frequency Synthesizer with 21GHz Locking Range and -74dBc/Hz Phase Noise at 1MHz Offset in 65nm CMOS
Richard Al Hadi1, Yanghyo Kim1,2, Adrian Tang1,2, Theodore Reck2, Huan-Neng Chen3, Chewnpu Jou3, Fu-Lung Hsueh3, Mau-Chung Frank Chang1,4 University of California, Los Angeles, CA, Jet Propulsion Laboratory, Pasadena, CA
ISSCC 2016
Session 19
Digital Circuits
A 0.0021mm2 1.82mW 2.2GHz PLL Using TimeBased Integral Control in 65nm CMOS
generators in analog, digital, RF, and embedded systems to generate a high frequency output clock from a low frequency reference clock. Modern systems-on-chip (SoCs) require many such PLLs that cater to multi-core proces
ISSCC 2016
Session 19
Digital Circuits
A 65nm CMOS ADPLL with 360μW 1.6ps-INL SS-ADC-Based Period-Detection-Free TDC
an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC. Power-hungry techniques, such as a Vernier delay line (VDL) and a time amplifier (TA) [1,2], have been proposed
ISSCC 2016
Session 19
Digital Circuits
Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System
Clock power remains a substantial contributor to power dissipation, from ultralow-power to high-performance systems [1, 2, 3]. Recently, resonant clocking has been shown to achieve power reduction in clock distribution n
ISSCC 2016
Session 19
Digital Circuits
A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation
Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring oscillator are integrated togeth