全部论文

Papers 2008–2026

共 3875 篇 ISSCC 论文，按年份倒序排列

年份 Year
2026 2472025 2422024 2222023 2002022 1672021 1952020 2022019 1812018 2052017 2082016 2002015 1912014 2032013 2102012 1882011 1962010 2102009 1802008 228
领域 Topic
RF & Wireless 362Power Management 302Wireline I/O 300Wireless 293Data Converters 279Digital Processors 268Memory 266AI / ML 231Digital Circuits 220Medical & Bio 211Image Sensors 184Analog Circuits 169mm-Wave 138Clocking & PLLs 127Sensors 100Plenary 63Hardware Security 36Quantum & Photonics 29Industry Highlights 7
顶级机构
University of California 101Delft University of Technology 73University of Macau 58KAIST 51Massachusetts Institute of Tec 48Tsinghua University 39National Taiwan University 38University of Michigan 37Georgia Institute of Technolog 35Columbia University 28Hong Kong University of Scienc 24MediaTek 23
ISSCC 2025 Session 21 Power Management
Merging Hybrid and Multi-Phase Topologies: A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3 Current Density
Mahmoud Hassan Kamel Hmada1, Wen-Chin Brian Liu1, Gaël Pillonnet2, Patrick Mercier1
voltage and current requirements, such as delivering over 1A at voltages below 1V. This drives the need for efficient point-of-load DC-DC converter topologies capable of large step-down conversion with high current densi
University of California, San Diego, CA CEA-Léti, Grenoble, France 1 2
ISSCC 2025 Session 21 Power Management
A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC
Jeong-Hun Kim1, Young-Jun Jeon1, Won-Gyu Kim1, Jaeseung Lee2,
significant thermal dissipation. Because long-term exposure to high temperature degrades SoC performance, it is necessary to manage the temperature in the devices. Consequently, low-dropout regulators (LDO) that supply t
Jun-Hyeok Yang2, Sung-Wan Hong1 Sogang University, Seoul, Korea Samsun
ISSCC 2025 Session 21 Power Management
A Fully Integrated Multi-Phase Voltage Regulator with
Enhanced Light-Load-Efficiency Peak of 86%, Featuring an, Autonomous Mode Transition from Hard-Switching to
Soft-Switching to Discontinuous Conduction Mode in 3nm FinFET CMOS Kishan Joshi1, Avinash Shreepathi Bhat2, Christopher Schaef2, Keng Chen3, Edward Lee2, Yura Kocharyan1, Ajay Janardanan2, Dinesh Ganta2, Huanhuan Zhang3,
ISSCC 2025 Session 21 Power Management
A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer
Yunho Lee, Hyunjun Park, Minsu Kim, Woojoong Jung, Hongseok Kim, Hyung-Min Lee
critical, particularly in those using a 2-cell battery such as tablets, portable gaming consoles, and power banks. In forward mode (FM), these devices are predominantly charged via a 5V USB travel adapter (VUSB), ensurin
Korea University, Seoul, Korea In modern portable devices, bidirection
ISSCC 2025 Session 21 Power Management
A Segmented-Interlacing Multi-Phase Hybrid Converter with Inherently Auto-Balanced ILs and Boosted IL Slew Rate During Load Transients
Jiacheng Yang1, Rui P. Martins1,2, Mo Huang1
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 In datacenters, direct conversion from a 12V input voltage VIN intermediate bus to point-of-load (PoL) is a common practice for powering computing chi
University of Macau, Macau, China
ISSCC 2025 Session 21 Power Management
A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCF Balancing and Wide VCR for Foldable Mobile Applications
Woojin Hong, Hyebong Ko, Jinwoo So, Woonhyung Heo, Yonghwan Cho,
Jeongdu Yoo, Ho-Sung Son, Youngwoo Chung, Dong-Joon Kim, Youngwoo Park, Byeonghyeon Jin, Sungkyu Cho, Minkyu Kwon, Kyungmin Park, Daewoong Cho, Jung Wook Heo, Sungwoo Lee, Sungwoo Moon, Hyoung-Seok Oh, Hwayeal Yu Samsung
ISSCC 2025 Session 21 Power Management
A 12A 89.3% Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators
Shengdao Ren, Yukan Du, Menglian Zhao, Zhichao Tan, Chushan Li, Yong Ding,
require a large output current at sub-1V voltages. On the other hand, the input voltage of power converters must be raised to ease the I2R loss on the system voltage bus. The high input voltage and large output current r
Wuhua Li, Wanyuan Qu Zhejiang University, Hangzhou, China The ever-hun
ISSCC 2025 Session 20 Medical & Bio
An Autonomous and Lightweight Microactuator Driving System Using Flying Solid-State Batteries
Zixiao Lin*1, Jim Wouda*2, Sami Oukassi2, Gaël Pillonnet2, Patrick Mercier1
electrostatic and piezoelectric actuators are crucial in small-scale electromechanical applications, but they significantly impact the overall system weight, especially in microrobotics [1,2,3]. These systems operate at
University of California, San Diego, CA CEA-Léti, Grenoble, France 1 2
ISSCC 2025 Session 20 Medical & Bio
A 94.8nW Battery-Free Intelligent Silicon Platform Enabling
Distributed, Adaptive, and Event-Driven Multimodal Sensing at, the Edge
Haochen Zhang1, Wei-Han Yu1, Zhongyu Zhao1, Zhizhan Yang1, Ka-Fai Un1, Jun Yin1, Rui P. Martins1,2, Pui-In Mak1 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Sens
ISSCC 2025 Session 20 Medical & Bio
A 384-Site Chip Platform for Biochemical Applications with Individual Site Precision Temperature Control
Michael Coln*1, Qingdong Meng*1, Viorel Bucur2, Ramji Lakshmanan2,
Aditya Yadav1, David Lloyd3, Nicolò Ferri4, Mark Bignell4, Daniele Di Nuzzo4, Phillip Nadeau1, Matthew Hayes4, Roman Trogan1 Analog Devices, Boston, MA Analog Devices, Limerick, Ireland 3 Analog Devices, San Jose, CA 4 E
ISSCC 2025 Session 20 Medical & Bio
Fully Integrated Self-Propelling Microrobot in 180nm CMOS with Sub-GHz Parity-Time-Symmetry On-Chip Energy Harvesting and Traveling Wave Electroosmosis Actuation
Runqing Cai, Muhanmad Dilawar Khan Niazi, Yucheng Ai, Jin Zhu, Linsheng Wu, Xuyang Lu
developing millimeter-scale and micrometer-scale micro-robots. However, achieving autonomous motion within a CMOS die has remained a significant challenge. This difficulty stems from the need to integrate energy harvesti
Shanghai Jiao Tong University, Shanghai, China Modern integrated circu
ISSCC 2025 Session 20 Medical & Bio
Millimeter-Sized 0.1pM LoD Wireless 16-Channel Organic-Electrochemical-Transistor-Based Electrochemical Sensing SoC
Yuan Ma*1, Shangbin Liu*1, Yahao Song1, Chao Xie1, Yuwei Zhang2, Chao Sun2,
such as TNF-alpha and IL-6, play a crucial role as biomarkers in the management of chronic diseases like autoimmune disorders, cardiovascular diseases, and cancer [1]. Since long-term monitoring of these cytokines is ess
Xiaoyan Ma2, Lan Yin1, Milin Zhang1 Tsinghua University, Beijing, Chin
ISSCC 2025 Session 20 Medical & Bio
MEMS-Free 4096-Pixel CMOS E-Nose Gas-Sensor Array with Molecular-Selective Metal-Organic-Framework Sensing and In-Pixel Thermodynamic Modulation for Fast Sensor Regeneration
Marco Saif*, Fuze Jiang*, Shao-Wei Lo, Adam Wang, Zhikai Huang,
species and concentrations is critical for a myriad of applications, including environmental protection, industry automation, public health monitoring, and bio-/chemical-security surveillance. For example, gas sensing in
Jiachen Wang, Hangxing Liu, Chih-Jen Shih, Thomas Burger, Hua Wang ETH
ISSCC 2025 Session 20 Medical & Bio
An RFID-Inspired One-Step Packaged Multimode Bio-Analyzer#with Vacuum Microfluidics for Point-of-Care Diagnostics
Yan-Ting Hsiao1, Ya-Chen Tsai1, Wei Foo1, Hung-Yu Hou1, Yun-Chun Su2,
low-concentration molecular biomarkers requires sending samples to centralized labs, leading to high costs and delays (Fig. 20.3.1). Recent developments in molecular diagnostics thus aim to enable point-of-care (POC) det
Yueting Lily Li1, Jun-Chau Chien1 University of California, Berkeley,
ISSCC 2025 Session 20 Medical & Bio
A 3×3.3mm Configurable γ Photon Spectrometer for Precision Radioguided Cancer Resection
Rahul Lall1, Youngho Seo1,2, Ali Niknejad1, Mekhail Anwar1,2
University of California, San Francisco, CA 1 ~60% of cancer patients undergo surgery to remove a primary tumor, and precise removal of all cancer cells is vital for optimal outcomes [1]. Microscopic clusters of cancer c
University of California, Berkeley, CA
ISSCC 2025 Session 20 Medical & Bio
A Crystal-less BodyID with an Asynchronous Clockless Leakage-Powered Wake-Up Receiver and Over-the-Channel Clock Recovery
Lingke Ding, Archisman Ghosh, Shreyas Sen
Energy-constraint wireless transceivers with wake-up receivers (WuRX) traditionally rely on an always-running clock (Fig. 20.11.1) for sampling incoming data and digital correlation, necessitating local oscillator calibr
Purdue University, West Lafayette, IN
ISSCC 2025 Session 20 Medical & Bio
A 200GHz 200-Pixel 2D Near-Field Imager for Biomedical Applications
Ali Ameri, Jun-Chau Chien, Ali Niknejad
Near fields, unencumbered by the restrictions imposed by diffraction limits, can be leveraged in high-resolution sub-wavelength imaging systems [1]. Utilizing the near-fields generated by arrays of mmWave and THz resonat
University of California, Berkeley, CA
ISSCC 2025 Session 20 Medical & Bio
A 3.5×3.5mm2 1.47mW/ch 16-Channel MSS-CMOS Heterogeneous Multi-Modal-Gas-Sensor Chip Stack
Kotaro Naruse1, Naru Kato1, Takuma Matsumori1, Jun Shiomi1, Yoshihiro Midoh1,
University of Tsukuba, Tsukuba, Japan 4 University of Southern California, Los Angels, CA 1 2 Miniaturizing and reducing the power consumption of multi-modal gas sensors with multiple channels can enable a wide array of
Tetsuya Hirose1, Gaku Imamura1,2, Genki Yoshikawa2,3, Constantine Side
ISSCC 2025 Session 2 Digital Processors
STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming
Kai-Ping Lin1, Tong Wu1, Chang-Pao Lin1, Po-Wei Chen1, Zhi-Jun Zhang1,
driving ultra-high-definition (UHD) TVs and screens, offering users an immersive experience. However, the scarcity of 8K-UHD streams and the high cost of transmission bandwidth necessitate the use of ISP techniques on te
Win-San Khwa2, Meng-Fan Chang2, Chao-Tsung Huang1 National Tsing Hua U
ISSCC 2025 Session 2 Digital Processors
A 210fps Image Signal Processor for 4K Ultra HD True Video Super Resolution
Ying-Sheng Lin1, Jun Nishimura2, Chia-Hsiang Yang1
Google, Mountain View, CA 1 2 Video super-resolution (VSR) aims to convert low-resolution (LR) videos to high-resolution (HR) videos with high image quality [1]. It can be used for various video applications, such as str
National Taiwan University, Taipei, Taiwan
ISSCC 2025 Session 2 Digital Processors
IRIS: A 8.55mJ/frame Spatial Computing SoC for Interactable Rendering and Surface-Aware Modeling with 3D Gaussian Splatting
Seokchan Song, Seryeong Kim, Wonhoon Park, Jongjun Park, Sanghyuk An,
applications, which demand a real-time and user-interactive 3D graphics system [1-3]. This requires real-time surface-aware modeling (SAM) to transfer a physical object to the virtual world, and interactive photorealisti
Gwangtae Park, Minseo Kim, Hoi-Jun Yoo KAIST, Daejeon, Korea Interacti
ISSCC 2025 Session 2 Digital Processors
mJ/Frame 373fps 3D GS Processor Based on Shape-Aware Hybrid Architecture Using Earlier Computation Skipping and Gaussian Cache Scheduler
Xiaoyu Feng*, Hedi Wang*, Chen Tang, Tongda Wu, Huazhong Yang, Yongpan Liu
applications like virtual reality and embodied AI. Unlike traditional Neural Radiance Fields (NeRF) [1], the novel 3D Gaussian Splatting approach (3D GS) [2] circumvents NeRF’s frequent sampling and intensive network inf
Tsinghua University, Beijing, China *Equally Credited Authors (ECAs) 3
ISSCC 2025 Session 2 AI / ML
A 16nm 5.7TOPS CNN Processor Supporting Bi-Directional FPN for Small-Object Detection on High-Resolution Videos
Yu-Chun Ding1, Chia-Yu Chang1, Chun-Yeh Lin1, Hui-Yun Tsai1, Hao-Jiun Tu1,
Kai-Feng Chang1, Yu-Ching Su1, Tsung-Han Hsieh1, Yu-Kuan Jian1, Wen-Ching Chen2, Nian-Shyang Chang2, Chun-Pin Lin2, Chi-Shi Chen2, Chao-Tsung Huang1 National Tsing Hua University, Hsinchu, Taiwan Taiwan Semiconductor Res
ISSCC 2025 Session 2 Digital Processors
IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator
Gerald Strevig1, Chris Berry2, Rahul Rao3, Noam Jungmann4, Michael Sperling2,
Michael Becht2, Eduard Herkel5, Matthias Pflanz5, Pat Meaney2, Michael Romain2, Mark Cichanowski1, Amanda Venton1, David Wolpert2, Elazar Kachir4, Luke Hopkins2, Tim Bubb2, Andreas Arp5, Daniel Kiss5, Simon Büchsenstein5
ISSCC 2025 Session 2 Digital Processors
A 0.52mJ/Frame 107fps Super-Resolution Processor Exploiting Pseudo-FP6 Sparsity for Mobile Applications
Xuyang Duan, Xinhua Shi, Zikang Zhou, Zhiyi Shu, Yitong Rong, Yufan Chen,
increasingly employed across various domains. The ability to recover fine details is especially critical in mobile applications such as gaming, video, and photography [1]. However, mobile devices are usually sensitive to
Zhen Yang, Menghan Li, Jun Han Fudan University, Shanghai, China Super
ISSCC 2025 Session 2 Digital Processors
“Zen 5”: The AMD High-Performance 4nm x86-64 Microprocessor Core
Teja Singh1, Spence Oliver1, Sundar Rangarajan1, Shane Southard1,
Carson Henrion2, Alex Schaefer1, Brett Johnson2, Sarah Bartaszewicz Tower1, Kathy Hoover1, Deepesh John1, Ted Antoniadis1, Shravan Lakshman1, Vibhor Mittal1, Brian Kasprzyk1, Ross McCoy1, Kurt Mohlman1, Anitha Mohan1, Ho
ISSCC 2025 Session 19 Clocking & PLLs
A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL
Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61dBc, In-band Fractional Spur in 40nm CMOS
stage DPD is implemented digitally. Thanks to its cascaded structure, our HC-DPD with a 6b calibration coefficient can be split into two-stage 3b DPDs, enabling significant hardwareoverhead reduction compared to the conv
ISSCC 2025 Session 19 Clocking & PLLs
A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms
Jitter, -249.7dB FoM, and 1.98µs Locking Time Using a, Polarity-Reversible SSPD
Haoran Li1, Jinge Li1, Xueying Jiang1, Xi Meng1, Jun Yin1, Rui P. Martins1,2, Pui-In Mak1 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Millimeter-wave (mm-wave)
ISSCC 2025 Session 19 Clocking & PLLs
A 60GHz I/Q-Calibrated SSB-Mixer-Based LO with Sub-ns Settling Time and -56dBc Worst-Case Spur Using ILO Filter in 28nm CMOS
Jaewon Oh1, Cheol So2, Hyojun Kim3, Songcheol Hong1, SeongHwan Cho1
University of California, Santa Babara, CA 3 Korea Aerospace Research Institute, Daejeon, Korea 1 2 Joint communication and radar sensing (JCAS) has been gaining much attention for its efficient use of spectrum, particul
KAIST, Daejeon, Korea
ISSCC 2025 Session 19 Clocking & PLLs
A Differential Series-Resonance CMOS VCO with Pole-Convergence Technique Achieving 202.1dBc/Hz FoMTA at 10MHz Offset
Jinhua Guo, Pei Qin, Haoshen Zhu, Xiang Yi, Wenjie Feng, Wenquan Che, Quan Xue
sought for various applications, such as high-speed wireless/wireline communications, high-speed ADC/DACs, etc. According to Leeson’s formula (Fig. 19.5.1 top-left), achieving lower PN requires a larger VTANK or a smalle
South China University of Technology, Guangzhou, China Voltage-control
ISSCC 2025 Session 19 Clocking & PLLs
An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz
Jiawen Chen1, Kai Xu2, Teerachot Siriburanon1, Robert Bogdan Staszewski1
King’s College London, London, United Kingdom 1 2 As data-rate requirements in 5G-Advanced and future 6G communications continue to rise, an RF oscillator with ultra-low phase noise (PN) is a prerequisite for ensuring hi
University College Dublin, Dublin, Ireland
ISSCC 2025 Session 19 Clocking & PLLs
A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique
Chao-Ching Hung, Chih-Hsien Shen, Chien-Li Lin, Mou Tzou, Kevin Fong, Yu-Li Hsueh
modulation schemes, such as 4K-QAM, and impose stringent phase-noise requirements on frequency synthesizers. In the past few years, an increasing number of frac-N PLLs with excellent jitter performance, i.e., sub-100fs,
MediaTek, Hsinchu, Taiwan State-of-the-art advanced-communication stan
ISSCC 2025 Session 19 Clocking & PLLs
A 13GHz Charge-Pump PLL Achieving 15.8fsrms Integrated Jitter and -98.5dBc Reference Spur
Depeng Sun1, Feng Bu1, Qixian Ye1, Shijie Li1, Yuan Gao1, Bowen Wang1, Hao Xu2,
wideband data converters, have imposed extremely stringent demands on phase-locked loops (PLLs) for lower jitter and spurs. Benefiting from high phase-detector (PD) gain, sub-sampling PLLs (SSPLLs) achieve superior jitte
Na Yan2, Shubin Liu1, Zhangming Zhu1 Xidian University, Xi’an, China F
ISSCC 2025 Session 19 Clocking & PLLs
A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoMJ Including the XO Power and Noise voltages as low as 0.28V for low-power VCO implementation, with the possibility to go up to 0.45V without risking gate-dielectric breakdown if lower out-of-band noise is needed. The performance of the VCO is further enhanced by the second-harmonic-resonance method applied at both supply and ground sides [18,19].
Can Livanelioglu*, Long He*, Jiang Gong*, Sina Arjmandpour, Gabriele Atzeni, Taekwang Jang
Figure 19.10.3 shows the details of the proposed pulse-injection XO driver and its noise characteristics. Figure 19.10.3 (left) shows the theoretical calculation and the simulation of the XO phase-noise (PN) floor (PNXO)
ISSCC 2025 Session 19 Clocking & PLLs
A PVT-Robust 5.5GHz Fractional-N Cascaded RO-Based Digital PLL with Voltage-Domain Feedforward Noise Cancellation
Yu Duan1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 Ring-oscillator (RO)-based digital PLLs (DPLLs) are well-suited for multi-PLL-integrated SoC designs owing to their compactness and immunity to magnetic
University of Macau, Macau, China
ISSCC 2025 Session 18 Data Converters
A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR
Bram Veraverbeke, Filip Tavernier
Cryo-CMOS has shown great potential to implement fast, scalable and efficient readout circuits for quantum bits (qubits). Several cryo-CMOS circuits for the dispersive readout of transmon qubits [1-2] or the reflectometr
KU Leuven ESAT-MICAS, Leuven, Belgium
ISSCC 2025 Session 18 Data Converters
A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMS with Progressive Conversion and Floating-Charge-Transfer Amplifier
Siyu Huang, Zhishuai Zhang, Xiyu He, Mingyang Gu, Yunsong Tao, Yi Zhong,
before the ADC often occupies a significant area and noise contribution, especially when a Nyquist-sampling ADC is used and a sharp anti-aliasing BBF is thereby necessary (Fig. 18.7.1a). The continuous-time ∆Σ modulator
Nan Sun, Lu Jie Tsinghua University, Beijing, China In the analog fron
ISSCC 2025 Session 18 Data Converters
An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration
Zhuoyi Chen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan,
realized utilizing the energy-efficient pipelined-SAR architecture [1-2]. However, a large sampling capacitance is required to suppress the thermal noise, making ADCs challenging to drive. Although the integrated driving
Ru Huang, Linxiao Shen Peking University, Beijing, China High-resoluti
ISSCC 2025 Session 18 Data Converters
A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting
Siyuan Ye, Jiajia Cui, Jihang Gao, Jie Li, Xing Zhang, Ru Huang, Linxiao Shen
With the development of high-resolution ADCs (>13b) leveraging the SAR topology, the pursuit of power efficiency in ADC design continues to make remarkable strides [1-5]. However, as the capacitance of the capacitive DAC
Peking University, Beijing, China
ISSCC 2025 Session 18 Data Converters
A 184.8dB-FoMS 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique
Zongnan Wang, Bingrui Li, Jiajun Tang, Zhongyi Wu, Haoyang Luo, Yuan Wang, Xiyuan Tang
high-resolution ∆Σ modulator, is favored for sensor nodes demanding high accuracy, good energy efficiency, and easy system integration. Conventional zoom ADCs, constrained by the low quantization levels of ∆Σ modulators,
Peking University, Beijing, China The incremental zoom ADC, integratin
ISSCC 2025 Session 18 Data Converters
A 12.2µW 99.6dB-SNDR 184.8dB-FOMS DT Zoom PPD ∆ΣM with Gain-Embedded Bootstrapped Sampler
Yaohui Luan, Xinhang Xu, Jihang Gao, Jiajia Cui, Zhuoyi Chen, Siyuan Ye,
consumption as they determine the overall noise and linearity performance. To achieve high resolution, discrete-time (DT) ∆ΣMs require large sampling capacitors [1-3]. This induces a huge driving burden for the ADC input
Ru Huang, Linxiao Shen Peking University, Beijing, China Input stages
ISSCC 2025 Session 18 Data Converters
A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMS in 1kHz BW *Equally Credited Authors (ECAs) An issue of 3-level switching is that it suffers from nonlinearity caused by VCM error. As shown in Fig. 18.1.3, without VCM error, the asymmetric capacitor mismatch in a differential 3-level DAC only causes an offset (common-mode mismatch). But with VCM error, the characteristic curve of DAC becomes nonlinear. This nonlinearity mainly introduces the 2nd-order harmonic distortion, as the VCM usage is a bilaterally symmetry pattern versus DAC input value. This nonlinearity can be neatly solved by the system-level chopping. When the polarity of chopping signal is reversed, the DAC mismatch is also reversed. In this manner, the differential DAC mismatch is averaged out, as well as the offset caused by asymmetric DAC mismatch. In this design, the VCM voltage is generated by two 2.5MΩ off-chip resistors. High-resolution ADCs with micro power and kHz-level BW have wide applications in portable instrumentation, implantable devices and smart sensors. To enhance flexibility and improve energy efficiency, many systems require duty-cycled operation and expect power scaling
with speed. State-of-the-art high-resolution ADC solutions include DSMs, zoom, SAR and, noise-shaping (NS) SAR ADCs. The
THD of -116dB, and it consumes high power due to the 4th-order loop filter. The zoom ADC in [2] combining with a coarse SAR and a fine DSM achieves 119.8dB SNR, but it can only process DC signals. The dynamic zoom ADCs [
ISSCC 2025 Session 17 Hardware Security
A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process
Nandish Mehta1, Stephen Tell2, Sanquan Song1, Sudhir Kudva1, Brian Zimmer1,
Mahmut Sinangil1, C. Thomas Gray2 Nvidia, Santa Clara, CA Nvidia, Durham, NC 1 2 On-chip oscillators are emerging as a critical circuit for improving the security of systemon-chips (SoCs). Many SoCs utilize an on-chip os
ISSCC 2025 Session 17 Hardware Security
An Eye-Opening Arbiter PUF for Fingerprint Generation Using Auto-Error Detection for PVT-Robust Masking and Bit Stabilization Achieving a BER of 2e-8 in 28nm CMOS
Bjoern Driemeyer, Holger Mandry, David-Peter Wiens, Joachim Becker,
John G. Kauffman, Maurits Ortmanns University of Ulm, Ulm, Germany Physically Unclonable Functions (PUFs) enable hardware identification and security key generation without storing them in non-volatile memory or exposing
ISSCC 2025 Session 17 Hardware Security
An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies and implemented in the 3nm (GAA) and 8nm (FinFet) technology nodes. The evaluations were performed on the test dies of both technologies across various process corners and operational conditions, where each die contains six PUF macros.
Bohdan Karpinskyy, Yong Ki Lee, Sumin Noh, Yunhyeok Choi, Jieun Park,
Figure 17.4.3 presents the distribution of &Vth in PUF cells, as measured in the analog Monte Jisu Kang, Taewook Park, Eunhye Oh, Gapkyung Kim, Sungha Lee, Hyunwoo Ko, Carlo simulation of 3nm (GAA) PUF cells, along with
ISSCC 2025 Session 17 Hardware Security
A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation
Liang-Hsin Lin, Yao-Kai Yang, Chia-Hsiang Yang
Secure data processing has become critical to privacy-preserving in the data-driven AI era. Multi-party computation (MPC) enables computations among multiple parties (users) in a collaborative way while preserving data p
National Taiwan University, Taipei, Taiwan
ISSCC 2025 Session 17 Hardware Security
A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing
Sijia Lu1,2, Wenping Zhu1,2, Bohan Yang1,2, Jiajun Yang1,2, Tongwei Dai1,2,
Chen Chen1,2, Xiangdong Han1,2, Jinjiang Yang3,$Hanning Wang1,2, Min Zhu4, Shaojun Wei1,2, Aoyang Zhang1, Leibo$Liu1,2 Tsinghua University, Beijing, China Beijing National Research Center for lnformation Science and Tech
ISSCC 2025 Session 17 Hardware Security
Sensor-Less Laser Voltage-Probing Attack Detection via Run-Time-Leakage-Shift Monitoring with 4.35% Area Overhead
Hui Zhang*1, Longyang Lin*2, Dingyi Xiong1, Massimo Bruno Alioto1
Southern University of Science and Technology, Shenzhen, China 1 2 *Equally Credited Authors (ECAs) Higher levels of security are constantly demanded in view of the ever-expanding threats of physical attacks [1–7], whose
National University of Singapore, Singapore, Singapore
ISSCC 2025 Session 16 Digital Processors
SambaNova SN40L: A 5nm 2.5D Dataflow Accelerator with Three Memory Tiers for Trillion Parameter AI
Raghu Prabhakar, Junwei Zhou, Darshan Gandhi, Youngmoon Choi,
Mahmood Khayatzadeh, Kyunglok Kim, Uma Durairajan, Jeongha Park, Satyajit Sarkar, Jinuk Luke Shin SambaNova Systems, Palo Alto, CA The SN40L is the latest-generation Reconfigurable Dataflow Unit (RDU) from SambaNova Syst
ISSCC 2025 Session 16 AI / ML
An On-Device Generative AI Focused Neural Processing Unit in 4nm Flagship Mobile SoC with Fan-Out Wafer-Level Package
Jun-Seok Park, Taehee Lee, Heonsoo Lee, Changsoo Park, Youngsang Cho,
Mookyung Kang, Heeseok Lee, Jinwon Kang, Taeho Jeon, Dongwoo Lee, Yesung Kang, Kyungmok Kum, Geunwon Lee, Hongki Lee, Minkyu Kim, Suknam Kwon, Sung-beom Park, Dongkeun Kim, Chulmin Jo, HyukJun Chung, Ilryoung Kim , Jongy