SAR ADC — ISSCC & JSSC 知识库

JSSC 2025第1期Data ConvertersSAR ADC

A 12 bit 15 GS s Single Channel Pipelined SAR ADC With a Pipelined

一篇关于12位15GS/s单通道流水线SAR ADC设计的JSSC论文

12 bit, 15 GS/s

JSSC 2025第2期Data ConvertersSAR ADC

A 1 GS s 11 b Time Interleaved SAR ADC With Robust Fast and

提出一种1 GS/s 11位时间交织SAR ADC，具备鲁棒快速准确自相关功能。

1 GS/s, 11-bit

JSSC 2025第3期Data ConvertersSAR ADC

A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Ampliﬁer

一款采用三态SAR逻辑和开环逆变器残差放大器的13位高速ADC

40nm CMOS, 1.1-1.2V, 600-675MS/s, 62.4dB SNDR, 7.05mW

JSSC 2025第3期Data ConvertersSAR ADCDelta-Sigma ADC

A 20-μs Turn-On Time, 24-kHz Resolution, 1.5–100-MHz Digitally Programmable Temperature-Compensated

一种基于快速锁定频率锁定环(FLL)和Δ-Σ分数分频器(FDIVs)的时钟发生器，具有20微秒启动时间和24kHz分辨率。

1.5–100 MHz可编程输出频率, 24kHz分辨率, 140ps峰峰值周期抖动, 6.8ppm/°C温漂

JSSC 2025第3期RF & WirelessSAR ADCHigh-Speed Link

A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET Yu a n m i n g Z h u, Member , IEEE

一种抗抖动40Gbps多载波接收前端，采用4GS/s基带和优化ADC设计。

22nm FinFET, 40Gb/s, 1.6-ps rms抖动容限, BER<10-5, 3.05-pJ/bit能效

JSSC 2025第4期Data ConvertersSAR ADC

A 5 nm 60 GS s 7b 64 Way Time Interleaved Partial Loop Unrolled SAR ADC Achievi

一篇关于5纳米工艺下64路时间交织部分循环展开SAR ADC设计的JSSC论文

5 nm CMOS, 60 GS/s

JSSC 2025第4期Data ConvertersSAR ADC

A 7 bit 175 GS s 69 fJ conv step FoMw Loop Unrolled Fully Asynchronous SAR ADC

本文介绍了一种7位175GS/s、69fJ/转换步长的全异步SAR ADC。

7 bit, 175 GS/s, 69 fJ/conv-step

JSSC 2025第6期Data ConvertersSAR ADC

A 936 dB SNDR Fully Dynamic CT DT Noise Shaping SAR ADC With Closed

提出一种具有闭环电容的936 dB SNDR全动态连续时间离散时间噪声整形SAR ADC

936 dB SNDR

JSSC 2025第7期Data ConvertersSAR ADC

A 272 fJ Conversion Step 13 bit SAR ADC With Wide Common Mode

提出一种272 fJ/转换步的13位SAR ADC，具有宽共模互补结构。

272 fJ/转换步, 13位精度

JSSC 2025第7期Data ConvertersSAR ADC

A 2 mW 707 dB SNDR 200 MS s Pipelined SAR ADC Using Continuous Time SAR Assiste

一款采用连续时间SAR辅助技术的低功耗高精度流水线SAR ADC

2mW, 707dB SNDR, 200MS/s

JSSC 2025第7期Data ConvertersSAR ADCPLL

A Digital Sampling PLL With a Second Order Noise Shaping SAR ADC

一种采用二阶噪声整形SAR ADC相位检测器的数字采样PLL

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JSSC 2025第10期RF & WirelessSAR ADC

Compressive Sensing Photoacoustic Imaging Receiver With Matrix-Vector-Multiplication SAR ADC

本文提出了一种用于可穿戴光声成像设备的压缩感知接收器，通过硬件嵌入压缩感知技术显著降低数据量。

57.5 dB SNDR @20.41MS/s, 3.5nV/(Hz)^1/2噪声, 5.83mW/通道

JSSC 2025第11期RF & WirelessSAR ADC

Compressive Sensing Photoacoustic Imaging Receiver With Matrix-Vector-Multiplication SAR ADC

本文提出了一种用于可穿戴光声成像设备的压缩感知接收器，通过硬件嵌入压缩感知技术显著降低数据量。

57.5 dB SNDR at 20.41 MS/s, 3.5 nV/(Hz)^1/2 input-referred noise, 5.83 mW/channel

JSSC 2025第12期Data ConvertersSAR ADCNeural Network Accelerator

A 72-GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3-dB SFDR at 20-GHz /Nyquist Inputs in 16-nm FinFET

本文介绍了一种72-GS/s 9位时间交错流水线-SAR ADC，在20GHz输入下实现55dB SFDR。

72-GS/s, 9-bit, 393.6 mW, 46.4-dB SNDR, 63.6-dB SFDR

JSSC 2025第12期Data ConvertersSAR ADC

A Calibration-Free Pipelined-SAR ADC With Cross-Stage Gain-Mismatch Error Shaping and Inherent Noise Shaping

提出一种无需校准的流水线-SAR ADC，采用跨级增益失配误差整形技术

55nm CMOS, 1.2V, 93.3dB SNDR, 156.25kHz带宽, 306.88uW功耗

JSSC 2025第12期Data ConvertersSAR ADCDAC

A Cryo-CMOS 800-MS /s 7-bit Charge-Injection SAR ADC With Only 4-fF Input Capacitance and 64-dB SFDR in 40-nm Bulk CMOS

一款低温CMOS 800MS/s 7位电荷注入SAR ADC，输入电容仅4fF。

40nm CMOS, 0.84Vpp, 800MS/s, 6.5K, 2.89mW

JSSC 2025第12期RF & WirelessSAR ADC

A Filter-Embedded Pipe-SAR ADC With Progressive Conversion and Floating Charge Transfer Ampliﬁer

提出一种嵌入式滤波器的流水线SAR ADC架构，具有高效率和宽带宽特性。

28nm CMOS, 70.1-dB SNDR, 80-MHz带宽, 4.9mW功耗, 172.2dB FoM

JSSC 2025第12期Data ConvertersSAR ADC

Erratum Erratum to “A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Oﬀset Calibration”

论文更正了异步SAR ADC中ENOB和FoMw的计算方法，采用SNDR公式以确保一致性。

7-bit, 115-GSs, 26-bitCycle

JSSC 2024第2期Power ManagementSAR ADCNeural Network Accelerator

A 15.4-ENOB, Fourth-Order Truncation-Error- Shaping NS-SAR-Nested 16 Modulator With Boosted Input Impedance and Range for

一种高输入阻抗、宽线性输入范围的16调制器，用于生物医学信号采集。

94.5-dB SNDR, 1–500-Hz带宽, 600-mV PP输入, 174.3 dB FoM SNDR, 175.8 dB FoM DR, 208 MΩ@dc输入阻抗

JSSC 2024第3期Data ConvertersSAR ADC

An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS

基于全电流处理的面积高效智能温度传感器设计

180nm CMOS, 1.8V, 34µA, 0.057mm², 92mK分辨率

JSSC 2024第3期Data ConvertersSAR ADCDelta-Sigma ADC

An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R

提出一种无额外环路延迟补偿的20MHz带宽四阶连续时间ΣΔ调制器，采用二阶噪声整形CT-SAR ADC技术。

28nm CMOS, 1.5-1V, 750MHz采样频率, 20MHz带宽, 75.5dB SNDR, 2.78mW功耗

JSSC 2024第4期Data ConvertersSAR ADCDelta-Sigma ADC

An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer Hsiang-Wen Chen , Student Member , IEEE

提出一种结合VCO-CTDSM与NS-SAR量化器的混合架构，通过AAF实现高阶噪声传递函数。

28nm CMOS, 1-MHz带宽, 100 MS/s, 1.62 mW功耗

JSSC 2024第4期Power ManagementSAR ADCEnergy Harvesting

An Incremental Step Sensing MPPT Based SI-SIDO Energy Harvester With >99% Peak MPPT Efficiency for an Input Power Range of 30 µW to 33 mW Murali K. Rajendran , Member , IEEE

提出一种基于增量步进传感的MPPT算法，实现高效能量收集系统。

99.5% MPPT效率，88%转换效率，1.8 µW静态功耗

JSSC 2024第7期Data ConvertersSAR ADC

A 0.004-mm 2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp

一种采用kT/C噪声消除技术和鲁棒输入的小面积高速SAR ADC

28nm CMOS, 13-bit, 200MS/s, 0.004mm², 1.3mW

JSSC 2024第7期Data ConvertersSAR ADCNeural Network Accelerator

A 511-µW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique Hao-Hsuan Chang , Ci-Ren Chen , and Tai-Cheng Lee

提出了一种混合两级ADC，结合SAR ADC和ISDM ADC，提升SNDR和功率效率。

370kHz频率，185kHz带宽，511µW功耗，89.3dB SNDR

JSSC 2024第8期Data ConvertersSAR ADCPipeline ADC

A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC Jae-Hyun Chung

提出了一种高效能高分辨率的双残差流水线-SAR ADC，结合噪声整形技术。

81.2-dB SNDR, 89.9-dB SFDR, 1.5-MHz BW, OSR=8, 170.4-dB Schreier FoM

JSSC 2024第9期Data ConvertersSAR ADCDAC

An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC Cong Wei , Student Member , IEEE

提出一种动态范围增强的离散时间ΔΣ调制器，适用于物联网应用，具有高能效和低功耗特性。

94.7dB动态范围, 92.4dB SNDR, 700Hz带宽, 2.3μW功耗

JSSC 2024第10期OtherSAR ADC

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling Dong-Hun Lee , Kent

采用SAR辅助DNC技术和MASH结构的高分辨率连续时间ΔΣ调制器

28nm CMOS, 1.1V, 25kHz带宽, 97.4dB SNDR, 260µW功耗

JSSC 2024第10期Data ConvertersSAR ADC

A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter Amplifier

提出一种高效可调的循环充电浮点放大器，应用于流水线-SAR ADC，实现高能效。

65nm CMOS, 1.2V, 2 MS/s, SNDR 74.0 dB, SFDR 85.5 dB, 72.3 µW

JSSC 2024第12期Data ConvertersSAR ADC

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm

提出一种新型动态偏置环形放大器，应用于12位400MS/s流水线-SAR ADC，无需偏置校准，具有高增益和低功耗。

12-bit, 400-MS/s, 2.08 mW, 64.4-dB SNDR, 77.6-dB SFDR

JSSC 2023第2期Data ConvertersSAR ADCNeural Network Accelerator

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction Y uekang Guo

一款40nm CMOS工艺的60-MS/s 5-MHz带宽噪声整形SAR ADC，集成高线性输入缓冲器。

40nm CMOS, 2.5V/1.1V双电源, 60MS/s, 5MHz BW, 8.06mW

JSSC 2023第3期Data ConvertersSAR ADC

A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Ampliﬁer

一款采用三态SAR逻辑和开环逆变器残差放大器的13位高速流水线-SAR ADC。

40nm CMOS, 1.1-1.2V, 600-675MS/s, 62.8dB SNDR, 7.05mW

JSSC 2023第3期Data ConvertersSAR ADCDelta-Sigma ADC

A 20-μs Turn-On Time, 24-kHz Resolution, 1.5–100-MHz Digitally Programmable Temperature-Compensated

提出一种基于快速锁定频率锁定环和Δ-Σ分数分频器的可编程温度不敏感时钟发生器

1.5–100 MHz可编程频率范围, 24-kHz分辨率, 140-ps峰峰值周期抖动, 6.8-ppm/°C温度不敏感性

JSSC 2023第3期RF & WirelessSAR ADCHigh-Speed Link

A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET Yu a n m i n g Z h u, Member , IEEE

一种抗抖动40Gb/s基于ADC的多载波接收前端，支持三频带信号传输。

22nm FinFET, 40Gb/s, 4GS/s, BER<10-5, 3.05pJ/bit

JSSC 2023第4期Data ConvertersSAR ADC

A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Ampliﬁer Hyunchul Y oon

提出一种PVT鲁棒的电容退化动态放大器，用于低功耗流水线SAR ADC，实现65dB SNDR和79.8dB SFDR。

65nm CMOS, 0.8-1.0V, 50MS/s, 65dB SNDR, 79.8dB SFDR, 0.46mW

JSSC 2023第4期Data ConvertersSAR ADC

A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled G m-C Integrator

本文提出了一种采用连续时间噪声整形技术的SAR ADC，通过去除采样开关和占空比设计实现高性能。

65nm CMOS, 77.3-dB SNDR, 625-kHz带宽, 13.5 µW功耗

JSSC 2023第4期Data ConvertersSAR ADC

A VTC/TDC-Assisted 4 × Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW

一种采用VTCTDC辅助的四路交织38 GS/s 7位SAR ADC，具有13 GHz有效分辨率带宽和60 mW功耗。

22nm FinFET CMOS, 3.8 GS/s, 38 dB SNDR, 60 mW, 24.4 fJ/step

JSSC 2023第4期OtherSAR ADCDelta-Sigma ADC

An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer

本文提出了一种时间交织架构，解决了连续时间ΣΔ调制器中噪声整形SAR量化器的速度-分辨率瓶颈问题。

28nm CMOS, 6.4mW功耗, 0.072mm²面积, 15.625MHz带宽, 81.6dB SNDR

JSSC 2023第6期Data ConvertersSAR ADC

A Single-Channel V oltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS

提出一种采用异步流水线逐次逼近技术的8位8GS/s时域ADC，突破传统速度限制

28nm CMOS, 0.9V/0.7V, 8GS/s/5.05GS/s, 39.2dB/37.6dB SNDR

JSSC 2023第7期Data ConvertersSAR ADCNeural Network Accelerator

A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing

一款用于量子计算的1GS/s 68位低温CMOS SAR ADC，支持多通道频率复用输入。

40nm CMOS, 1GS/s, 6-8位分辨率, 36.2dB SNDR, 200pJ/conv-step FOM

JSSC 2023第8期RF & WirelessSAR ADCHigh-Speed Link

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET

一款38GS/s 7位流水线-SAR ADC，采用速度增强型自举开关和输出电平移位技术

22nm FinFET, 38GS/s, 41.9fJ/conv.-step, 20GHz 3-dB带宽

JSSC 2023第9期Data ConvertersSAR ADC

A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion

提出一种用于DNN加速器的4位混合信号MAC宏，仅需一次ADC转换完成512次4×4位MAC运算。

65nm CMOS, 56.3 GOPS, 345.3µW, 164 TOPS/W

JSSC 2023第9期Data ConvertersSAR ADC

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating

提出一种带宽自适应的流水线SAR ADC，采用三极联浮动反相放大器实现高能效和低噪声。

40nm CMOS, 40 MS/s, 821 µW, SNDR 75.7 dB

JSSC 2023第10期Data ConvertersSAR ADCTDC

A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain

一种采用环形TDC精细量化器的12位260MS/s流水线-SAR ADC，具有自动电压时间域对齐功能。

22nm CMOS, 0.8V, 260MS/s, 60.5dB SNDR, 77dB SFDR, 0.97mW

JSSC 2023第10期Data ConvertersSAR ADC

A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive V oltage– Time–V oltage Converter

提出一种12位有效精度、二阶噪声整形SAR ADC，采用PVT不敏感的电压-时间-电压转换器。

1V电源电压, 10MS/s采样率, 73.8dB SNDR, 71.4µW功耗

JSSC 2023第10期Data ConvertersSAR ADC

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating

一款采用自适应偏置浮动逆变放大器（AB-FIA）和混合参考纹波抑制技术（H-RRM）的14位500MS/s单通道流水线-SAR ADC。

28nm CMOS, 6.34mW总功耗, 500MS/s, 0.018mm²面积

JSSC 2023第10期Data ConvertersSAR ADC

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

一种校准自由的双通道时间交织噪声整形SAR ADC，采用二阶误差前馈技术，实现高分辨率和带宽。

28 nm CMOS, 1 V supply, 330 MHz operating frequency, 73.2 dB SNDR over 30 MHz bandwidth, 3.07 mW power consumption

JSSC 2023第12期Data ConvertersSAR ADC

A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference

提出一种基于环形放大器的低功耗12位1GS/s混合架构ADC。

28nm CMOS, 62.5dB SNDR, 10.6mW, 169.2dB FoM S

JSSC 2023第12期Data ConvertersSAR ADCDAC

A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC

一款采用时间交织技术的28GS/s SAR ADC，通过时间域量化实现高能效转换。

28-GS/s采样率，51.79-dB SNDR，72.36-dB SFDR，18mW功耗

JSSC 2023第12期Data ConvertersSAR ADCNeural Network Accelerator

A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting

提出一种带集成输入缓冲器的两步式SAR ADC，采用预测电平移位技术实现轨到轨信号摆幅，性能优异。

12 MS/s, 91.3 dB SNDR, 94.1 dB DR, 6.6 Vpp差分摆幅, 4 MHz输入频率, 30.41 mW功耗

JSSC 2023第12期Data ConvertersSAR ADC

A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully

一种采用量化预测展开增益误差整形技术的二阶噪声整形流水线SAR ADC

28nm CMOS, 1V, 400MS/s, 25MHz带宽, 77.2dB SNDR, 2.03mW

JSSC 2022第3期Data ConvertersSAR ADCDAC

A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques Y

一种无需校准的14位过采样SAR ADC，采用失配误差整形和预比较技术，实现103dB SFDR。

65nm CMOS, 0.8V, 4kHz带宽, 0.98µW功耗, 0.033mm²面积, 180.6dB Schreier FoM, 8.9fJ/conversion-step Walden FoM

JSSC 2022第4期Data ConvertersSAR ADCDAC

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS

一种基于环形放大器的动态流水线-SAR ADC，采用背景校准技术实现高精度和低功耗。

16nm CMOS, 500 MS/s, 3.3 mW, 10.1 ENOB, 75.5-dB SFDR

JSSC 2022第4期Data ConvertersSAR ADCVCO

OTA-Free 1-1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC Sanjeev

提出一种无OTA的1-1 MASH ADC，采用全被动噪声整形SAR VCO ADC结构，实现高能效转换。

0.16 mW功耗，71.5/75.8 dB SNDR/DR，1.1-MHz带宽，23.3 fJ/step Walden FoM

JSSC 2022第5期RF & WirelessSAR ADC

A 5G FR2 Power-Ampliﬁer With an Integrated Power-Detector for Closed-Loop EIRP Control V

5G FR2频段功率放大器集成功率检测器，实现闭环EIRP控制

28nm CMOS SOI, 12.5dBm输出功率, 10% PAE, <-25dB EVM, 400MHz带宽

JSSC 2022第5期Data ConvertersSAR ADC

A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant

提出一种采用容错插值技术的9位500MS/s 2位/周期SAR ADC，通过延迟决策提高线性度。

28nm CMOS, 1.87mW, 500MS/s, SNDR 50.6dB, SFDR 61.4dB

JSSC 2022第5期Data ConvertersSAR ADCPipeline ADC

An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration Hongshuai Zhang , Student Member , IEEE,Y a nZ h u , Senior Member , IEEE

提出一种增益误差容忍的噪声整形SAR辅助流水线ADC，采用无源前馈结构实现高精度和低功耗。

28nm CMOS, 1V, 400MS/s, 25MHz带宽, 1.26mW功耗, 75dB SNDR, 178dB FoMS

JSSC 2022第9期Power ManagementSAR ADC

An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter Chaegang Lim , Student Member , IEEE, Y ohan Choi, Student Member , IEEE, Jaegeun Song , Student Member , IEEE, Soonsung Ahn, Student Member , IEEE, Seokwon Jang , Student Member , IEEE

本文提出了一种用于高分辨率电容传感器应用的高能效噪声整形SAR电容数字转换器。

180nm CMOS, 63.3µW, 320kHz, 88.9dB SNR

JSSC 2022第10期RF & WirelessSAR ADCEqualizer

A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer Dongsuk Kang, Student Member , IEEE, Jae-Woo Park , Student Member , IEEE, Injae Park, Student Member , IEEE,M i n - S uP a r k, Student Member , IEEE,X u e f a nJ i n, Member , IEEE, Kyu-Dong Hwang , Student Member , IEEE, Dae-Han Kwon

提出一种用于GDDR接口的双二进制收发器，采用自适应均衡器技术，实现21Gb/s传输速率。

21 Gb/s, 1.42 mW/Gb, 10^-12误码率

JSSC 2022第12期Data ConvertersSAR ADCTDC

A 10-GS/s 8-bit 2850- μm2 Two-Step Time-Domain ADC With Speed and Efﬁciency Enhanced by the Delay-Tracking Pipelined-SAR TDC

一款10GS/s 8位时间域ADC，采用双通道时间交织和SAR TDC技术实现高能效和小面积。

14nm FinFET CMOS, 10GS/s, 8-bit, 2850μm², 24.8-fJ/conv-step

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