子分类 · Memory

DRAM

102 篇相关 JSSC 论文

JSSC 2025第1期MemoryEqualizerDRAM
A 16 Gb 37 Gb s GDDR7 DRAM With PAM3 Optimized TRX Equalization and ZQ Calibrat
一篇关于16Gb 37Gb/s GDDR7 DRAM的论文，重点介绍了PAM3优化的TRX均衡和ZQ校准技术。
16Gb, 37Gb/s
JSSC 2025第4期MemoryDRAM
Dyamond Compact and Efficient 1T1C DRAM IMC Accelerator With Bit
Dyamond 提出了一种紧凑高效的1T1C DRAM IMC加速器，支持位列加法操作。
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JSSC 2025第5期MemoryDRAM
A Variation Tolerant Continuous Time Ising Machine With eDRAM Based
提出一种基于eDRAM的自旋交互连续时间Ising机，具有高容错性。
无
JSSC 2025第6期MemoryDRAM
A 16 kB 65 nm GC eDRAM Macro With Internal Bias Voltage Generation
一篇关于65nm工艺下16kB GC eDRAM宏的论文，重点介绍内部偏置电压生成技术。
16kB, 65nm
JSSC 2025第6期MemoryDRAMNeural Network Accelerator
Dual Input Stacked Inverter Based Single Ended DRAM Sense Amplifier Using BL Sw
基于双输入堆叠反相器的单端DRAM感测放大器设计
无
JSSC 2025第7期MemoryDRAM
Enabling Energy Efficient Homomorphic Encryption Evaluation via eDRAM
通过基于eDRAM的设计实现高效能同态加密评估。
28nm CMOS, 1.2V, 100MS/s
JSSC 2024第1期MemoryDRAM
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell
DynaPlasia是一种基于eDRAM内存计算的可重构空间加速器，通过动态可重构核心架构和新型三模式单元提升能效和面积效率。
28nm CMOS, 20.25mm² die area, 9.6Mb cell capacity, 19.5 TOPS peak throughput, 56.0 TOPS/W peak efficiency
JSSC 2024第3期MemoryDRAMCIM
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM
提出一种无需校准的4位电流编程存内计算宏，采用3T1C eDRAM单元，提升能效和精度。
65nm CMOS, 233-304 TOPS/W, 0.4ms刷新间隔, CIFAR10 >90%推理准确率
JSSC 2024第7期MemorySRAMDRAM
A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS Rob A. Damsteegt , Ramon W. J. Overwater
本文比较了40nm CMOS工艺下SRAM与DRAM在室温至4.2K低温下的性能，提出低温存储器设计指南。
40nm CMOS, 4.2K, 75kHz
JSSC 2024第8期Data ConvertersDRAMCIM
Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive
提出一种基于eDRAM的高效能内存计算加速器，通过动态缩放ADC提升信噪比并降低开销。
28nm CMOS, 2.03mm² die area, 800kb eDRAM, 39.7-TOPS/W (8–9 b)
JSSC 2024第10期RF & WirelessDRAM
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications Hyun-A Ahn
提出第四代10nm 16Gb LPDDR5x DRAM的I/O电路和控制方法，实现8.5Gbps低功耗运行。
8.5Gbps, 0.66UI Tx眼宽, 0.57UI Rx眼宽, 功耗降低20%
JSSC 2024第10期RF & WirelessPAM-4DRAM
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed
提出一种采用PAM-4调制、数据总线反转和ZQ校准的单端DRAM接口发射机设计，提升能效并降低噪声。
38 Gb/s, 26.16 mW, 0.688 pJ/bit
JSSC 2023第1期RF & WirelessDRAM
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ Daewoong Lee , Associate Member , IEEE, Jaehyeok Baek, Hye-Jung Kwon, Dae-Hyun Kwon, Chulhee Cho , Associate Member , IEEE, Sang-Hoon Kim, Donggun An , Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-Y oung Park, Hyoung-Joo Kim, Hoseok Seol, Juhwan Kim, Jungbum Shin, Gil-Y oung Kang, Y ong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, Chan-Y ong Lee, Seungseob Lee, Tae-Hoon Park, Chi-Sung Oh , Hyodong Ban
首款采用T-coil技术的16Gb GDDR6 DRAM，通过合并多路复用器TX和优化WCK操作实现27Gb/s/pin带宽
27 Gb/s/pin with 1.35 V
JSSC 2023第1期Wireline I/ODRAM
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based
介绍了一种192-Gb 896-GB/s的HBM3 DRAM，采用低功耗高可靠性设计。
192-Gb 896-GB/s 1.0-V
JSSC 2023第1期Wireline I/ODRAM
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and V arious Activation Functions for Deep Learning Application Daehan Kwon
提出基于GDDR6的1.25V 8Gb 16Gbps内存加速器，支持深度学习操作并优化性能。
1.25V, 8Gb, 16Gbps/pin, 1TFLOPS
JSSC 2023第1期Clocking & PLLsDRAM
A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM Yeonwook Jung , Seongseop Lee
提出一种基于LMS算法的自适应滤波器，用于消除LPDDR5移动DRAM中的电源噪声引起的抖动。
28nm CMOS, 6.4 Gb/s, 60-mV PP 1-MHz supply noise, rms jitter从27.84 ps降至4.28 ps
JSSC 2023第4期Wireline I/ODRAM
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features Yesin Ryu , Sung-Gi Ahn, Jae Hoon Lee, Jaewon Park, Yong Ki Kim , Hyochang Kim , Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Sukhan Lee, Kyoung-Hwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong , Sunghwan Joo , Dajung Cho, So Young Kim, Minsu Lee, Hyunho Kim , Minhwan Kim, Jae-San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O Kim, Kyomin Sohn , Sang-Joon Hwang, and
本文提出了一种16GB HBM3 DRAM设计，通过源同步总线和片上纠错技术实现1024 GB/s带宽。
16GB容量，1024 GB/s带宽，8 Gb/s/pin，105°C高温稳定运行
JSSC 2023第12期RF & WirelessPLLDRAM
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution
一种基于单LC-VCO的5G FR1宽带LO生成器，采用子采样架构和数字校准技术实现低相位噪声。
65nm CMOS, 超低抖动, 覆盖5G FR1全频段
JSSC 2022第1期RF & WirelessDRAM
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
提出一种基于半速率时钟架构的GDDR6 DRAM，实现24 Gb/s/pin的高带宽性能。
24 Gb/s/pin, 1.35-V DRAM, PSIJ从9.97 ps降至3.22 ps
JSSC 2022第1期Wireline I/OPAM-4DRAM
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling Timothy M. Hollis , Senior Member , IEEE, Ronny Schneider, Martin Brox , Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon-Garrido
通过集成PAM-4技术，GDDR6X DRAM实现了单端信号传输下22Gbps的速率提升。
22 Gbps per-pin data rate
JSSC 2022第2期Clocking & PLLsPLLDRAM
A Low-Jitter and Low-Spur Charge-Sampling PLL
提出一种低抖动和低杂散的电荷采样锁相环，采用新型电荷域子采样相位检测器。
40nm CMOS, 5mW, 11.2GHz, -77.3dBc, 48.6fs
JSSC 2022第10期RF & WirelessSAR ADCEqualizer
A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer Dongsuk Kang, Student Member , IEEE, Jae-Woo Park , Student Member , IEEE, Injae Park, Student Member , IEEE,M i n - S uP a r k, Student Member , IEEE,X u e f a nJ i n, Member , IEEE, Kyu-Dong Hwang , Student Member , IEEE, Dae-Han Kwon
提出一种用于GDDR接口的双二进制收发器，采用自适应均衡器技术，实现21Gb/s传输速率。
21 Gb/s, 1.42 mW/Gb, 10^-12误码率
JSSC 2021第1期Clocking & PLLsDRAM
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme Ki Chul Chun , Y ong Ki Kim, Y esin Ryu, Jaewon Park, Chi Sung Oh, Y oung Y ong Byun, So Y oung Kim, Dong Hak Shin, Jun Gyu Lee, Byung-Kyu Ho, Min-Sang Park, Seong-Jin Cho, Seunghan Woo, Byoung Mo Moon, Beomyong Kil, Sungoh Ahn, Jae Hoon Lee, Soo Y oung Kim, Seouk-Kyu Choi, Jae-Seung Jeong, Sung-Gi Ahn, Jihye Kim, Jun
介绍了一种16GB 640GB/s的HBM2E DRAM，采用数据总线窗口扩展技术和同步设计，提升性能和可靠性。
16GB容量，640GB/s带宽，5Gb/s/引脚，105°C高温稳定运行
JSSC 2021第1期Power ManagementDRAM
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques
一篇关于采用混合存储体架构的低功耗LPDDR5 SDRAM的IEEE JSSC论文，实现了8.5Gb/s/pin的数据传输速率。
8.5Gb/s/pin, 12Gb容量, 第二代10nm DRAM工艺
JSSC 2021第8期Wireline I/OEqualizerDRAM
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer Hyeongjun Ko , Mino Kim
提出一种用于高容量DRAM的控制器PHY，采用阻尼电阻辅助脉冲前馈均衡器减少信号干扰。
1067 Mb/s时C/A信号时序裕量从0.23 UI提升至0.29 UI，2133 Mb/s时DQ信号读写时序裕量分别为0.53 UI和0.72 UI
JSSC 2021第10期MemoryDRAM
An Energy-Efficient GAN Accelerator With On-Chip Training for Domain-Specific Optimization
提出一种能效优化的GAN训练加速器，支持用户本地数据重训练。
65nm CMOS, 0.38-TFLOPS/W能效, 256×256图像100轮训练<30s, 274mW功耗
JSSC 2020第1期Clocking & PLLsDLLEqualizer
A 1.1-V 10-nm class 6.4-Gb/s/pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx Dongkyun Kim, Minsu Park , Sungchun Jang, Jun-Y ong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han, Kibong Koo, Y ongmi Kim, Dong Uk Lee, Jaein Lee, Kihun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jongsam Kim, Seungwook Oh, Dain Im, Y ongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, and
10nm级CMOS工艺下1.1V 6.4Gb/s/pin 16Gb DDR5 SDRAM，性能与功耗优于DDR4。
1.1V, 6.4Gb/s/pin, 16Gb
JSSC 2020第1期Clocking & PLLsDRAM
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With V arious High-Speed and Low-Power Techniques Kyung-Soo Ha , Chang-Kyo Lee , Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Y oung-Hwa Kim, Y oung Hoon Son, Byongwook Na, Seungseob Lee, Y oun-Sik Park, Hyuck-Joon Kwon, Tae-Y oung Oh, Y oung-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, and Jung-Bae Lee
本文介绍了一种采用1xnm DRAM工艺的8Gb LPDDR5 SDRAM，通过多种高速和低功耗技术实现7.5 Gb/s/pin的带宽。
7.5 Gb/s/pin, 8-Gb, 21% read power reduction, 33% write power reduction, 25% self-refresh power reduction
JSSC 2020第8期MemoryDRAM
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced V ariation of Decision Threshold V oltage Jung Min Y oon , Student Member , IEEE, Hyungrok Do, Student Member , IEEE, Daehyun Koh, Student Member , IEEE, Seung Han Oak
一种采用耦合电容抵消偏移的DRAM感应放大器，减少阈值电压随机变化的影响。
65nm CMOS
JSSC 2019第1期RF & WirelessPLLEqualizer
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking Young-Ju Kim , Hye-Jung Kwon, Su-Yeon Doo, Minsu Ahn, Yong-Hun Kim, Yong-Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-Hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyungbae Park, Seunghoon Oh, Sang-Yong Lee, Ji-Hak Yu, Kihun Yu, Chulhee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yongjun Kim, Young-Hun Seo, Chang-Ho Shin, Chan-Yong Lee, Sam-Young Bang, Younsik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, and
16Gb GDDR6 DRAM采用每比特可训练单端DFE和ZQ编码发射器，实现18Gbps/pin高速操作
16 Gb/s/pin @1.15V, 18 Gb/s/pin @1.35V
JSSC 2019第1期Wireline I/OSRAMDRAM
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS
QUEST是一款采用3D堆叠技术的多用途对数量化DNN推理引擎，具有高带宽和低延迟特性。
7.49 TOPS（二进制精度）, 1.96 TOPS（4位精度）, 300MHz时钟频率
JSSC 2019第11期MemoryDRAM
PEDRAM MOHSENI , Guest Editor Department of Electrical, Computer, and Systems Engineering Case Western Reserve University Cleveland, OH 44106 USA pedram.mohseni@case.edu
Pedram Mohseni教授在神经工程和无线传感系统领域的研究贡献。
无
JSSC 2018第1期MemoryDRAM
An 8 Gb 12 Gbpin GDDR5X DRAM for Cost Effective High
一篇关于8Gb 12Gbps GDDR5X DRAM的高性能低成本应用研究
8Gb容量, 12Gbps速率
JSSC 2018第7期MemoryDRAM
An 800 MHz Mixed VT4T IFGC Embedded DRAM in 28 nm CMOS Bulk Process for Approxi
28纳米CMOS工艺下实现的800MHz混合VT4T IFGC嵌入式DRAM
800MHz, 28nm CMOS
JSSC 2018第8期MemoryDRAM
A Fully Integrated Energy Efficient H265HEVC Decoder With eDRAM for
一款集成eDRAM的高能效H.265/HEVC解码器，适用于可穿戴设备
关键性能指标（如：28nm CMOS, 1.2V, 100MS/s）
JSSC 2018第10期OtherDRAM
Dual Loop Two Step ZQ Calibration for Dynamic VoltageFrequency Scaling in LPDDR
提出一种双环两步ZQ校准方法，用于LPDDR的动态电压频率调节。
无
JSSC 2017第1期MemoryDRAM
A 12 V 20 nm 307 GB s HBM DRAM With At Speed Wafer Level IO Test Scheme and Ada
一篇关于12V 20nm DRAM技术的IEEE JSSC论文，介绍了高速HBM和晶圆级IO测试方案。
12V, 20nm, 307 GB/s
JSSC 2016第1期MemoryDRAM
A 14 nm 11 Mb Embedded DRAM Macro With 1 ns Access
14纳米工艺下11Mb嵌入式DRAM宏，实现1纳秒访问速度。
14nm, 11Mb, 1ns access
JSSC 2015第1期Wireline I/ODRAM
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test
12V 8Gb 8通道128GB/s高带宽HBM堆叠DRAM，采用TSV阵列和微凸点接口技术。
8Gb, 8通道, 128GB/s, 1.2V
JSSC 2015第1期Power ManagementCharge PumpDRAM
A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology
22纳米三栅CMOS技术中实现的1Gb 2GHz嵌入式DRAM，具有128GB/s带宽
1Gb容量, 2GHz频率, 128GB/s带宽, 1.05V电压, 100µs保持时间
JSSC 2015第1期Wireline I/ODRAM
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation Tae-Y oung Oh, Hoeju Chung, Jun-Y oung Park, Ki-Won Lee, Seunghoon Oh, Su-Y eon Doo, Hyoung-Joo Kim, ChangY ong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-S oo Ha, Y oungRyeol Choi, Y oung-Chul Cho, Y ong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwangil Park, SeongJin Jang, and Joo
一款1.0V 8Gbit LPDDR4 SDRAM，支持3.2Gbps/pin速度并集成ECC引擎，适用于亚1V DRAM核心。
1.0V, 3.2Gbps/pin, 8Gbit
JSSC 2015第1期Clocking & PLLsDRAM
Haswell: A Family of IA 22 nm Processors
介绍第四代Intel Core处理器家族Haswell，采用22nm技术，支持多种设备形态，提升性能和能效。
22nm, 102 GB/sec L4 eDRAM, 50%电池寿命延长
JSSC 2015第8期Wireline I/ODRAM
A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques Keunsoo Song, Sangkwon Lee, Dongkyun Kim, Y oungbo Shim, Sangil Park, Bokr im Ko, Duckhwa Hong, Y ongsuk Joo, Wooyoung Lee, Y ongdeok Cho, Wooyeol Shin, Jaew oong Y un, Hyengouk Lee, Jeonghun Lee, Eunryeong Lee, Namkyu Jang, Jaemo Y ang, Hae-k ang Jung, Joohwan Cho, Hyeongon Kim, and
本文提出了一种LPDDR4设计，通过多通道架构和低摆幅接口等技术，实现了39%的能效提升和4.3 Gbps的数据速率。
1.1 V, 4.3 Gbps
JSSC 2015第10期MemoryDRAM
A Refresh-Less eDRAM Macro With Embedded V oltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder Woong Choi, Student Member , IEEE , Gyuseong Kang , Student Member , IEEE ,a n d
提出一种基于2T增益单元的无刷新eDRAM设计，用于IEEE 802.11n WLAN的Viterbi解码器。
65nm CMOS工艺，24 kb eDRAM，面积节省44%，功耗节省39%
JSSC 2015第11期RF & WirelessEqualizerDRAM
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel
提出一种65nm CMOS工艺的16.8 Gbps单端收发器，用于SiP基DRAM接口。
65 nm CMOS, 16.8 Gbps, BER < 1e-12, 5.9 pJ/bit
JSSC 2014第1期RF & WirelessDRAM
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory
一款用于双列直插内存模块的6.4Gb/s近地单端收发器，采用低功耗信号传输技术。
6.4Gb/s, 3.5英寸FR4 PCB传输, 9.1pJ/bit能效
JSSC 2014第3期MemoryDRAM
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM
采用非刷新嵌入式DRAM的低功耗高吞吐量LDPC解码器设计
9 Gb/s峰值吞吐量，89.5 pJ/b能效，37.7 mW功耗
JSSC 2014第4期Clocking & PLLsDRAM
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Y u Hsu, Shu-Chun Y ang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang
通过CoWoS平台展示1Tbit/s带宽PHY，采用TSMC 40nm CMOS技术，实现低功耗和小面积eDRAM PHY。
1Tbit/s带宽, 0.3V, 1.1Gbit/s
JSSC 2014第4期MemoryDRAM
A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 µW, 78 pArms, 400 V/s FSCV Sensing Bardia Bozorgzadeh, Student Member , IEEE, Daniel P . Covey, Christopher D. Howard, Paul A. Garris
一款用于体内神经化学模式生成的SoC，集成电刺激与快速扫描循环伏安法传感技术。
输入噪声电流78 pA rms (dc – 5 kHz), 输入电流范围±950 nA, 功耗9.3 µW
JSSC 2014第11期RF & WirelessDRAM
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Y ong-Ju Kim, Y un-Saing Kim, Byungsub Kim, Jae-Y
提出一种低能耗单端双二进制收发器，用于DRAM接口，能效达0.56 pJ/bit@7Gb/s。
0.56 pJ/bit@7Gb/s, 80 mV信号摆幅
JSSC 2013第1期MemoryDRAM
A1 . 2V3 0n m3 . 2G b / s / p i n4G bD D R 4S D R A M With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme Kyomin Sohn, Taesik Na, Indal Song, Y ong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seokhun Hyun, Hanki Jeoung, Ki-Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sangh ee Kim, Haeyoung Chung, Y oung Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, and Joo
1.2V 4Gb DDR4 SDRAM采用30nm CMOS工艺，通过双错误检测方案提升信号可靠性，实现3.3Gb/s高速操作。
30nm CMOS, 1.2V, 3.3Gb/s
JSSC 2013第4期MemoryDRAM
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM Sami Rosenblatt, Daniel Fainstein, Alberto Cestero
提出一种基于32nm SOI嵌入式DRAM的动态芯片ID生成方法，实现高安全认证。
420k ID对比较，266芯片，99.999%识别率
JSSC 2013第6期RF & WirelessDRAM
A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS
采用XTCR技术的12Gb/s多通道IO前端设计，显著提升信号完整性
12 Gb/s, 0.96 pJ/b/lane
JSSC 2013第10期MemoryDRAM
A Process-V ariation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM Daeyong Shim, Hyunsik Jeong
提出一种用于DRAM温度自适应刷新的片上CMOS温度计，显著降低自刷新电流。
3.2 mV/°C灵敏度，0.36 μW功耗，1.1V供电
JSSC 2013第11期MemorySAR ADCDRAM
A 64-fJ/Conv.-Step Continuous-Time Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital Truncator Hung-Chieh Tsai, Chi-Lun Lo, Chen-Y
40纳米CMOS工艺下采用异步SAR的64-fJ/转换步长连续时间调制器
65 MHz采样频率, 83.4 dB动态范围, 1.91 mW功耗, 1.2V电源
JSSC 2013第11期MemoryDRAM
A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson
提出一种利用嵌入式DRAM固有指纹实现芯片自认证的架构
22nm SOI, 4Mb嵌入式DRAM, 4Kb eFUSE
JSSC 2013第12期RF & WirelessEqualizerDRAM
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS
提出一种采用Tomlinson-Harashima预编码的10Gbps 8抽头6位2-PAM/4-PAM发射机，通过流水线和半速率操作提升数据率。
5.0-Gb/s 2-PAM和10.0-Gb/s 4-PAM模式，1.2 pJ/bit能效
JSSC 2012第1期Wireline I/ODRAM
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang Kyu Kang, So-Y oung Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo Sun Choi, and Y oung-Hyun Jun
一款1.2V 1Gb移动SDRAM，采用50nm技术，具有4通道512DQ引脚，实现12.8GB/s带宽。
1.2V, 12.8GB/s, 330.6mW
JSSC 2012第1期MemoryDRAM
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic V oltage Scaling Technique in 44 nm CMOS Technology
介绍了一种采用自动态电压调节技术的512Mbit DDR2 SDRAM，提升芯片寿命和性能。
44nm标准DRAM工艺技术，1.8V电源，17.7mm²/50die面积
JSSC 2012第2期MemoryDRAM
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, and Chris H. Kim , Senior Member , IEEE
提出了一种667 MHz逻辑兼容嵌入式DRAM，采用非对称2T增益单元和电流模式感放技术，显著提升读写速度和能效。
667 MHz随机周期频率，1.65 ns延迟，1.1 V电压，85°C温度
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