Papers 2008–2026

Young-Chul Cho2, Seong-Jin Jang2, Joo Sun Choi2, Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1 Pohang University of Science and Technology, Pohang, Korea, Samsung Electronics, Hwaseong, Korea 1 2 Bandgap references (BGRs

An increasing number of power domains and of power states per domain, as well as decreasing decoupling capacitance per local grid and ultra-wide current dynamic range of digital load circuits (for low power on one end wh

inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible with opamp-RC techniques. The class-AB behavior of the inverter, together with the high transconductance for a given quiescent current,

David D. Wentzloff, Benton H. Calhoun PsiKick, Charlottesville, VA Most systems require a voltage reference independent of variation of power supply, process, or temperature, and a bandgap voltage reference (BGR) often s

Area-efficient low-noise instrumentation amplifiers (IAs) are required in various multi-channel sensing and monitoring applications. These IAs must be designed to achieve low noise and low power, good noise efficiency fa

input common-mode voltage range (CMVR) while powered from a single 5V supply. This beyond-the-rails capability is obtained by employing a capacitively coupled high-voltage (HV) chopper at the input of a switched-capacito

KAIST, Daejeon, Korea, 3 Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea 1 2 Low-power CMOS reference clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as impla

widely used to support industrial, instrumentation, and other applications [1]. Most of them have been realized with BJT or JFET processes [1] to offer voltage noise PSD better than 10nV/√Hz and offset voltage drift bett

Jim Farrell1, Dave Johnson2, Guhan Krishnan1, Hugh McIntyre3, Edward McLellan1, Samuel Naffziger2, Russell Schreiber4, Sriram Sundaram4, Jonathan White1 AMD, Boxborough, MA, 2AMD, Fort Collins, CO, 3 AMD, Sunnyvale, CA,

Droop, Temperature and Aging Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo Aseron, Trang Nguyen Jr, Charles Augustine, James Tschanz, Vivek De Intel, Hillsboro, OR 8-transistor (8T) cell 1-read/1-write (1R1W) register file

analysis in image retrieval with high accuracy [1]. As Fig. 4.6.1 shows, various applications, such as text, 2D image and motion recognition use DL due to its best-in-class recognition accuracy. There are 2 types of DL:

Arvind Raghavan1, Charles Morganti2, Chris Houghton1, Dan Krueger2, Olivier Franza1, Jayen Desai2, Jason Crop2, Dave Bradley2, Chris Bostak2, Sal Bhimji1, Matt Becker1 Intel, Hudson, MA, 2Intel, Fort Collins, CO 1 The ne

Huy N. Nguyen2, Mihir Pandya2 IBM Research, Rüschlikon, Switzerland, Freescale Semiconductor, Austin, TX 1 2 MicroServers integrate an entire server motherboard into a single Server-on-aChip (SoC), excluding DRAM, NOR-bo

Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang Oracle, Redwood Shores, CA The goal of the power management system of Oracle’s SPARC M7 CPU [1] is to maximize the performanc

Francis Schumacher, Venkat Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McA

Donald Plass2, Yuen Chan2, Sean Carey2, Gerard Salem4, Friedrich Schroeder5, Frank Malgioglio2, Guenter Mayer5, Christopher Berry2, Michael Wood2, Yiu-Hing Chan2, Mark Mayo2, John Isakson3, Charudhattan Nagarajan6, Tobia

greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock fr

in 65nm CMOS Tejasvi Anand1, Mrunmay Talegaonkar1, Ahmed Elkholy1, Saurabh Saxena1, Amr Elshazly2, Pavan Kumar Hanumolu1 University of Illinois, Urbana, IL, 2Intel, Hillsboro, OR 1 Energy-proportional operation of serial

Sebastian Hoyos, Samuel Palermo control that allows all combinations ranging from all pre-cursor to all postcursor equalization taps. A loop-unrolled architecture is utilized to meet the critical feedback timing paths of

to data-rates of 40Gb/s and beyond. Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for

signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from pr

Bruce Xu, Daniel Wu, Didem Turker, Hesam Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang Xilinx, San Jose, CA The introduction of high-speed backplane transceivers inside

Norio Nakajima2, Masatoshi Tsuge2, Tatsunori Usugi2, Tomofumi Hokari2, Hideki Koba2, Takemasa Komori2, Junya Nasu2, Tsuneo Kawamata2, Yuichi Ito2, Seiichi Umai2, Jun Kumazawa2, Hiroaki Kurahashi2, Takashi Muto2, Takeo Ya

in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impair

such as electric motor controllers, solar panel power inverters, electric vehicle battery chargers, uninterrupted and switching mode power supplies benefit from the galvanic isolation of contactless current sensors (CCS)

Temperature sensors are widely used in microprocessors to monitor on-chip temperature gradients and hot-spots, which are known to negatively impact reliability [1-4]. Such sensors should be: 1) Small to facilitate floor

capacitance-to-digital converter (CDC) that is >9× smaller than prior CDCs with >10b resolution [1-4], and improves the energy efficiency by >10× compared to previous PM-based CDCs [1]. This is achieved with the help of

various physical quantities, including position, pressure, and concentration of certain chemicals [1-6]. Integrating capacitive sensors into a small wireless sensor system is challenging due to their large power consumpt

Resonant sensors are a promising candidates for energy-constrained applications. For instance, the resonance frequency shift of polymer-coated MEMS resonators has been used to realize electronic nose systems for personal

Jingren Gu1, Richard Ruby2, Brian P. Otis1 University of Washington, Seattle, WA, Avago Technologies, San Jose, CA 1 2 This work presents a single-chip sub-mm3 wireless pressure sensor suitable for tire pressure monitori

in high-volume applications, largely due to intuitive user interfaces in smart phones and video game controllers. For their continued expansion into more demanding CE applications, a further reduction of their noise, off

requires gm to be much larger than 1/Rs, which leads to large power overhead. The proposed subtractor in Fig. 27.2.2 utilizes a low-power OTA and a series-shunt feedback to boost the open loop gain, which makes the effec

(ESC) systems [1], which are mandated for new vehicles in many countries. Gyroscopes for ESC applications require higher performance specifications than those of consumer gyroscopes available in the market today. In addi

(TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching

Rong Wu1, Hemasundar M. Geddada1, Yen-Jen Ko2, Yen Ding2, Chun-Sheng Huang2, Wei-Ta Shih2, Ming-Hung Hsieh2, Wei-Te Chou1, Tianwei Li1, Ayaskant Shrivastava1, Yi-Chun Chen1, Juo-Jung Hung1, Giuseppe Cusmai1, Jiangfeng Wu

Seng-Pan U1,2, R. P. Martins1,3 University of Macau, Macao, China, Synopsys, Macao, China, 3 Instituto Superior Tecnico, Universidade de Lisboa, Portugal 1 2 Communication devices such as 60GHz-band receivers and serial

taken advantage of timeinterleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexit

Nitz Saputra3, Qiongna Zhang1, Jeff Riley1, Han Yan1, Mattia Introini1, Sijia Wang1, Christopher M. Ward1, Jan Westra1, Jiansong Wan1, Klaas Bult1 Broadcom, Bunnik, The Netherlands, Broadcom, Irvine, CA, 3Qualcomm, San D

g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 1

The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [1]. Consisting of two low-resolution charge-redistribution SAR ADCs coupled by a residue amplifier, a SAR-assisted pipeline ADC relax

Multiple emerging wireless applications (body-worn devices and IoT, for example) will demand previously impossible thin-film form factors and low system cost. One key enabling technology for this paradigm is a new class

For the last few decades, phase-noise (PN) improvement of VCOs has been an intriguing problem and remains as one of the challenges in transceiver design. PN in CMOS VCOs, especially close-in PN, greatly suffers from flic

Recent developments in RF receiver design have eliminated all on-chip inductors except for that used in the local oscillator. This paper addresses this “last inductor” problem and proposes an integer-N synthesizer archit

(PLLs) are required to have wide a frequency tuning range from 71 to 86GHz and low phase noise of -90dBc/Hz @1MHz [1], which are still very challenging even with aggressive CMOS scaling [2]. Another issue associated with

STMicroelectronics, Crolles, France 1 2 Non-ionizing terahertz imaging using solid-state integrated electronics has been gaining increasing attention over the past few years. However, there are currently several factors

The 1/f (flicker) noise upconversion degrades the close-in spectrum of CMOS RF oscillators. The resulting 1/f3 phase noise (PN) can be an issue in PLLs with a loop bandwidth of <1MHz, which practically implies all cellul

CMOS VCO performance metrics have not improved significantly over the last decade. Indeed, the best VCO Figure of Merit (FOM) currently reported was published by Hegazi back in 2001 [1]. That topology, shown in Fig. 25.3

loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequenc

Digital fractional-N PLLs are increasingly used in place of analog fractional-N PLLs as frequency synthesizers in wireless applications, because they avoid large analog loop filters and can tolerate device leakage and lo

mounted in satellites must be small and light, having high data transfer rates, and high storage capacity [1]. A small reduction in size and weight could reduce the cost of launching a satellite by a significant amount.