JSSC 年份

2022

270 篇期刊论文

JSSC 2022第1期RF & WirelessPAM-4
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS
一款集成2抽头FFE和2抽头直接反馈DFE的100Gbps PAM-4光接收器
28nm CMOS, 100Gb/s, -8.9dBm灵敏度@2.4e-4 BER, 3.9pJ/bit能效
JSSC 2022第1期Wireline I/OEqualizerPAM-4
A 112-Gbs PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline R
本文提出了一种低功耗九抽头滑动块决策反馈均衡器（SB-DFE），用于112Gb/s PAM-4长距离有线接收器，采用7nm FinFET工艺。
112Gb/s PAM-4, 7nm FinFET, 36dB损耗通道, 误码率2×10^-12, 功耗降低0.33pJ/b
JSSC 2022第1期Digital Circuits
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control Katsushige Matsubara , Hanno Lieske , Motoki Kimura, Atsushi Nakamura, Manabu Koike
提出一款12nm工艺的自动驾驶处理器，支持ASIL D安全等级，CNN处理性能达604 TOPS，能效比138 TOPS/W。
12nm工艺, 604 TOPS CNN性能, 138 TOPS/W能效比, 6MB本地内存
JSSC 2022第1期OtherNeural Network Accelerator
A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication
提出一种共模复制技术，实现130dB CMRR和50GΩ输入共模阻抗的仪表放大器。
130dB CMRR, 50GΩ输入共模阻抗, 1.86μA@1.8V, 0.227mm²
JSSC 2022第1期RF & WirelessDACEqualizer
A 224-Gbs DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFE
一款基于DAC的224Gb/s PAM-4四分之一速率发射机，采用10nm FinFET工艺，具有8抽头FFE和低抖动时钟分布网络。
224Gb/s, 65fs rms随机抖动, 1.0Vppd输出摆幅, 1.88pJ/b能效
JSSC 2022第1期Clocking & PLLsDRAM
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
提出一种基于半速率时钟架构的GDDR6 DRAM，实现24 Gb/s/pin的高带宽性能。
24 Gb/s/pin, 1.35-V DRAM, PSIJ从9.97 ps降至3.22 ps
JSSC 2022第1期MemorySRAM
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive C
三星3GAE EUV技术实现256Mb GAA 6T SRAM，采用ADBL和ACP方案降低SRAM最小电压。
256Mb, 230mV V_MIN improvement
JSSC 2022第1期MemoryEmerging MemoryCIM
A 40-nm, 64-Kb, 56.67 TOPS/W V oltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With V erification and Online Read-Dis turb Detection Jong-Hyeok Y oon , Member , IEEE
40纳米工艺64Kb RRAM宏单元，支持1-8位可编程向量矩阵乘法，峰值能效达56.67 TOPS/W。
56.67 TOPS/W, 1-8位输入和权重, 20位输出
JSSC 2022第1期Memory
A 51.3-TOPS/W, 134.4-GOPS In-Memory Binary Image Filtering in 65-nm CMOS Sumon
65nm CMOS工艺下基于6T-SRAM存内计算的图像去噪方案，能效比达51.3 TOPS/W。
65nm CMOS, 峰值吞吐量134.4 GOPS, 峰值能效51.3 TOPS/W
JSSC 2022第1期RF & WirelessEqualizer
A 56-Gbs 50-mW NRZ Receiver in 28-nm CMOS
28nm CMOS工艺下实现56Gbps低功耗NRZ接收器
56-Gb/s, BER<10^-12, 50-mW, 25dB信道损耗
JSSC 2022第1期Other
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware
一款7纳米四核混合精度AI芯片，支持FP16、HFP8、INT4和INT2计算精度，用于高效深度学习训练和推理。
262-TFLOPS Hybrid-FP8
JSSC 2022第1期Clocking & PLLs
A Clock-Phase Reuse Technique for Discrete-Time
提出一种时钟相位复用技术，显著提升离散时间带通滤波器的阻带抑制性能。
28nm CMOS, 70dB阻带抑制, 1.65mW功耗, +17.3dBm带外IIP3
JSSC 2022第1期Clocking & PLLsDLL
A Fractional- N Digital MDLL With Background Two-Point DTC Calibration Qiaochu Z
提出了一种带有背景两点DTC校准的分数-N数字MDLL，实现低抖动和低杂散。
65nm CMOS, -60dBc分数杂散, 1.67ps rms抖动
JSSC 2022第1期Wireline I/OPAM-4DRAM
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling Timothy M. Hollis , Senior Member , IEEE, Ronny Schneider, Martin Brox , Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon-Garrido
通过集成PAM-4技术，GDDR6X DRAM实现了单端信号传输下22Gbps的速率提升。
22 Gbps per-pin data rate
JSSC 2022第1期Digital Circuits
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET Colin Schmidt , John Wright , Student Member , IEEE, Zhongkai Wang, Student Member , IEEE, Eric Chang , Albert Ou , Student Member , IEEE
一款采用16nm FinFET工艺的八核144GHz RISC-V向量处理器SoC，集成可编程精度向量加速器。
16nm FinFET, 0.55V, 339MHz, 峰值能效209/92/56 GFLOPs/W (半/单/双精度)
JSSC 2022第1期Other
An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization Pengfei Zhai, Student Member , IEEE
一种采用压缩感知和增强量化的片上电源噪声分析器，显著提升测量速度和精度。
20-GHz带宽，2-MHz频谱分辨率，0.23-µV²/√MHz噪声基底
JSSC 2022第1期RF & WirelessPAM-4
An Output Bandwidth Optimized 200-Gbs PAM-4 100-Gbs NRZ Transmitter With 5-Tap F
28nm CMOS工艺下实现200Gb/s PAM-4和100Gb/s NRZ的发射机，优化带宽和摆幅
28nm CMOS, 200Gb/s PAM-4, 100Gb/s NRZ, >52.9mV眼高, 0.36UI眼宽, >98% RLM, 4.63pJ/b
JSSC 2022第1期RF & Wireless
Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon
50Gbps SiGe BiCMOS光电接收器的模拟前端设计，采用3D集成技术实现高效能
56mW功耗，1.8V供电，78.7Ω跨阻增益，27GHz带宽
JSSC 2022第1期mm-Wave
Analysis and Design of High-Harmonic-Rejection Multi-Ratio mm-Wave
提出一种高谐波抑制的多比率毫米波频率倍增器设计
22.4-40.6 GHz, 57.7 dBc@28 GHz, 51.7 dBc@39 GHz
JSSC 2022第1期Clocking & PLLs
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent
通过动态下垂分配和自适应时钟技术提升SIMO数字SoC能效
65nm CMOS, 四域SIMO SoC, Vdd保护带减少98%(UniCap)/40%(DDA), 系统功耗降低53%/31%
JSSC 2022第1期MemorySRAM
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous
一种SRAM架构，集成真随机数生成器和多比特物理不可克隆功能，实现低成本硬件安全。
28nm CMOS, 12.5µm²/输出流, 12.6Gbps, 72fJ/bit
JSSC 2022第1期Other
Introduction to the Special Section on the 2021 IEEE International Solid-State C
2021年IEEE ISSCC精选论文特辑，涵盖有线、数字电路、机器学习等多个领域的前沿研究。
224-Gb/s, 200-Gb/s, 112-Gb/s
JSSC 2022第1期RF & Wireless
Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× V oltage Gain
提出一种低功耗高线性度的被动混频器优先接收器，适用于物联网应用。
22nm FDSOI, 1.8-2.8GHz, 45-47dB转换增益, 2MHz基带带宽, 1.7-2.5mW功耗
JSSC 2022第1期Other
SCVR-Less Dynamic V oltage-Stacking Scheme for IoT MCU
提出动态电压堆叠方案，降低物联网MCU睡眠功耗38%
睡眠电流降低38%，ULPMark-CP分数提升23.6%
JSSC 2022第1期Memory
Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing
基于存内计算的可编程神经网络推理加速器，支持高效并行计算。
16nm CMOS, 3 TOPS, 30 TOPS/W (8-bit)
JSSC 2022第1期OtherEqualizer
Syn-STELLAR An EMPower SCA-Resilient AES-256 With Synthesis-Friendly Signature A
Syn-STELLAR提出了一种抗侧信道攻击的AES-256加密技术，通过数字友好的电流源和反馈机制提升安全性。
MTD从10M提升至250M
JSSC 2022第1期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
本文介绍了IEEE固态电路学会的组织结构和联系方式。
无
JSSC 2022第1期Other
V ega A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-U
Vega是一款面向物联网终端节点的十核SoC，支持DNN加速和认知唤醒，具有超低功耗和高能效。
1.7μW睡眠功耗，32.2 GOPS峰值性能，615 GOPS/W (8-bit INT), 1.3 TOPS/W (8-bit DNN), 79 GFLOPS/W (32-bit FP), 129 GFLOPS/W (16-bit FP)
JSSC 2022第2期Clocking & PLLsCDRPAM-4
A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Re ference and Separate FD Pulling Off an 8.2-Gb/s/ μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS
本文提出了一种无需参考和独立频率检测器的单环路全速率Bang-Bang时钟数据恢复电路，支持PAM-4模式，具有宽频率捕获范围和高能效。
28nm CMOS, 23-to-29-Gb/s capture range, 0.68 pJ/bit energy efficiency
JSSC 2022第2期OtherEqualizerNeural Network Accelerator
A 0.4-mA-Quiescent-Current, 0.00091%-THD +N Class-D Audio Amplifier With Low-Complexity Frequency Equalization for PWM-Residual- Aliasing Reduction Yi-Zhi Qiu , Shih-Hsiung Chien
提出一种低复杂度频率均衡技术，降低PWM残留混叠失真，实现低THD+N和低静态电流。
0.00091% THD+N, 0.0027% 最大THD+N, 168kHz fSW, 0.5-µm CMOS
JSSC 2022第2期Other
A 0.45-THz 2-D Scalable Radiator Array With 28.2-dBm EIRP Using an Elliptical Teflon Lens
提出一种新型2D可扩展辐射器阵列，通过优化设计和集成方法，在硅基THz源中实现了最高EIRP和效率。
28.2-dBm EIRP at 452.3 GHz, 0.16% dc-to-THz efficiency, 4.6% frequency tuning range
JSSC 2022第2期Clocking & PLLsPLL
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter Mario Mercandelli , Alessio Santiccioli
提出了一种125GHz分数-N型I采样PLL，采用数字相位误差校正技术，实现低抖动和高性能频率合成。
28nm CMOS, 18mW, 58.2fs rms jitter, -73.5dBc参考杂散
JSSC 2022第2期RF & WirelessLNANeural Network Accelerator
A 1.7–3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP 3 and 3.4–4.8 dB NF
一种基于开关、电容和升压变压器的N路径无源低噪声放大器，具有高线性、可调谐和高Q值特性。
28nm CMOS, 1.7-3.6 GHz, 20 MHz带宽, 9.8 dB电压增益, 3.4-4.8 dB NF, +23.5 dBm OB-IIP3, 33 dB HFRR3, +1.7 dBm B-1dB, 17.8-38.2 mW功耗
JSSC 2022第2期Clocking & PLLsCrystal Oscillator
A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio
一种采用高能量噪声比脉冲注入的510皮瓦32kHz晶体振荡器，实现超低功耗和宽温范围工作。
0.51nW, 0.45V, -25°C至125°C, 2ppb Allan偏差
JSSC 2022第2期RF & WirelessPAM-4
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator V oltage V ariations
28nm CMOS工艺下采用时间域LSB解码器和S/H技术的56Gb/s PAM-4接收器
28nm CMOS, 56Gb/s, 0.975pJ/bit
JSSC 2022第2期Wireline I/O
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
开发适用于工业机器人手臂的6 Gb/s旋转非接触连接器，实现高速可靠无线数据传输。
40 nm CMOS, BER < 10^-12, 3 mm通信距离
JSSC 2022第2期OtherClock Generation
A Charge-Sharing Locking Technique With a General Phase Noise Theory of
提出一种基于电荷共享锁定技术的毫米波频率合成器，结合数字频率跟踪环路优化性能。
28nm CMOS, 21.75-26.25 GHz, 77-fs rms jitter, 16.5 mW
JSSC 2022第2期Clocking & PLLs
A Compact 0.2–0.3-V Inverse-Class-F 23 Oscillator for Low 1 / f 3 Noise Over Wide
提出一种新型逆F类23振荡器，采用2:3变压器实现低谐波阻抗，降低相位噪声。
28nm CMOS, 0.3V, -95dBc/Hz@100kHz, -118dBc/Hz@1MHz
JSSC 2022第2期Other
A High-Efficiency 142182-GHz SiGe BiCMOS Power Amplifier With Broadband Slotline-B
提出一种基于槽线的高效宽带毫米波功率放大器，采用新型功率合成技术实现高输出功率和低损耗。
峰值功率增益30.7dB，饱和输出功率18.1dBm，峰值效率12.4% @161GHz
JSSC 2022第2期RF & Wireless
A Ka -Band SA TCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for
65nm CMOS工艺的Ka波段卫星通信收发器，具有高线性发射器和双通道接收器。
65nm CMOS, 1.05V, PSAT 20.5dBm, NF 5.4dB
JSSC 2022第2期Clocking & PLLsPLLDRAM
A Low-Jitter and Low-Spur Charge-Sampling PLL
提出一种低抖动和低杂散的电荷采样锁相环，采用新型电荷域子采样相位检测器。
40nm CMOS, 5mW, 11.2GHz, -77.3dBc, 48.6fs
JSSC 2022第2期Other
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual
提出一种基于逆变器的下垂检测器和双模式逻辑（DML）技术，有效缓解电源下垂引起的时序错误。
62 µW功耗, 2 ns响应时间, 0.9% Vdd精度, 400 mV下垂容忍
JSSC 2022第2期Digital Circuits
A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling
提出一种基于点云的流水线神经网络处理器，用于移动设备中的3D视觉系统，优化了采样分组层和卷积层的加速。
4.45 ms处理时间，8.24 mm HPE误差，266 mW功耗
JSSC 2022第2期Clocking & PLLsPLL
A Wide-Lock-In-Range and Low-Jitter 12145 GHz SSPLL Using a Low-Power Frequency-
一种采用频率扰动检测/校正环路的宽锁定范围低抖动12-14.5 GHz SSPLL
65nm CMOS, 50MHz fREF, 160MHz锁定范围, <800ns频率重捕获时间, 83fs rms抖动, 7.7mW总功耗
JSSC 2022第2期RF & WirelessPhased Array
An Eight-Element 140-GHz Wafer-Scale IF Beamforming Phased-Array Receiver With 64-QAM Operation in CMOS RFSOI
一款140 GHz八元素晶圆级中频波束成形相控阵接收器，具有低噪声和高数据速率。
7 dB噪声系数，27-28 dB阵列电子增益，139-155 GHz RF前端带宽，9.5-12.5 GHz IF带宽
JSSC 2022第2期MemoryFlash MemoryCIM
An Embedded NAND Flash-Based Compute-In-Memory Array Demonstrated in a Standard
在65nm CMOS工艺中实验验证了基于嵌入式NAND闪存的存内计算阵列神经网络硬件。
98.5%手写数字识别准确率（与软件精度差距<0.5%）
JSSC 2022第2期Data ConvertersDAC
An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs
提出一种低成本ISI加扰技术，结合DEM消除DAC中的非线性失真。
1-GS/s, 14-bit
JSSC 2022第2期Other
Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold D
28nm近阈值DSP处理器中通过时序错误检测与校正技术降低设计裕量，显著减少能耗。
0.25-0.7V, 1-200MHz, 8.1pJ/cycle@0.34V
JSSC 2022第2期Clocking & PLLsCDR
Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector
提出一种基于随机频率相位检测器的连续速率CDR设计技术，实现6.4-32Gb/s捕获范围和0.96pJ/b能效。
6.4-32Gb/s捕获范围，<11μs锁定时间，BER<10^-12，0.96pJ/b能效
JSSC 2022第2期Other
Design of Sub-10- μW Sub-0.1% THD Sinusoidal Current Generator IC for Bio-Impedance Sensing
一款用于生物阻抗传感的超低功耗、低失真正弦电流发生器IC
65nm CMOS, 0.5V, 2μApp@20kHz, 6.2μW, THD<0.088%
JSSC 2022第2期RF & WirelessNeural Network Accelerator
Dual-Band Two-Layer Millimeter-Wave Transceiver for Hybrid MIMO Systems
提出一种双频段双层毫米波收发器，用于混合MIMO系统，具有低复杂度和高能效。
28-/37-GHz频段，八元素，四流混合MIMO收发器
JSSC 2022第2期RF & Wireless
Errata Erratum to “A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain”
该论文更正了原论文中图4的错误。
无
JSSC 2022第2期Other
SMIV: A 16-nm 25-mm 2 SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent
16nm SoC SMIV集成了Arm Cortex-A53、eFPGA和缓存一致性加速器，适用于物联网设备的高效能计算。
16nm FinFET, 25mm², 1.1mW-1.36W, 4.8 TOPS/W
JSSC 2022第2期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊论文的标题和摘要信息
无关键性能指标
JSSC 2022第2期MemorySRAMCIM
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI
提出一种基于6T SRAM的双向转置存内计算宏，支持AI边缘设备的高效能乘加运算
28nm CMOS, 3.8–21 ns延迟, 7–61.1 TOPS/W能效
JSSC 2022第3期Other
A4 -μW Bandwidth/Power Scalable Delta–Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers
本文提出一种基于摆幅增强浮点逆变器的ΔΣ调制器，实现94.1dB动态范围和4µW功耗。
180nm CMOS, 4µW, 94.1dB动态范围, 89.3dB SNDR
JSSC 2022第3期RF & WirelessPLL
A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA Kyung-Sik Choi , Student Member , IEEE, Jinho Ko
一种采用伪随机相位切换调制和Class-G谐波抑制功率放大器的宽带物联网发射机
55nm CMOS, 0.9V, 0.3-to-1-GHz, 2.7±0.2 dBm输出功率, 52%±3% PA效率
JSSC 2022第3期Data ConvertersSAR ADCDAC
A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques Y
一种无需校准的14位过采样SAR ADC，采用失配误差整形和预比较技术，实现103dB SFDR。
65nm CMOS, 0.8V, 4kHz带宽, 0.98µW功耗, 0.033mm²面积, 180.6dB Schreier FoM, 8.9fJ/conversion-step Walden FoM
JSSC 2022第3期Data ConvertersPipeline ADC
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and
一种20MHz带宽、79dB SNDR的SAR辅助噪声整形流水线ADC，具有优化的噪声传递函数零点和背景校准功能。
28nm CMOS, 1V, 260MS/s, 20MHz带宽, 79.1dB SNDR, 3.1mW功耗
JSSC 2022第3期RF & Wireless
A 24 GHz-915 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Anjana D
一款高灵敏度2.4GHz唤醒接收器，采用包内占空比技术实现超低功耗。
2.4GHz, -91.5dBm灵敏度, 2μW@100ms延迟
JSSC 2022第3期Clocking & PLLsDelta-Sigma ADCTDC
A 32-GHz 405 fs rms Jitter 2372d BF o MJIT Ring-Based Fractional-N Synthesizer A
提出了一种基于环形振荡器的低抖动数字分数-N频率合成器，采用频率倍增器和优化TDC等技术。
3.2-GHz输出时钟，96-MHz输入时钟，抖动306/405 fs，功耗11.7 mW
JSSC 2022第3期MemoryEmerging MemoryCIM
A 40-nm 118.44-TOPS/W V oltage-Sensing Compute-in-Memory RRAM Macro With Write V erification and Multi-Bit Encoding Jong-Hyeok Y oon , Member , IEEE
40纳米工艺下基于电压感知的RRAM内存计算宏单元，实现118.44 TOPS/W能效
40nm CMOS, 118.44 TOPS/W, 256×256阵列
JSSC 2022第3期RF & WirelessPAM-4
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR
一款50Gb/s PAM-4硅光发射器，采用集总段MZM设计，实现高带宽和线性调制。
50Gb/s, 9.8dB ER, 0.99 level mismatch ratio, 1.39pJ/bit/dB FoM, 682mW power
JSSC 2022第3期OtherNeural Network Accelerator
A Broadband Spectrum Channelizer With PWM-LO-Based Sub-B
一种基于PWM-LO的宽带频谱信道化器，具有子带增益控制功能。
800MHz带宽, 8子带, 20dB增益调节范围, 1.6GS/s采样率
JSSC 2022第3期RF & Wireless
A Calibration-Free Energy-Efficient IC for Link-Adaptive Real-Time Energy Storage Optimization of CM Inductive Power Receivers
一种无需校准的高能效IC，用于实时优化谐振感应电流模式功率接收器的能量存储效率。
0.18µm CMOS, 0.45mm², 能效提升53%-67%
JSSC 2022第3期Analog CircuitsNeural Interface
A Digitally Assisted Multip lexed Neural Recording System With Dynamic Electrode Offset Cancellation via an LMS Interference-Canceling Filter
提出一种低功耗、面积高效的植入式神经记录系统，支持高密度神经植入应用。
每通道面积0.00248 mm²，功耗3.38 µW，输入参考噪声2.6 µVrms，噪声效率因子1.83
JSSC 2022第3期Clocking & PLLsCrystal Oscillator
A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS
提出阻抗引导啁啾注入技术，实现晶体振荡器快速启动。
5-100 µs启动时间，38.4 MHz晶体，2.6倍加速启动
JSSC 2022第3期RF & WirelessPower Amplifier
A Four-Way Series Doherty Digital Polar Transmitter at mm-Wave Frequencies Mohsen Mortazavi , Student Member , IEEE,Y i y uS h e n, Member , IEEE, Dieuwert Mul, Student Member , IEEE, L e oC .N .d eV r e e d e, Senior Member , IEEE
毫米波频段高效数字极化发射机，采用四路串联Doherty合路器提升深度功率回退效率。
40nm CMOS, 1.1mm²核心面积, 18.7dBm饱和功率, 33%/36%/22%效率@0/4.5/11.5dB PBO
JSSC 2022第3期Clocking & PLLs
A Frequency-Locked Oscillator Using Complex RC Impedance IQ-Balancing
本文提出了一种基于复杂RC阻抗IQ平衡的频率锁定振荡器，用于全集成片上频率参考。
0.18-µm CMOS, 647 kHz/1.39 MHz, 22 ppm/°C, 10-15 ppm Allan deviation, 0.89-1.27 pJ/cycle
JSSC 2022第3期Digital Circuits
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees
提出一种8位共享指数偏置浮点数神经网络训练处理器，支持高性能低精度训练。
硅验证DNN训练处理器，采用24路FMA树
JSSC 2022第3期RF & WirelessEqualizer
A Scalable 32–56 Gb/s 0.56–1.28 pJ/b V oltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS
28nm CMOS工艺下实现56Gb/s能效1.28pJ/b的电压模式VCSEL光发射机
28nm CMOS, 1.15V, 56Gb/s NRZ, 1.28pJ/b
JSSC 2022第3期Other
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems Y
提出一种可扩展的CMOS伊辛计算机，具有稀疏和可重构的自旋互连，用于解决NP难组合优化问题。
65-nm CMOS, 252 spins
JSSC 2022第3期RF & WirelessNeural Interface
A Wireless Somatosensory Feedback System Using Human
基于人体通信的无线体感反馈系统，用于瘫痪手部触觉恢复
180nm CMOS, 36.4 pJ/bit, 60 pJ/bit, 1.2 Mbps
JSSC 2022第3期RF & WirelessCDRNeural Network Accelerator
An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CD R Using Clock-Embedded C-PHY Signaling Over Trio Wires Tae-Jin Kim , Jae-Woo Park, Hyun-Wook Lim , Jae-Y oul Lee
一种采用输入电平感知CDR的18.24Gb/s、0.93pJ/bit接收器
28nm CMOS, 1V供电, 18.24Gb/s, 0.93pJ/bit, 0.022mm²
JSSC 2022第3期Other
An 85-GHz Power Amplifier Utilizing a Transformer-Based Power Combiner Operating Beyond the Self-Resonance Frequency
65nm CMOS工艺下85GHz八路四级功率放大器，采用变压器功率合成/分配器，工作频率超过自谐振频率。
29.3dB增益, 82.7-86.7GHz带宽, 19.1dBm饱和输出功率, 8.6%峰值PAE
JSSC 2022第3期OtherEnergy Harvesting
EQS Res-HBC: A 65-nm Electro-Quasistatic Resonant 5–240 μW Human Whole-Body Powering and 2.19 μW Communication SoC With Automatic Maximum Resonant Power Tracking Nirmoy Modak , Student Member , IEEE
利用电准静态谐振人体通信实现人体长度无关的无线供电与通信。
240 µW, 28 µW, 5 µW 功率传输，2.19 µW 通信功耗
JSSC 2022第3期Other
Envelope Tracking Supply Modulator with Trellis-Search-Based Switching and 160-M
采用网格搜索算法的混合放大器优化开关序列，提升效率并降低误差电流。
802.11ax调制下PA总效率提升7.2%，EVM -32.7dB
JSSC 2022第3期Other
Guest Editorial 2021 Custom Integrated Circuits Conference T HIS
2021年定制集成电路会议（CICC）特别专栏，展示虚拟会议中的前沿技术与教育成果。
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JSSC 2022第3期RF & Wireless
Magnetoelectric Bio-Implants Powered and Programmed by a Single Transmitter for Coordinated Multisite Stimulation Zhanghao Y u
一种基于磁电效应的无线供能与编程生物植入系统，支持多站点协同刺激。
0.8mm²芯片面积，6.2mm³植入体积，60°角度容差，1.5cm横向偏移容差，90%刺激效率(1.5-3.5V)
JSSC 2022第3期Other
On-Chip HV Bootstrap Gate Driving for GaN Compatible Power Circuits Operating Above 10 MHz Min
提出GaN功率电路的高效栅极驱动技术，实现20MHz高频开关和84.9%峰值效率。
0.35µm HV BCD, 20V输入, 8.4W输出, 84.9%效率, 48V/ns转换速率
JSSC 2022第3期RF & WirelessDAC
SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-A
提出一种无SAW滤波器的多模直接射频发射机，具有高动态范围和低带外噪声。
2.2GHz载波, 17.4dBm输出功率, -40dB EVM, -169dBc/Hz NSD, 1.2W功耗
JSSC 2022第3期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，提供固态电路领域的最新研究和技术进展。
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JSSC 2022第4期Data ConvertersSAR ADCDAC
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
一种基于环形放大器的动态流水线-SAR ADC，采用背景校准技术实现高精度和低功耗。
16nm CMOS, 500 MS/s, 3.3 mW, 10.1 ENOB, 75.5-dB SFDR
JSSC 2022第4期Analog Circuits
A − 121.5-dB THD Class-D Audio Amplifier With 49-dB LC Filter
提出一种双环路架构的D类音频放大器，抑制LC滤波器非线性49dB，THD达-121.5dB。
180-nm BCD, -121.5-dB THD, -107.1-dB THD+N, 21W@4Ω, 12W@8Ω
JSSC 2022第4期RF & WirelessEqualizerPAM-4
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET Chi Fung Poon , Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Daniel Zhaoyin Wu, Kee Hian Tan
7nm FinFET工艺下1.24pJ/b能效的112Gb/s PAM4收发器芯片设计
1.24pJ/b能效, 112Gb/s速率, <1e-12误码率
JSSC 2022第4期RF & Wireless
A 28-GHz Phased-Array Relay Transceiver for 5G Network Using V ector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer Michihiro Ide
一种用于5G网络的28GHz无线供电相控阵中继收发器
1.8mm²芯片面积，3.1mW直流功率输出，-27.5dB Tx EVM，-31.3dB Rx EVM
JSSC 2022第4期Power ManagementBuck ConverterNeural Network Accelerator
A 32-A, 5-V -Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-V oltage GaN nMOS
采用低压GaN nMOS功率晶体管的高频高密度降压转换器，峰值效率达94.2%。
5-V输入, 1-V输出, 94.2%峰值效率, 3.1-MHz开关频率, 40-nH电感
JSSC 2022第4期Clocking & PLLsDelta-Sigma ADCCrystal Oscillator
A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With -Modulated
一种用于物联网的超低功耗温度补偿晶体振荡器，通过分段线性温度补偿实现高精度
32.768-kHz, ±4.2 ppm, 43 nW, 34 ppb Allan deviation
JSSC 2022第4期OtherDelta-Sigma ADC
A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End
提出一种基于Delta Sigma调制的采样平均共模反馈技术的声学模拟前端，具有稳定的高通频率拐点和低功耗特性。
180nm CMOS, 192nW总功耗, 100TΩ最大有效电阻
JSSC 2022第4期RF & WirelessNeural Interface
A Light-Tolerant Wireless Neural Recording IC for Motor Prediction With Near-Infrared-Based Power and
一种光耐受无线神经记录IC，用于运动预测，支持近红外光供电和数据遥测。
0.57 µW功耗，4.1噪声效率因子（NEF）
JSSC 2022第4期Medical & BioBiosignal
A Patient-Specific Closed-Loop Epilepsy Management SoC With One-Shot Learning
提出一种患者特异性闭环癫痫管理SoC，具备一次性学习和在线调谐功能，实现高精度癫痫检测与抑制。
0.97 µJ/class, 0.13 mm²/ch., 97.8%灵敏度, 99.5%特异性, <1秒延迟
JSSC 2022第4期Clocking & PLLsPLLNeural Network Accelerator
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW
提出一种自适应增益失配的两点调制II型数字PLL，实现快速线性调频且无稳态频率误差。
28nm CMOS, 1V电源, 23mW功耗, 0.31mm²面积, 12.5GHz频率, 2.27GHz带宽, 18.2μs周期
JSSC 2022第4期Data ConvertersDAC
A mm-Wave Switched-Capacitor RFDAC Hieu Minh Nguyen Graduate Student Member IE
提出一种基于边缘组合器的毫米波开关电容RFDAC，通过时钟频率三倍提升实现高效Ka波段操作。
28 GHz Ka-band, 21 dBm Pout, >36% drain efficiency, >22% system efficiency, 2.4 Gb/s调制, 3.3% EVM, 30.8-dBc ACLR
JSSC 2022第4期MemoryEmerging Memory
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference Kartik Prabhu , Albert Gural, Student Member , IEEE, Zainab F. Khan
CHIMERA是一款基于40nm CMOS工艺的非易失性边缘AI加速器，支持训练和推理，采用RRAM技术。
40nm CMOS, 0.92-TOPS峰值性能, 2.2-TOPS/W能效
JSSC 2022第4期RF & WirelessBuck Converter
Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-
提出一种用于4G LTE和5G NR的双频带高效射频功率放大器供电调制器架构
峰值效率88.2%(LTE)/84.1%(5G), 输出功率23dBm/27dBm
JSSC 2022第4期Other
Guest Editorial Introduction to the Special Issue on the 2021 Symposium on VLSI
2021年VLSI电路研讨会论文集介绍，展示了虚拟平台互动交流的创新方式。
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JSSC 2022第4期Memory
HERMES-CoreA 159-TOPSmm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-psLS
提出了一种基于14nm CMOS工艺的256×256内存计算核心，集成多级相变存储器，实现高效计算。
14nm CMOS, 159 TOPS/mm², 300ps LS
JSSC 2022第4期Data ConvertersSAR ADCVCO
OTA-Free 1-1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC Sanjeev
提出一种无OTA的1-1 MASH ADC，采用全被动噪声整形SAR VCO ADC结构，实现高能效转换。
0.16 mW功耗，71.5/75.8 dB SNDR/DR，1.1-MHz带宽，23.3 fJ/step Walden FoM
JSSC 2022第4期Digital Circuits
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse
OmniDRL是一款面向边缘设备的高效能深度强化学习处理器，通过数据压缩和稀疏训练降低内存访问。
28nm CMOS, 3.6×3.6mm², 4.18 TFLOPS峰值性能, 29.3 TFLOPS/W峰值能效
JSSC 2022第4期MemorySRAM
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling Keonhee Cho , Heekyung Choi, In Jun Jung ,J i s a n gO h,T a eW o oO h , Kiryong Kim , Giseok Kim , Taemin Choi, Changsu Sim
提出SRAM写入和性能辅助单元，解决互连电阻增加导致的写入能力和性能下降问题。
28nm CMOS, 100%写入能力良率, 读取时间减少28%
JSSC 2022第4期RF & WirelessOptical I/OEqualizer
Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS
本文介绍了一种基于微环调制器的4波长WDM光发射器，支持112 Gb/s速率，采用光电流热控制方案。
112 Gb/s, <0.7 dB TDECQ, 5.8 pJ/bit
JSSC 2022第4期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE固态电路期刊的出版信息及编辑团队介绍
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JSSC 2022第4期Memory
V ersa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory
Versa是一款能效优化的36核脉动多处理器，支持动态重构互连和内存。
同步延迟提升6.5倍，能效比移动CPU和GPU分别提升37.2倍和11.6倍
JSSC 2022第5期RF & Wireless
A 031-THz Orbital-Angular-Momentum OAM Wave Transceiver in CMOS With Bits-to-OAM
首款基于CMOS的0.31-THz轨道角动量(OAM)波收发芯片，支持动态模式切换与模式识别。
65nm CMOS, -4.8dBm EIRP, 154mW(发射)/166mW(接收)功耗, 2.1×2.6mm²面积
JSSC 2022第5期Digital CircuitsNeural Network Accelerator
A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction Huiyu Mo
提出一种基于有效权重的量化网络加速处理器，优化CNN处理效率。
28nm CMOS, 1.9mm² core area
JSSC 2022第5期Wireline I/OPAM-4Neural Network Accelerator
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS
22nm FinFET CMOS工艺下实现的高能效128Gb/s单端PAM4线性TIA
22nm FinFET CMOS, 0.8V, 128Gb/s PAM4, 59.3dBΩ增益, 11.2mW功耗, 45.5GHz带宽, 27μArms输入噪声
JSSC 2022第5期Other
A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving 44-dBc HD3 Up To 15-V p-p O
22nm FDSOI CMOS高线性度有源巴伦，实现44-dBc HD3和1.5V p-p输出摆幅
22nm FDSOI CMOS, 5V供电, 925mW功耗, <−44-dBc HD3, 1.5V p-p输出, 0.01-5.4GHz带宽
JSSC 2022第5期RF & Wireless
A 25–34-GHz Eight-Element MIMO Transmitter for Keyless High Throughput Directionally Secure Communication Naga Sasikanth Mannem , Student Member , IEEE
利用MIMO阵列实现高吞吐量无密钥定向安全通信
45nm CMOS SOI, 八通道MIMO发射机, 5°/10°信息波束宽度
JSSC 2022第5期Clocking & PLLsCDRPAM-4
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems Takashi Toi
提出一种基于PAM-4的四通道复用和级联CDR的256Gb/s接口，用于高带宽大容量NAND闪存系统。
28nm CMOS, 3.69pJ/b能效, 25.6Gb/s速率, BER<1e-15, 1.84dB损耗
JSSC 2022第5期Clocking & PLLsCrystal Oscillator
A 32-MHz, 34- μW Temperature-Compensated RC Oscillator Using
一种采用脉冲密度调制的32MHz 34μW温度补偿RC振荡器，通过双温度修调和电阻温度系数补偿实现高精度频率输出。
32MHz, 34μW, 530ppm精度, 8.4ppm/°C, 80ppm/V电压灵敏度, 2.5ppm艾伦方差, 1μW/MHz能效
JSSC 2022第5期RF & WirelessSAR ADC
A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP C
5G FR2频段功率放大器集成功率检测器，实现闭环EIRP控制
28nm CMOS SOI, 12.5dBm输出功率, 10% PAE, <-25dB EVM, 400MHz带宽
JSSC 2022第5期Data ConvertersSAR ADC
A 9-bit 500-MSs 2-bitcycle SAR ADC With Error-Tolerant Interpolation Technique J
提出一种采用容错插值技术的9位500MS/s 2位/周期SAR ADC，通过延迟决策提高线性度。
28nm CMOS, 1.87mW, 500MS/s, SNDR 50.6dB, SFDR 61.4dB
JSSC 2022第5期RF & WirelessNeural Network Accelerator
A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting
基于切片时变架构的双通道高线性滤波混叠接收器前端设计
28nm CMOS, 0.9V, 50dB阻带抑制, 3.2倍RF带宽过渡带, +35dBm OOB IIP3, +12dBm阻塞1dB压缩点, -81dBm LO泄漏
JSSC 2022第5期RF & WirelessPhased Array
A Multi-Band 16–52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14–15.4-dBm Psat for 5G NR FR2 Operation
本文介绍了一种支持5G NR FR2频段的毫米波多频段发射相控阵设计，采用SiGe BiCMOS工艺的波束成形芯片和Vivaldi天线阵列。
峰值增益28.3 dB，输出P1dB 13.5–14.7 dBm，Psat 14–15.4 dBm，20–50 GHz
JSSC 2022第5期RF & WirelessHigh-Speed LinkEqualizer
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS Y
提出一种采用PWM技术的PAM-8有线收发器，通过时间域前馈均衡提高线性度。
12.0至39.6 Gb/s，补偿14-dB损耗，6.6 GHz，8.66 pJ/bit效率
JSSC 2022第5期Clocking & PLLsCDRPAM-4
A Sub-0.25-pJ/bit 47.6-to- 58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS Xiaoteng Zhao , Student Member , IEEE
一种无需参考和频率检测器的半速率单环路Bang-Bang时钟数据恢复电路，实现高速低功耗PAM-4信号处理。
28nm CMOS, 0.056mm²核心面积, 0.22–0.25 pJ/bit能效, 9.8 (Gb/s)/µs捕获速度
JSSC 2022第5期RF & Wireless
A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS
一种用于人体内联网的亚100微瓦、0.1至27Mb/s脉冲数字发射机
28nm FD-SOI CMOS, 0.5V, 0.1-27Mb/s, 17-76µW, 2.8-170pJ/b
JSSC 2022第5期Clocking & PLLsCharge PumpPLL
A Sub-100 Fs RMS jitter 20 GHz Fractional- N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference Sachin Kalia , Salvatore Finocchiaro
一款基于BAW谐振器的20GHz分数-N模拟PLL，具有亚100飞秒抖动性能。
20GHz, 65/92fs抖动, 188dBc/Hz FOM
JSSC 2022第5期RF & Wireless
A Wideband IQ-Mapping Direct-Digital RF Modulator for 5G Transmitters
一款用于5G发射机的宽带IQ映射直接数字射频调制器，提升功率并抑制I/Q镜像。
40nm CMOS, 14dBm峰值输出功率, -52dBc ACLR, -40dB EVM
JSSC 2022第5期Data ConvertersSAR ADCPipeline ADC
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration Hongshuai Zhang , Student Member , IEEE,Y a nZ h u , Senior Member , IEEE
提出一种增益误差容忍的噪声整形SAR辅助流水线ADC，采用无源前馈结构实现高精度和低功耗。
28nm CMOS, 1V, 400MS/s, 25MHz带宽, 1.26mW功耗, 75dB SNDR, 178dB FoMS
JSSC 2022第5期Other
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS
本文提出了一种140 GHz收发前端模块的设计与分析，采用22nm FD-SOI CMOS技术。
140 GHz, 33.6/35.7 dB功率增益, 12.5/14.7 dBm饱和输出功率, 10.8/11.3%峰值功率附加效率
JSSC 2022第5期Other
Design and Analysis of an Electrical Balance Duplexer With Independent and Concurrent Dual-Band TX-RX Isolation
设计并分析了一种支持Wi-Fi 6/6E在5-7GHz频段独立双频带TX-RX隔离的电平衡双工器。
≤4dB RX插入损耗, ≤3.8dB TX插入损耗, +29dBm TX输出, >40dB隔离度
JSSC 2022第5期Power Management
Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC
提出一种固定开关频率背景电容电流传感器校准技术，用于DC-DC转换器以实现快速负载瞬态响应。
2-A/4-ns step-up (step-down) load transient, 8.8 µs calibration period at 30 MHz switching frequency
JSSC 2022第5期Other
Guest Editorial Introduction to the Special Section on the 2021 RFIC Symposium T
2021年RFIC研讨会特邀论文集的特别章节，涵盖射频和毫米波集成电路的前沿技术与应用。
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JSSC 2022第5期mm-Wave
High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation
提出基于双调谐变压器的新型Class-E输出网络，实现毫米波雷达传感器的高效功率放大器设计。
峰值功率附加效率(PAE) 30.5%/34.7%/32.6%，输出功率17/18.1/17 dBm
JSSC 2022第5期mm-Wave
High Efficiency D-Band Multiway Power Combined Amplifiers With 17.5–19-dBm Psat and 14.2–12.1% Peak PAE in 45-nm CMOS RFSOI
采用八路低损耗功率合成的D波段高效功率放大器，在CMOS工艺中实现高饱和输出功率。
45nm CMOS, 1.2V, 16.8-19dBm Psat, 11.7%-14.2% PAE
JSSC 2022第5期mm-Wave
Highly Efficient Terahertz Beam-Steerable Integrated Radiator Based on Tunable Boundary Conditions Y
基于可调边界条件的高效太赫兹波束可调集成辐射器
等效全向辐射功率(EIRP) 21.66 dBm, DC-THz效率2.22%, 调谐范围10.8%
JSSC 2022第5期Other
Multi-Watt-Level 4.9-GHz Silicon Power Amplifier for Portable
开发了一种紧凑型4.9GHz硅基功率放大器，用于便携式热声成像。
55nm BiCMOS, 4.9GHz, 37.3-dBm峰值输出功率
JSSC 2022第5期RF & WirelessPower Amplifier
Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs
28nm CMOS工艺下基于单变压器的紧凑型Doherty功率放大器，适用于5G毫米波频段。
28nm CMOS, 27GHz, >18.8dBm POUT, >30% PAE
JSSC 2022第5期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
本文介绍了IEEE固态电路期刊及其相关组织架构和领导成员。
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JSSC 2022第6期Clocking & PLLsDLL
A 1.12–1.91 mW/GHz 2.46–4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS R. Gautam , Student Member , IEEE
提出一种低功耗低抖动的两阶段时钟乘法器，采用65nm CMOS工艺实现2.46-4.92GHz频率输出。
65nm CMOS, 2.5mW@307.2MHz, 3mW@4.92GHz, 761fs rms抖动, 825fs rms总抖动
JSSC 2022第6期Clocking & PLLsPLL
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping Simone M. Dartizio
基于自适应算法的Bang-Bang相位检测器，实现129至151 GHz数字PLL，优化噪声整形。
28nm CMOS, 0.21 mm²核心面积, 69.5 fs rms抖动, 10.8 mW功耗
JSSC 2022第6期OtherPower Amplifier
A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement
一种基于变压器的15位正交数字功率放大器，通过IQ单元共享和Doherty操作提升效率。
55nm CMOS, 1.2/2.4V, 29.3dBm峰值输出功率, 43.1% PAE
JSSC 2022第6期Wireline I/OEmerging MemoryNeural Network Accelerator
A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device Y en-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang
22纳米1Mb 1024位读取数据保护的STT-MRAM宏，采用近存移位旋转功能降低峰值电流和能耗。
42.67 GB/s读取带宽，0.23 pJ/bit能效
JSSC 2022第6期RF & Wireless
A 220-GHz Energy-Efficient High-Data-Rate Wireless ASK
220GHz高效能ASK发射器阵列，实现20Gb/s数据传输。
55nm SiGe BiCMOS, 165.2mW功耗, 4.2dBm EIRP, 20Gb/s, 8.26pJ/bit能效
JSSC 2022第6期Image SensorsSRAMCMOS Image Sensor
A 30-fps 192 × 192 CMOS Image Sensor With Per-Frame Spatial-Temporal Coded Exposure for Compressive Focal-Stack
一种支持每帧时空编码曝光的192×192 CMOS图像传感器，用于压缩焦堆成像。
192×192像素阵列, 12.6×12.6 µm²像素尺寸, 30 fps, 768 masks/frame
JSSC 2022第6期Data ConvertersPipeline ADC
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier
一款采用线性化动态放大器的3.3GS/s 6位全动态流水线ADC
28nm CMOS, 3.3GS/s, 5.5mW, 40.02-fJ/conversion-step FoM
JSSC 2022第6期Wireline I/O
A 5 Gb/s Time-Interleaved V oltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC Ji-Y
提出一种用于3D堆叠内存的低功耗双二进制编码方案，实现5Gb/s高速传输。
65nm CMOS, 5Gb/s, 0.373pJ/b/pF
JSSC 2022第6期Other
A CMOS Dual-Mode Brain–Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression Haoran Pu , Student Member , IEEE
一款用于双向脑机接口的CMOS双模芯片组，具有2mV精度时间电荷平衡技术。
40V兼容电流刺激器，12.75mA最大电流，180nm CMOS工艺
JSSC 2022第6期Power Management
A Cascaded Hybrid Switched-Capacitor DC–DC Converter Capable of Fast Self Startup for USB
一种具有快速自启动能力的级联混合开关电容DCDC转换器，采用改进纹波注入控制实现高效电压调节和电容平衡。
0.18µm CMOS, 5:1.2V转换, 峰值效率96.9%, 8µs启动时间
JSSC 2022第6期Data ConvertersVCO
A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC Viet Nguyen , Student Member , IEEE
0.2V超低压开环VCO-ADC，适用于能量收集IoT传感应用
28nm CMOS, 0.2V, 35MS/s, 64.4dB SNDR, 15.9µW
JSSC 2022第6期Clocking & PLLsPLLPAM-4
A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for
提出一种采用耦合倍频器的低相位噪声数字LC-PLL，用于224Gb/s PAM-4发射机时钟
23.9-29.4GHz, 65fs随机抖动, 17.1mW功耗, 0.8/1.0V供电
JSSC 2022第6期Data ConvertersPLL
A Fractional- N Digitally Intensive PLL Achieving 428-fs Jitter and <− 54-dBc Spurs Under 50-mV pp Supply Ripple Yu e C h e n, Student Member , IEEE, Jiang Gong , Student Member , IEEE
一款抗电源纹波的分数N数字密集型PLL，实现428fs抖动和-54dBc杂散。
4.5-5.1GHz, 428fs rms抖动, <-54dBc最大杂散, 3.25mW功耗
JSSC 2022第6期OtherBoost ConverterNeural Network Accelerator
A High-Efficiency Dual-Polarity Thermoelectric Energy-Harvesting Interface Circuit With Cold Startup and Fast-Searching ZCD
一种基于单电感升压/降压-升压混合转换器的自动极性热电能量收集接口电路。
0.13-µm CMOS, 1.2V输出, 峰值端到端效率90%
JSSC 2022第6期Power ManagementBoost Converter
A High Conversion Ratio and 97.4% High Efficiency Three-Switch Boost Converter With Duty-Dependent Charge Topology for 1.2-A High Driving Current and 20% Reduction of Inductor DC Current in MiniLED Applications Si-Yi Li, Student Member , IEEE, Y en-An Lin, Zheng-Lun Huang, Jia-Jyun Lee
提出一种三开关升压转换器，用于MiniLED面板，具有高转换比和高效率。
转换比=7.5, 驱动电流=1.2A, 效率=97.4%
JSSC 2022第6期Image SensorsCMOS Image Sensor
A High Dynamic Range 128 × 120 3-D Stacked CMOS SPAD Image Sensor SoC for Fluorescence Microendoscopy Ahmet T. Erdogan , Tarek
一款用于荧光显微的高动态范围128×120三维堆叠CMOS SPAD图像传感器SoC
1.4mm×1.4mm芯片尺寸，8μm像素尺寸，45%填充因子
JSSC 2022第6期Clocking & PLLsPLLVCO
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation Hyojun Kim , Student Member , IEEE, Woosong Jung , Student Member , IEEE, Kwandong Kim
一种基于环形振荡器的低抖动8GHz ADPLL，采用PVT鲁棒的模拟闭环设计
8GHz下289fs RMS抖动，1.1V供电，9.48mW功耗，0.055mm²面积
JSSC 2022第6期OtherNeural Network Accelerator
A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust Technique for Mitigating
提出一种新型动态偏移归零技术，有效抑制斩波纹波，提升输入阻抗，实现低噪声低功耗仪表放大器。
13-nV/√Hz输入参考噪声密度，1.3噪声效率因子，4.5 μW功耗
JSSC 2022第6期RF & Wireless
A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless
提出一种可重构单级非对称全波降压整流器，用于快速无线充电，支持设备间双向充电。
5.1W最大充电功率，46.3%总效率，1.6cm充电距离
JSSC 2022第6期Power ManagementLDOProcessor/CPU
A Scalable High-Current High-Accuracy Dual-Loop Four-Phase Switching LDO for Microprocessors
一款适用于高性能微处理器的1.5A高精度双环四相开关LDO，显著降低负载电容需求。
28nm CMOS, 1.5A, 70mV undershoot, 1mV/A负载调整率, 1.5mV/V线性调整率, -63dB PSR
JSSC 2022第6期Power ManagementBoost ConverterEnergy Harvesting
A Self-Resonant Boost Converter for Photovoltaic Energy Harvesting With a Tracking Efficiency >90% Over an Ultra-Wide Source Range Seneke
本文提出了一种自谐振升压转换器，用于光伏能量收集，具有超宽范围源跟踪功能。
180nm CMOS, 125nW总功耗, 90%跟踪效率, 86%峰值端到端效率
JSSC 2022第6期RF & WirelessPhased Array
An Eight-Element 136–147 GHz Wafer-Scale Phased-Array Transmitter With 32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation
介绍了一种基于IF波束成形的140GHz八元素晶圆级相控阵发射器。
136–147 GHz RF带宽, 3–4 GHz IF带宽, 30–32 dBm EIRP
JSSC 2022第6期RF & WirelessPhased Array
An Eight-Element Freque ncy-Selective Acoustic Beamformer and Bitstream Feature Extractor Seungjong Lee , Student Member , IEEE, Taewook Kang , Student Member , IEEE
结合延迟求和与恒定指向性波束成形，提升语音识别抗噪性能。
40nm CMOS, 1.1mm², 84dB SNDR, 8kHz带宽
JSSC 2022第6期Clocking & PLLsPLL
An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BL
提出一种基于注入锁定环形振荡器的分数N数字锁相环，支持蓝牙低能耗频率调制。
40nm CMOS, 0.09mm², 2.76mW, -44dBc分数杂散
JSSC 2022第6期OtherNeural Network Accelerator
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology
通过分析环形注入锁定分频器的谐波生成，提出了一种新型双路径分频器，显著扩展锁定范围且不增加功耗。
8-to-101.6GHz频率范围，13.6–69.1GHz区间>20%锁定范围，5.6mW最大功耗，0.9V供电
JSSC 2022第6期Digital CircuitsNeural Network Accelerator
BitBlade: Energy-Efficient V ariable Bit-Precision Hardware Accelerator for Quantized
提出一种面积/能效优化的可变精度神经网络硬件加速器架构
28nm CMOS, 吞吐量提升7.7倍, 能效提升1.64倍
JSSC 2022第6期Other
Even-Harmonic Class- E CMOS
提出一种基于ZVS和ZDS条件的偶次谐波Class-E CMOS振荡器，具有优异的相位噪声性能。
4GHz, -152.75dBc/Hz@10MHz, 197.9dB FoM, 10.6%调谐范围
JSSC 2022第6期OtherPLL
Low-Loss Heterogeneous Integrations With High Output Power Radar Applications at W -Band Xiao Y ang , Student Member , IEEE
该研究提出了一种94GHz高性能紧凑型频率调制连续波雷达传感器设计，采用异构集成技术实现高输出功率和低损耗。
22dBm输出功率，10.2dB噪声系数，55dB动态范围，11.7cm距离分辨率
JSSC 2022第6期Clocking & PLLsVCODLL
Multi-Phase Clock Generation for Phase Interpolation With a Multi- Phase, Injection-Locked Ring Oscillator and a Quadrature DLL
提出一种基于多相注入锁定环形振荡器的高精度低抖动多相时钟生成器。
1.2V 65nm CMOS, 7GHz, 15.6mW, 58.8fs rms jitter, -252.7dB FOM
JSSC 2022第6期OtherPhased Array
Optically Synchronized Phased Arrays in CMOS
首款基于CMOS光学接收器的28GHz相控阵发射机，实现光纤同步与波束成形。
8单元28GHz相控阵，25米光纤同步
JSSC 2022第6期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，提供固态电路领域的最新研究和技术进展。
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JSSC 2022第8期Digital CircuitsNeural Network Accelerator
A3 . 8 -μW 1.5-NEF 15-G  Total Input Impedance Chopper Stabilized Amplifier With Auto-Calibrated Dual Positive Feedback in 110-nm CMOS Y
一种用于生物电位监测的自动校准双正反馈环路电容耦合斩波放大器
3.83 μW每通道，0.36 μVrms输入参考噪声，1.54噪声效率因子
JSSC 2022第8期Other
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random
提出一种基于锁存器的真随机数生成器，利用失配自补偿和亚稳态区域增强随机噪声，实现低功耗和高随机性。
0.186 pJ/bit, 0.3-1.0V, -20°C-100°C, 661μm²核心面积
JSSC 2022第8期Power ManagementLDOCharge Pump
A 0.5–1 V , −68 dB Power Supply Rejection Capacitorless Analog LDO Using V oltage-to-Time Conversion in 28-nm CMOS
提出一种基于电压-时间转换技术的模拟LDO，在低于1V电源电压下实现高电源抑制比。
28nm CMOS, 0.5-1V, -68dB PSR@1kHz, 150mA负载
JSSC 2022第8期Other
A 0.9-V 28-MHz Highly Digital CMOS Dual- RC Frequency Reference With ±200 ppm Inaccuracy From − 40 ◦Ct o8 5 ◦C
本文提出了一种用于无线传感器节点的高能效双RC频率参考，采用数字频率锁定环技术。
28-MHz, 0.9V, 142 μW, 7 ps period jitter, ±200 ppm inaccuracy
JSSC 2022第8期Other
A 16 MHz CMOS RC Frequency Reference With 90 ppm Inaccuracy From 45 Ct o8 5 C
本文介绍了一种16 MHz RC频率参考电路，采用180nm CMOS工艺，通过数字温度补偿实现±90 ppm的精度。
16 MHz, 180nm CMOS, 1.8V, 220 µA, ±90 ppm
JSSC 2022第8期RF & WirelessNeural Network Accelerator
A 207438-GHz Low Power Reconfigurable 23 Frequency Multiplier for Multiple 5G-mm-
提出一种可重构注入锁定频率倍增器，支持倍频和三次倍频模式，提高工作频率范围和功率效率。
带宽20.7-43.8 GHz，谐波抑制优于27 dB，功耗12 mW（28 GHz）和9.6 mW（39 GHz）
JSSC 2022第8期RF & WirelessPower Amplifier
A 44–64-GHz mmWave Broadband Linear Doherty PA in Silicon With Quadrature Hybrid Combiner and Non-Foster
提出一种宽带、高效且线性的毫米波Doherty功率放大器，采用正交混合器和非福斯特阻抗调谐器。
44-64 GHz, 18.5-21.5 dBm Psat, 峰值效率26%-34.7%, 6dB回退效率14%-23.2%
JSSC 2022第8期RF & Wireless
A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process Tianyu Wang ,D aW e i ,Student Member , IEEE, Ranick Ng, Gaurav Malhotra, Anup P. Jose , Member , IEEE
本文提出了一种用于下一代8K超高清电视的高速接收器，采用180nm CMOS工艺，支持5.2 Gb/s无差错通信。
180nm CMOS, 1.8V, 5.2 Gb/s, 29-dB通道损耗补偿, 120mA电流消耗
JSSC 2022第8期Digital CircuitsNeural Network Accelerator
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications Yixiong Y ang
提出一种65nm能效优化的帧间数据重用神经网络加速器，用于视频处理。
65nm CMOS, 24.7 µJ/帧（MobileNet-slim模型）
JSSC 2022第8期RF & Wireless
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller
65nm无线图像SoC支持片上DNN优化与实时计算通信权衡
65nm CMOS
JSSC 2022第8期RF & WirelessEnergy Harvesting
A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC
提出一种6.78MHz多发射器无线充电系统，通过自适应磁场加法器IC最大化系统效率。
74%功率转换效率, ±2.5%耦合系数检测误差, 576mW负载功率
JSSC 2022第8期RF & Wireless
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO
65nm CMOS工艺实现的300GHz双向相控阵收发器，采用外相位技术提升输出功率并抑制LO泄漏。
65nm CMOS, 300GHz, 四元件相控阵
JSSC 2022第8期RF & WirelessClock Generation
A Cryo-CMOS Wideband Quadrature Receiver With Frequency Synthesizer for Scalable Multiplexed Readout of Silicon Spin Qubits Ya ta o P e n g, Member , IEEE, Andrea Ruffino , Member , IEEE, Tsung-Y eh Y ang
一款用于硅基自旋量子比特读取的低温CMOS宽带正交接收器，集成频率合成器。
平均增益65dB，最小噪声系数0.5dB，中频带宽0.1-1.5GHz，镜像抑制比23dB，功耗108mW（3.5K）
JSSC 2022第8期Other
A Novel 6125 GHz Monostatic CMOS Interrogator for Batteryless Backscattering RFI
本文介绍了一种61.25 GHz单静态CMOS RFID询问器的设计与分析。
22 nm FD-SOI, 0.022 mm² active area
JSSC 2022第8期Other
A Pulsed-Coherent Lidar With Sub-10 μm Precision Li-Y
一种采用19GHz脉冲调制光载波和分段飞行时间检测的脉冲相干激光雷达，实现亚10微米精度。
6微米精度，5MSa/s采样率，2.5米距离
JSSC 2022第8期RF & WirelessLNA
A Reflectionless Receiver With Absorptive IF Amplifier and Dual-Path Noise-Canceling LNA
一种具有吸收性IF放大器和双路径噪声消除功能的反射抑制接收器
最小噪声系数3.6 dB，峰值输入三阶截点-11.7 dBm
JSSC 2022第8期Digital CircuitsNeural Network Accelerator
A Wide-Input-Range Low-Profile Adaptive Delay Compensated Hysteretic LED Driver W
一种宽输入范围、低高度的自适应延迟补偿滞后控制LED驱动器
5-100V输入, 25W输出, ±3.2%电流误差, 91.7%峰值效率, 1.8MHz频率
JSSC 2022第8期RF & WirelessNeural Network Accelerator
An Auto-Zero-Stabilized V oltage Buffer With a Quiet Chopping Scheme and Constant Sub-pA
一种采用静默斩波技术和恒定输入电流的自归零稳定电压缓冲器，实现低偏移和低噪声。
偏移0.4µV, 输入电流0.8pA, 白噪声密度14nV/√Hz
JSSC 2022第8期Power ManagementEnergy Harvesting
An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and
提出一种基于电感整流的高效压电能量收集方法，通过预充电和能量累积提高输出功率。
180nm CMOS, 3.3V V_MAX, 3.68×功率提升
JSSC 2022第8期RF & Wireless
An IR-UWB CMOS Transceiver With Extended Pulse Position Modulation Geunhaeng Lee , Junyoung Jang
一种采用E-MPPM、CC包络检测和DFH技术的低功耗高数据率IR-UWB CMOS收发器。
1.125 Gbps数据率，2米通信距离，28 mW功耗，24.9 pJ/b能效
JSSC 2022第8期Other
DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm Nimish Shah , Laura Isabel Galindez Olascoaga , Shirui Zhao
提出DPU处理器，高效执行不规则DAG，支持精度可调posit运算，显著提升性能与能效。
28nm CMOS, 0.23W, 538 GOPS/W
JSSC 2022第8期Other
Guest Editorial Message From the Outgoing Editor-in-Chief M Y THREE-YEAR term as
IEEE JSSC期刊主编卸任感言，感谢团队贡献与期刊成就
无
JSSC 2022第8期Other
Message From the Incoming Editor-in-Chief I WOULD like to thank the Solid-State
新任主编感谢前任并展望JSSC期刊的未来发展。
无
JSSC 2022第8期Other
SOUL: An Energy-Efficient Unsupervised Online Learning Seizure Detection Classifier
SOUL是一种基于随机梯度下降的无监督在线学习癫痫检测分类器，具有高灵敏度和低功耗特性。
28nm CMOS, 0.1mm², 1.5nJ/classification
JSSC 2022第8期MemoryCIM
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse Jinshan Y ue , Member , IEEE, Y
STICKER-IM是一款基于65nm工艺的存内计算神经网络处理器，采用块稀疏架构提升能效。
5.8–158 TOPS/W 平均系统能效
JSSC 2022第8期Other
Static CMOS Physically Unclonable Function Based on 4T V oltage Divider With 0.6%–1.5% Bit Instability at 0.4–1.8 V Operation in 180 nm Massimo Vatalaro , Raffaele
提出基于4T电压分压器的静态CMOS物理不可克隆函数，具有高随机性和稳定性。
0.6%比特不稳定性（1.8V, 25°C）, 0.493平均归一化PUF间汉明距离, 0.0016平均归一化PUF内汉明距离
JSSC 2022第8期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊论文的标题和摘要信息
无关键性能指标描述
JSSC 2022第9期RF & WirelessNeural Network Accelerator
A 046 GHz Receiver for Cellular and WiFi Applications
一款适用于蜂窝和WiFi应用的0.46 GHz宽带射频接收器，采用多环路架构和新技术实现低功耗高性能。
28-nm CMOS, 200 kHz to 160 MHz, 2.1–4.42 dB NF, 23–49 mW, 2.8–9.8 dBm OOB IIP3, >60 dB harmonic rejection
JSSC 2022第9期Other
A 12-GHz Reconfigurable Multicore CMOS DCO With a Time-V ariant Analysis of the I
28nm CMOS工艺的可重构多核DCO，通过时变电路分析优化相位噪声与功耗。
28nm CMOS, 10.7-14.1GHz(27%调谐范围), 6MHz分辨率, -126dBc/Hz@1MHz, 173mW, FoM -184dBc/Hz
JSSC 2022第9期Digital CircuitsNeural Interface
A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS Arda Uran , Student Member , IEEE,K e r i mT u r e, Member , IEEE, Cosimo Aprile, Alix Trouillet, Florian Fallegger , Emilie C. M. Revol , Student Member , IEEE,A z i t aE m a m i, Senior Member , IEEE, Stéphanie P. Lacour, Member , IEEE
提出一种16通道神经记录SoC，采用CHT特征提取技术，显著降低数据传输率。
10-bit 20-kS/s
JSSC 2022第9期RF & Wireless
A 164-μW 915-MHz Sub-Sampling Phase-Tracking Zero-IF Receiver With 5-Mb/s Data Rate for Short-Range Applications Y
一款915MHz超低功耗子采样相位跟踪零中频接收器，功耗仅164μW，数据速率5Mb/s。
65nm CMOS, 0.5/1V, 5Mb/s, 164μW, -69.5dBm灵敏度
JSSC 2022第9期RF & Wireless
A 24–29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM and 400-MHz 256-QAM for 5G
一篇关于65纳米CMOS工艺下24295GHz高线性相控阵收发机前端的研究论文
峰值增益25.5/14.2 dB，噪声系数4.3 dB，输出功率7.9–8.9 dBm
JSSC 2022第9期Data ConvertersEmerging MemoryCIM
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-V erify, and Temperature-Independent ADC References Wantong Li ,X i a o y uS u n , Shanshi Huang
40nm MLC-RRAM计算内存宏，支持稀疏控制和片上写验证，加速DNN推理。
40nm CMOS, 97.8 GOPS/mm², 44.5 TOPS/W
JSSC 2022第9期Clocking & PLLsCDRPAM-4
A 56-Gbs 8-mW PAM4 CDRDMUX
一种低功耗PAM4 CDRDMUX电路，具有高抖动容限和宽环路带宽。
56 Gbps, 8 mW, 160 MHz抖动传输带宽, 1 UI抖动容限@10 MHz
JSSC 2022第9期Data ConvertersFlash ADCDAC
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique Dong-Ryeol Oh ,M i n - J a eS e o
一种采用采样保持共享技术的7位两步式闪存ADC，具有高带宽和低功耗特性。
40nm CMOS, 0.9V, 3GS/s
JSSC 2022第9期Power ManagementNeural Network Accelerator
A 94.3% Peak Efficiency Adaptive Switchable CCM and DCM Single-Inductor Multiple-Output Converter With 0.03 mV/mA Low Crosstalk and 185 nA Ultralow Quiescent Tzu-Hsien Y ang, Student Member , IEEE, Y ong-Hwa Wen, Y u-Jheng Ouyang, Chun-Kai Chiu, Bo-Kuan Wu
提出一种自适应可切换CCM和DCM的单电感多输出转换器，峰值效率达94.3%。
峰值效率94.3%，负载能力3W，静态电流185nA，芯片面积1.2×1.7mm²
JSSC 2022第9期Clocking & PLLsDACPLL
A 96.9-dB-Resolution 109- μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS Elisa Sacco , Student Member , IEEE, Johan V ergauwen, Member , IEEE
一种高分辨率、低功耗的VCO传感器前端，采用二阶噪声整形和闭环结构。
180nm CMOS, 109µW, 96.9dB分辨率, 0.5ms转换时间
JSSC 2022第9期RF & WirelessTransceiver
A Current Re-Use Quadrature RF Receiver Front-End for Low Power Applications: Blixator Circuit Mohammad Barzgari , Student Member , IEEE,A l iG h a f a r i, Associate Member , IEEE
提出一种低功耗四象限RF接收前端，适用于BLE标准，功耗仅340µW。
NF 10.5dB, IIP3 -15.5dBm, 0.8V供电, 340µW功耗
JSSC 2022第9期Other
A Duty-Cycled Integrated-Fluxgate Magnetometer for
一种用于电流感测的占空比集成磁通门磁力计，实现低能耗运行
±2.4 mT测量范围，125 kHz 3-dB带宽，500-nT rms噪声，770 kS/s峰值采样率
JSSC 2022第9期RF & Wireless
A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FL
提出了一种采用双锁定接收器FLL的490GHz全集成CMOS接收器，显著提升锁定范围并降低功耗。
噪声系数51.1dB，等效噪声功率0.85pW/Hz^0.5，灵敏度-92.9dBm，功耗31.8mW@1.2V
JSSC 2022第9期Clocking & PLLsPLL
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional- N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping M
提出一种基于环形振荡器的低抖动低杂散分数-N数字锁相环，采用概率密度整形调制器和非线性抵消技术。
5.3GHz下抖动<365fs，杂散<-63dBc，功耗9.27mW
JSSC 2022第9期RF & Wireless
A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise
一种采用无源混频器优先架构的宽带噪声消除混频器，实现低噪声、宽带匹配和共享天线接口。
3.8-dB NF, 0.75-dBm out-of-band P1dB, 440-µW power consumption, -86-dBm sensitivity
JSSC 2022第9期RF & WirelessEnergy HarvestingNeural Network Accelerator
A Reconfigurable DC-DC Converter for Maximum Thermoelectric Energy Harvesting in a Battery- Powered Duty-Cycling Wireless Sensor Node Y oung-Seok Noh , Jeong-Il Seo
一种可重构DC-DC转换器，用于热电能量收集最大化。
88.5%峰值效率（SIDO模式），93.3%峰值效率（降压模式），44%电池功耗节省
JSSC 2022第9期Power ManagementSAR ADC
An 889-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter C
本文提出了一种用于高分辨率电容传感器应用的高能效噪声整形SAR电容数字转换器。
180nm CMOS, 63.3µW, 320kHz, 88.9dB SNR
JSSC 2022第9期Clocking & PLLsPLL
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based
提出一种基于功率门控注入锁定频率倍增器的超低抖动、低功耗102GHz锁相环。
65nm CMOS, 22.5mW, 0.16mm², 82fs RMS抖动(1kHz-300MHz), FoM JIT -248.2dB
JSSC 2022第9期mm-Wave
Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers W
提出三种无调谐毫米波注入锁定频率分频器，采用八阶变压器谐振器实现超宽锁定范围。
104.5%锁定范围, 5.8mW功耗, 0.9V电源
JSSC 2022第9期Other
Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing
一种抗辐射多比特触发器系统，具有嵌入式时序预错误检测功能。
ST BCD 90-nm技术实现，基于ARM Cortex M4微处理器验证
JSSC 2022第9期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，提供固态电路领域的最新研究。
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JSSC 2022第9期OtherOptical I/O
Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s
采用时间交织开关发射极跟随器扩展前端采样速率至200GS/s
57GHz输入带宽，4×32GS/s输出，3-6位精度，支持100GBd及以上PAM信号
JSSC 2022第9期RF & Wireless
W-band Scalable 2 2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCM
W波段SiGe BiCMOS工艺的2×2相控阵收发芯片组，支持高数据率无线通信。
TX单通道IF-to-RF增益26dB, OP1dB 11dBm; RX RF-to-IF增益19.5dB, 噪声系数7.7dB
JSSC 2022第10期Power Management
A0 9 -μA Quiescent Current High PSRR Low Dropout Regulator Using a Capacitive F
提出一种低静态电流高PSRR的LDO稳压器，采用电容前馈纹波消除技术。
0.18-µm CMOS, 0.9 µA静态电流, 200 mA最大负载电流, PSRR提升22 dB@1MHz
JSSC 2022第10期OtherPhased Array
A4 × 4 Steerable 14-dBm EIRP Array on CMOS at 0.41 THz With a 2-D Distributed
提出一种多层太赫兹阵列架构，实现稳健频率合成和波束成形
4×4阵列，0.416THz，14dBm EIRP
JSSC 2022第10期Power Management
A 0.033-mm 2 21.5-aF to 114.9-aF Resolution Continuous-Time  Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF
一种高分辨率连续时间电容-数字转换器，适用于大寄生电容环境。
110nm CMOS, 1.5V, 120μW, 21.5-59aF分辨率, 14.3位有效分辨率
JSSC 2022第10期Other
A 068072-THz 2-D Scalable Radiator Array With 3-dBm Radiated Power and 273-dBm E
提出一种新型2D可扩展耦合谐波振荡器阵列，实现694GHz高频辐射
694GHz下27.3dBm EIRP，-3dBm辐射功率，754mW功耗
JSSC 2022第10期Other
A 20F 2/Bit Current-Integration-Based Differential NAND -Structured PUF for Stable and V /T V ariation-Tolerant Low-Cost IoT Security
提出一种基于电流积分的差分NAND结构PUF，用于低成本物联网安全。
20F²/bit面积，0.145%/0.1V和0.120%/10°C的V/T变化容忍度
JSSC 2022第10期RF & WirelessEqualizerDRAM
A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer Dongsuk Kang, Student Member , IEEE, Jae-Woo Park , Student Member , IEEE, Injae Park, Student Member , IEEE,M i n - S uP a r k, Student Member , IEEE,X u e f a nJ i n, Member , IEEE, Kyu-Dong Hwang , Student Member , IEEE, Dae-Han Kwon
提出一种用于GDDR接口的双二进制收发器，采用自适应均衡器技术，实现21Gb/s传输速率。
21 Gb/s, 1.42 mW/Gb, 10^-12误码率
JSSC 2022第10期Data ConvertersCMOS Image Sensor
A 30.2- µVrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera Fukashi Morishita , Wataru Saito , Y oichi Iizuka, Norihito Kato
提出低噪声高灵敏度CMOS图像传感器，采用三项新技术优化电路噪声和线性特性。
55nm BSI, 8.3-Mpixel, 60-frames/s, 30.2 µVrms horizontal streak noise
JSSC 2022第10期Other
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm 2 Density With Charge-Assisted Offset Cancellation Sense Amplifier Masaya Nakano , Y oshinobu Kaneda , Satoru Nakanishi, Y asumitsu Murai, Y osuke Tashiro, Y asuhiko Taito , Tomoya Ogawa, Hidenori Mitani
40纳米嵌入式SG-MONOS闪存宏，实现200MHz高速随机读取，适用于高端MCU。
40nm CMOS, 200MHz随机读取, 7.91 Mb/mm²密度
JSSC 2022第10期RF & WirelessDACEqualizer
A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS
一款56Gb/s PAM-4光链路收发芯片组，采用非线性FFE补偿VCSEL不对称响应。
56Gb/s, -0.9dBm OMA, 1.73pJ/b(TX), 4.96pJ/b(RX), BER<10^-12@0.08UI
JSSC 2022第10期RF & Wireless
A 76-Gbits 265-GHz CMOS Receiver With WR-34 Waveguide Interface Shinsuke Hara M
一款采用40nm CMOS工艺的265GHz接收器，通过WR-3.4波导接口实现76Gbit/s无线数据传输。
76Gbit/s, 265GHz, 16QAM
JSSC 2022第10期Power Management
A BJT-Based Temperature-to-Frequency Converter With 1 C 3σ Inaccuracy From 40 C
基于BJT的温度-频率转换器，在-40°C至140°C范围内实现±1°C的3σ精度。
±1°C(3σ), 3.1μW功耗, 0.025mm²面积
JSSC 2022第10期OtherEnergy Harvesting
A Constant-Energy-Packet-Extraction-Based MPPT Technique With 98% Average Extraction Efficiency for Wide Range Generic Ambient Energy Scavenging Supporting 1000 × Source Resistance Range Priya V enugopal , Murali K. Rajendran
提出一种基于恒定能量包提取的新型MPPT技术，实现98%的平均提取效率。
50-500 mV输入电压范围，3Ω-3.5kΩ内部阻抗，81.8%峰值端到端效率
JSSC 2022第10期Clocking & PLLsPLLDLL
A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local
提出一种基于标准单元的可合成分数N锁相环，采用DTC多级注入技术，降低抖动和功耗。
1.0095-GHz输出频率, 24-MHz参考频率, 2.55 ps RMS抖动, 3.36 mW功耗
JSSC 2022第10期RF & WirelessPower Amplifier
A Millimeter-Wave CMOS Series-Doherty Power Amplifier With Post-Silicon Inter-Stage Passive V alidation
本文提出了一种用于毫米波5G应用的宽带系列Doherty功率放大器。
40nm CMOS, 20.4 dBm PSAT, 39.1%/34% PAE at 0-/6-dB PBO
JSSC 2022第10期Data ConvertersNeural Network Accelerator
A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom  ADC for Saturation-Free Closed-Loop Neural Interfaces Y
提出一种带自动增益控制的神经记录IC，动态范围提升30dB以上，噪声低至6.1μVrms。
99.5dB DR, 6.1μVrms IRN, 5kHz带宽, FoM DR 185.2dB
JSSC 2022第10期RF & WirelessNeural Interface
An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of
一种植入式神经形态传感系统，实现近传感器计算和事件驱动数据压缩。
40nm CMOS, 0.32mm², 28.2-50µW, >125×数据压缩, 4% NRMSE
JSSC 2022第10期Clocking & PLLs
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error
5nm FinFET工艺下基于频率误差反馈的片上弛豫振荡器，提升抗噪性和稳定性。
5nm FinFET, 0.9V/1.2V, 77MHz, 0.84mW, 0.0152mm²
JSSC 2022第10期Other
An Ultrasound ASIC With Universal Energy Recycling for >7-m All-Weather Metamorphic Robotic Vision Han Wu, Student Member , IEEE, Miaolin Zhang, Student Member , IEEE, Zhichun Shao , Jiaqi Guo, Student Member , IEEE,K i a nA n nN g , Senior Member , IEEE
一款支持7米全天候导航的超声波ASIC，集成64通道收发路径，能耗降低44%。
25 mm²面积，4.3 mW/通道功耗，7米障碍检测能力
JSSC 2022第10期Power Management
Arithmetic Progression Sw itched-Capacitor DCDC Converter Topology With Soft VCR
提出一种算术级数开关电容DC-DC转换器拓扑，实现软电压转换比和准对称两相电荷传输。
65nm CMOS, 1.5V输入, 0.18-1.19V输出, 400mA最大输出电流, 93.7%峰值效率
JSSC 2022第10期Data ConvertersDelta-Sigma ADCDAC
Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators
提出一种新型多环路ΔΣ调制器结构，结合MASH和SMASH优势，消除量化误差提取DAC需求。
65nm CMOS, 1.1/1.5V, 600MHz, 73.4dB SNDR, 78.3dB DR, 17.85mW
JSSC 2022第10期Clocking & PLLsCDRPAM-4
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic
提出一种基于随机相位检测器的48Gb/s PAM-4波特率CDR设计技术
48 Gb/s, 24 pJ/b, BER<10^-11, 0.24 mm^2
JSSC 2022第10期Other
FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems
提出FlashMAC架构，结合时域和频域计算，支持多比特乘法，实现高能效DNN加速。
无具体数据
JSSC 2022第10期Other
Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC)
2021年亚洲固态电路会议精选论文特刊介绍
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JSSC 2022第10期Other
High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm Jeongwon Choe , Student Member , IEEE
提出并行EMS算法，实现高吞吐量非二进制LDPC解码器。
22nm FinFET, 950 MHz, 7 Gb/s
JSSC 2022第10期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊论文分析，涉及固态电路领域的研究与进展。
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JSSC 2022第10期Digital Circuits
Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning Y ang Wang , Y ubin Qin , Dazheng Deng, Jingchuan Wei, Tianbao Chen
提出一种支持动态权重剪枝的能效边缘设备训练处理器Trainer
28nm CMOS, 20.96mm²面积
JSSC 2022第12期Data ConvertersTDC
A 10-GS/s 8-bit 2850- μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC
一款10GS/s 8位时间域ADC，采用双通道时间交织和SAR TDC技术实现高能效和小面积。
14nm FinFET CMOS, 10GS/s, 8-bit, 2850μm², 24.8-fJ/conv-step
JSSC 2022第12期OtherPower Amplifier
A 110-to-130 GHz SiGe BiCMOS Doherty Power Amplifier With a Slotline-Based
本文提出了一种基于槽线的D波段多赫蒂功率放大器，采用创新的槽线-GCPW耦合结构实现高效功率合成。
峰值输出功率22.7dBm@110GHz，功率附加效率18.7%，核心面积1.1×0.53mm²
JSSC 2022第12期Power ManagementNeural Network Accelerator
A 110/230 V AC and 15–400 V DC 0.3 W Power-Supply IC With Integrated Active Zero-Crossing Buffer Christoph Rindfleisch , Member , IEEE
一款支持AC-DC和DC-DC转换的离线电源IC，适用于物联网和智能家居等低功耗应用。
458 mW/cm³功率密度，84%峰值效率
JSSC 2022第12期OtherNeural Network Accelerator
A 1214-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier Huajun Zhang G
一款采用电容耦合斩波技术的121.4dB动态范围D类音频放大器。
121.4dB DR, -109.8dB THD+N, 93%/88%效率(8Ω/4Ω负载)
JSSC 2022第12期Power Management
A 12V/24V-to-1V PWM-Controlled DSD Converter With Delay-Insensitive and Dual-Phase Charging Techniques for Fast
提出一种12V/24V至1V PWM控制的双降压转换器，具有延迟不敏感和双相充电技术。
0.18-µm BCD, 1-MHz, 88.3% (12V-to-1V), 83.5% (24V-to-1V)
JSSC 2022第12期RF & WirelessRadar
A 140-GHz FMCW TX/RX-Antenna-Sharing Transceiver With Low-Inherent-Loss Duplexing and Adaptive Self-Interference Cancellation Xibi Chen , Student Member , IEEE,X i a n gY i , Senior Member , IEEE, Muhammad Ibrahim Wasiq Khan , Student Member , IEEE, Xingcun Li , Student Member , IEEE
提出一种140GHz FMCW雷达收发器，采用天线共享和全双工技术解决波束对准问题。
140GHz FMCW, 25.2dBm EIRP, 6.2dBm总辐射功率, 20.2dB SSB NF, 33.3dB TX-RX隔离度
JSSC 2022第12期Data ConvertersDACNeural Network Accelerator
A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm C
一款在40纳米CMOS工艺中实现的158毫瓦功耗、360MHz带宽、68dB动态范围的连续时间1-1-1滤波MASH ADC。
40nm CMOS, 1/1.1/1.8V, 5GS/s, 68dB DR, 360MHz BW
JSSC 2022第12期RF & WirelessPhased Array
A 24–30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoel ectric
本文介绍了一种24-30GHz 256单元双极化5G相控阵，支持快速波束切换和高功率效率。
200-ns波束设置时间，8-ns空中切换时间，68.5 dBm EIRP，BF-IC NF <3.9 dB
JSSC 2022第12期RF & WirelessLNA
A 266-μW Bluetooth Low-Energy BLE Receiver Featuring an N-Path Passive Balun-LNA
一款采用N路径无源巴伦-LNA的超低功耗蓝牙低能耗接收器，功耗仅266μW。
28nm CMOS, 1V/0.6V, 61dB增益, 6.1dB噪声系数, 22.5dBm OOB-IIP3
JSSC 2022第12期Data ConvertersDAC
A 28-nm 6-GHz 2-bit Continuous-Time  ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC
28纳米工艺下6GHz 2位连续时间ADC，实现101dBc THD和120MHz带宽
28nm CMOS, 6GHz, 2-bit, 101-dBc THD, 120-MHz BW, 108.8mW
JSSC 2022第12期Data ConvertersSAR ADC
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier Jia-Ching Wang , Student Member , IEEE
一种采用分布式平均相关电平移位技术的14位130MS/s流水线-SAR ADC，具有高SNDR和低功耗。
28nm CMOS, 130MS/s, 72.5dB SNDR, 0.82mW
JSSC 2022第12期Other
A 91 dB THD N Class-D Piezoelectric Speaker Driver Using Dual V oltageCurrent F
采用双电压电流反馈拓扑的D类压电扬声器驱动器，实现低功耗高线性度。
180nm BCD, 4.4A峰值电流, 122mW静态功耗, THD+N -91dB
JSSC 2022第12期Clocking & PLLsPLL
A Fractional- N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time Simone M. Dartizio
提出一种基于II型齿轮切换和自适应频率切换的快速锁定、低抖动分数-N Bang-Bang锁相环。
28nm CMOS, 0.23 mm², 1.56 µs锁定时间, 48.6 fs rms抖动, 20 mW功耗
JSSC 2022第12期RF & WirelessPLL
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET
22nm FinFET工艺下实现160Gb/s速率的全集成D波段发射器
160Gb/s 16QAM, -17dB EVM, +0.8dBm输出功率, 1pJ/b能效
JSSC 2022第12期Power ManagementBuck Converter
A Fully Integrated Multi-Phase Buck Converter With On-Chip Capacitor Dynamic Re-
提出一种全集成多相降压转换器，采用峰值谷值差分检测和动态电容重分配技术，实现高效能和高功率密度。
28nm CMOS, 400MHz/phase, 1.23W/mm², 83.7% peak efficiency, 75mV/ns DVS rate
JSSC 2022第12期Clocking & PLLsPLLVCO
A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application
提出一种用于毫米波应用的谐波混合PLL架构，实现低噪声合成器设计。
74-MHz参考频率，-250-dB PLL品质因数，88-fs rms抖动
JSSC 2022第12期Clocking & PLLsPLL
A Low-Jitter Ring-DCO-Based Fractional- N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin
提出一种基于环形振荡器的低抖动分数-N数字锁相环，通过减少DTC热噪声和动态选择相位降低抖动。
65nm CMOS, 0.139mm², 15.67mW, 5.2GHz, 188fs rms jitter, -243dB FoM
JSSC 2022第12期Power ManagementPLL
A MEMS Coriolis-Based Mass-Flow-to-Digital Converter for Low Flow Rate Sensing A
一种基于MEMS科里奥利效应的低流量数字转换器，适用于液体和气体。
0.18-μm CMOS, 1.8V, 13mW, 80μg/h/√Hz噪声基底, ±0.31mg/h零稳定性
JSSC 2022第12期Power Management
A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC–DC Conversion
提出一种单片GaN功率IC，集成栅极驱动、电平转换和温度传感技术，实现高效48V/1V直流转换。
48V/1V dc-dc转换, 5A最大负载电流, 1.1A/mm2电流密度
JSSC 2022第12期RF & Wireless
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24–71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR
一款支持5G多频段的高效能CMOS相控阵接收器
24-71GHz, 256QAM, 400MHz带宽, 36dB带外抑制
JSSC 2022第12期Clocking & PLLsDAC
A Pseudo-Virtual Ground Feedforwarding Technique Enabling Linearization and Higher Order Noise Shaping in VCO-Based  Modulators
采用伪虚拟地前馈技术的三阶VCO-ADC，实现高线性度和噪声整形。
65nm CMOS, 0.8V, 92.1-dB SNDR, 2.5-kHz带宽, 179.6-dB FoM
JSSC 2022第12期RF & WirelessPLL
A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET Barosaim Sung , Hyun-Gi Seok , Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Y oungmin Kim, Anna Y u, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sungjun Lee
首款支持5载波聚合的数字中频接收器，采用14nm FinFET CMOS技术，实现低功耗和高性能。
14nm FinFET CMOS, 1.5dB NF, +7.6dBm OOB IIP3, 2.5% EVM
JSSC 2022第12期Other
A Triboelectric Energy-Harvesting Interface With Scalable Multi-Chip-S tacked Bias-Flip and Daisy-Chained Synchronous
提出一种可扩展的多芯片堆叠偏置翻转技术，用于高效收集摩擦电纳米发电机的能量。
130V提取电压，96.4µW/cm²功率密度，70.7%峰值效率
JSSC 2022第12期Data ConvertersDelta-Sigma ADC
A V ersatile ±25-A Shunt-Based Current Sensor With ±0.25% Gain Error From − 40 ◦Ct o8 5 ◦C
一款基于分流电阻的电流传感器，具有0.25%的增益误差，适用于电池管理应用。
0.18μm CMOS, 1.8V, ±25A, ±0.25%增益误差, 265μA功耗
JSSC 2022第12期RF & WirelessSAR ADCNeural Network Accelerator
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRF
提出一种低过采样率高分辨率四阶噪声整形SAR ADC，结合EF-CRFF结构和BIL技术。
65nm CMOS, 1.2V/2V, 500kHz BW, OSR=5, 84.1dB SNDR, 133.8μW
JSSC 2022第12期Other
An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer
提出一种基于磁阻抗效应的磁力计，采用自动增益增强技术实现高带宽和低噪声。
0.18-µm CMOS, 8-pT/√Hz噪声基底, 31-kHz带宽, 96dB动态范围, 1.97mW功耗
JSSC 2022第12期RF & Wireless
An Energy-Efficient and High-Data-Rate IR-UWB Transmitter for Intracortical Neural
一种用于脑皮层神经传感的高能效、高速率IR-UWB发射器
28nm CMOS, 1.66Gbps, 5.8pJ/bit, -41.3dBm/MHz
JSSC 2022第12期Clocking & PLLs
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)
2022年IEEE国际固态电路会议精选论文特刊，涵盖RF、无线、模拟、数据转换和电源管理领域
10-GHz VCO: -138 dBc/Hz @1MHz, -190 dBc/Hz FoM, 1.2V供电
JSSC 2022第12期Other
Monolithic GaN-Based Driver and GaN Switch With Diode-Emulated GaN Technique for 50-MHz Operation and Sub-0.2-ns Deadtime Control Tz-Wun Wang, Y u-Y ung Kao, Sheng-Hsi Hung, Y ong-Hwa Wen, Tzu-Hsien Y ang
基于GaN的单片驱动器和开关采用二极管仿真技术，实现高频高效转换
50 MHz工作频率，120 V/ns转换速率，95.4%峰值效率
JSSC 2022第12期Other
New Associate Editor I
介绍Sanu K. Mathew成为IEEE JSSC期刊的新副编辑及其在数字电路和系统领域的专业背景。
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JSSC 2022第12期Other
Subranging BJT-Based CMOS Temperature Sensor With a ±0.45 ◦C Inaccuracy (3 σ)F r o m− 50◦Ct o 180◦C and a Resolution-FoM of 7.2 pJ ·K2 at 150 ◦C
提出了一种基于BJT的CMOS温度传感器，采用非线性子范围读取方案，实现高精度和低功耗。
0.18-μm CMOS, 1.5V, ±0.45°C 误差, 7.2 pJ·K² FoM
JSSC 2022第12期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE固态电路期刊的出版信息及编委会成员介绍
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JSSC 2022第12期Clocking & PLLs
Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the
本文提出一种利用串联谐振降低X波段BiCMOS VCO相位噪声的新电路拓扑。
55nm BiCMOS, 1.2V, 10GHz, -138dBc/Hz@1MHz, -190dBc/Hz FoM