JSSC 2015 — ISSCC & JSSC 知识库

JSSC 2015第1期Other

3D Ultrasonic Range ﬁnder on a Chip Richard J. Przybyla , Member , IEEE,H a o - Y e n T a n g, Student Member , IEEE , André Guedes

一种基于AlN MEMS换能器的3D超声波测距芯片，能在1米范围内精确定位目标。

0.5米距离下RMS位置误差：0.4毫米（距离轴），0.2度（x轴角度），0.8度（y轴角度）；功耗：400μW（1米范围，30fps），5μW（0.3米范围，10fps）

JSSC 2015第1期Data ConvertersCMOS Image Sensor

A0 . 1 3μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC Cyrus S. Bamji, Patrick O’Connor, Tamer Elkhatib , Associate Member , IEEE,S w a t i M e h t a, Member , IEEE

介绍了一种用于微软Kinect的512×424 TOF深度图像传感器，采用130nm CMOS工艺，支持高调制频率和灵活操作。

10μm×10μm像素, 67%调制对比度(50MHz), 0.14 A/W响应度(860nm), 8 Gb/s I/O带宽

JSSC 2015第1期Clocking & PLLs

A2 8n mD S PP o w e r e db ya nO n - C h i pL D O for High-Performance and Energy-Ef ﬁcient

28nm工艺高通Hexagon DSP，采用LDO供电，能效比提升2-3倍。

28nm CMOS, 0.60V-1.05V, 255MHz-1.24GHz, 58µW/MHz

JSSC 2015第1期Other

A4 . 9m Ω-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System Sunjoo Hong, Student Member , IEEE, Kwonjoon Lee , Student Member , IEEE, Unsoo Ha , Student Member , IEEE, Hyunki Kim, Student Member , IEEE, Y ongsu Lee, Student Member ,IEEE, Y ouchang Kim, Student Member , IEEE

一款用于早期乳腺癌检测的移动电阻抗断层成像IC，灵敏度达4.9mΩ。

0.18µm CMOS, 2.5×5mm, 53.4mW, 4.9mΩ灵敏度

JSSC 2015第1期RF & Wireless

AP o w e r - E fﬁcient Switched-Capacitor Stimulating System for Electrical/Optical Deep Brain Stimulation Hyung-Min Lee, Student Member , IEEE, Ki Y ong Kwon,S t u d e n tM e m b e r ,I E E E,W e n L i, Senior Member , IEEE

提出一种高效无线开关电容刺激系统，用于电/光深脑刺激，提升刺激效率与效果。

80.4% stimulator efficiency, ±2V capacitor pairs

JSSC 2015第1期Digital Circuits

A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications Gyeonghoon Kim, Student Member , IEEE , Kyuho Lee , Student Member , IEEE , Y ouchang Kim, Student Member , IEEE

一款用于增强现实头戴显示系统的低功耗高性能多核处理器

65nm CMOS, 1.2V, 250MHz, 381mW平均功耗, 1.22TOPS峰值性能

JSSC 2015第1期Wireline I/ODRAM

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test

12V 8Gb 8通道128GB/s高带宽HBM堆叠DRAM，采用TSV阵列和微凸点接口技术。

8Gb, 8通道, 128GB/s, 1.2V

JSSC 2015第1期Other

A 143 81 Mutual-Capacitance Touch-Sensing Analog Front-End With Parallel Drive and Differential

提出一种并行驱动的互电容触摸传感模拟前端IC，支持224个传感器通道，实现高信噪比和大尺寸触摸屏。

0.18μm CMOS, 3.3V, 240Hz报告率, 37dB SNR

JSSC 2015第1期MemorySRAM

A 14 nm FinFET 128 Mb SRAM With V Enhancement Techniques for Low-Power Applications Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Y ang, Jaeho Park, Sunghyun Park, Y ongho Kim, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sun gbong Kim, Gyuhong Kim, Jintae Kim, Y oungkeun Lee, Sang-Pil Sim, Jong Shik Y oon, K yu-Myung Choi, Hyosig Won, and

14纳米FinFET技术下的128Mb SRAM芯片，采用负位线方案和降噪技术提升性能与能效。

14 nm FinFET, 128 Mb, 0.50 V with 200 mV improvement by NBL, 0.47 V with 40 mV improvement by DNR

JSSC 2015第1期MemorySRAM

A 16 nm 128 Mb SRAM in High- Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications Y en-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Y

16纳米FinFET技术中实现128Mb SRAM，采用两种写入辅助技术降低最小供电电压。

128Mb容量，供电电压降低300mV（95%分位）

JSSC 2015第1期Power ManagementCharge PumpDRAM

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

22纳米三栅CMOS技术中实现的1Gb 2GHz嵌入式DRAM，具有128GB/s带宽

1Gb容量, 2GHz频率, 128GB/s带宽, 1.05V电压, 100µs保持时间

JSSC 2015第1期Other

A 1 TOPS/W Analog Deep Machine-Learning Engine With Floating-Gate Storage in 0.13 µm CMOS Junjie Lu, Student Member , IEEE, Steven Y oung, Student Member , IEEE,I t a m arA r e l, Senior Member , IEEE,a n d

013微米CMOS工艺下实现的1 TOPS/W能效模拟深度学习引擎，支持在线无监督学习与非易失性存储。

0.13µm CMOS, 3V, 8300 vectors/s, 11.4µW, 1×10^12 ops/s/W

JSSC 2015第1期Clocking & PLLsPLL

A 22 nm 15-Core Enterprise Xeon®

22纳米工艺15核企业级Xeon处理器，采用模块化设计和多时钟电压域以降低功耗。

22 nm工艺, 15核, 30线程, 37.5 MB共享L3缓存, 8GT/s PCIe Gen3和QPI

JSSC 2015第1期Clocking & PLLsPLL

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores Mitsuhiko Igarashi, Toshifumi Uemura, Ry o Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fu jigaya

28nm工艺高性能异构多核移动应用处理器，采用2GHz高性能核心与1GHz高效核心组合。

28nm HPM工艺, 2GHz/1GHz双频核心, 35,600 DMIPS峰值性能

JSSC 2015第1期Wireline I/ODRAM

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation Tae-Y oung Oh, Hoeju Chung, Jun-Y oung Park, Ki-Won Lee, Seunghoon Oh, Su-Y eon Doo, Hyoung-Joo Kim, ChangY ong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-S oo Ha, Y oungRyeol Choi, Y oung-Chul Cho, Y ong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwangil Park, SeongJin Jang, and Joo

一款1.0V 8Gbit LPDDR4 SDRAM，支持3.2Gbps/pin速度并集成ECC引擎，适用于亚1V DRAM核心。

1.0V, 3.2Gbps/pin, 8Gbit

JSSC 2015第1期Clocking & PLLs

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

22纳米三栅CMOS工艺下的16×16网状网络芯片，实现高吞吐量和能效优化的片上互连。

20.2 Tb/s总吞吐量，0.9 V，25°C；峰值能效18.3 Tb/s/W，430 mV，25°C

JSSC 2015第1期Digital CircuitsNeural Network AcceleratorBiosignal

A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP Nick V

一款低功耗多传感器生物医学SoC，集成高性能模拟前端和数字信号处理器，支持生物阻抗和心电图信号处理。

345 µW, 31 W/channel, 58 W/channel, 9.8 mΩ/√Hz

JSSC 2015第1期Clocking & PLLs

A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator

首款32kHz低功耗MEMS振荡器，用于替代晶体振荡器，适用于空间受限移动设备。

1.5×0.8 mm², 0.9 µA (XO), 1.0 µA (TCXO), ±3 ppm (TCXO), 1.4V-4.5V

JSSC 2015第1期Clocking & PLLs

A 460 MHz at 397 mV , 2.6 GHz at 1.3 V , 32 bits VLIW DSP Embedding F MAX Tracking Edith Beigné, Alexandre V a lentian, Ivan Miro-Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastie n Bernard, Olivier Billoint

28nm FDSOI技术下32位DSP实现宽电压范围高效能运行

28nm FDSOI, 397mV-1.3V, 460MHz@397mV, 2.6GHz@1.3V

JSSC 2015第1期Memory

A 6 mW, 5,000-Word Real-Time Speech Recognizer Using WFST Models

一款基于WFST模型的低功耗实时语音识别芯片，支持5000词库。

65nm CMOS, 6.0 mW核心功耗, 13.0%词错误率

JSSC 2015第1期Medical & BioNeural Interface

A Fully-Implantable Cochlear Implant SoC With Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation Marcus Yip, Rui Jin , Student Member , IEEE, Hideko Heidi Nakajima, Kons tantina M. Stankovic

一种全植入式人工耳蜗SoC，集成压电中耳传感器和可重构数字声音处理器。

0.18µm CMOS, 572µW (8通道模式)

JSSC 2015第1期Data ConvertersDACPLL

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolu- tion Digital V aractor Using Gated Edge

提出一种基于注入锁定的全数字PLL，采用插值相位耦合振荡器，实现最小面积和低抖动。

65nm CMOS, 900MHz, 1.7ps RMS抖动, 780µW功耗

JSSC 2015第1期Data ConvertersPipeline ADC

A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Recon ﬁgurable High-Performance Data Converters Christophe Erdmann, Donnacha Lowney, Adrian Lynam

一种由28nm FPGA和65nm混合信号芯片组成的可重构异构3D-IC，实现高性能数据转换。

500 MS/s时SNDR > 61.6 dBFS, 1.6 GS/s时SFDR > 63.8 dBc, 接口功耗0.3 mW/Gb/s

JSSC 2015第1期RF & Wireless

A Minimally Invasive 64-Channel Wireless μECoG Implant

一种低侵入性64通道无线μECoG植入系统，用于高分辨率慢性皮层信号记录与传输。

1 kS/s采样率，1.2 μV输入参考噪声，225 μW功耗，12 mW外部供电

JSSC 2015第1期Digital Circuits

A Multi-Granularity FPGA With Hierarchical Interconnects for Ef ﬁcient and Flexible Mobile Computing Fang-Li Y uan, Student Member , IEEE , Cheng C. Wang , Student Member , IEEE , Tsung-Han Y u, Student Member , IEEE, and Dejan Markovi ć, Member , IEEE

提出一种多粒度FPGA，结合细粒度逻辑块、中粒度DSP和粗粒度内核，优化移动计算的能效与灵活性。

40nm CMOS, 20.5mm², 互连面积减少3-4倍, 能效比ASIC低4-5倍

JSSC 2015第1期Medical & BioBiosignal

An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring Ye n - P o C h e n, Student Member , IEEE, Dongsuk Jeon , Student Member , IEEE, Y

一种可注射式64nW ECG混合信号SoC，用于心律失常监测。

65nm CMOS, 64nW功耗, 31nA电流消耗

JSSC 2015第1期Other

Digital Object Identi ﬁer 10.1109/JSSC.2014.2384402

无摘要提供，无法生成概要。

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JSSC 2015第1期Clocking & PLLsDRAM

Haswell: A Family of IA 22 nm Processors

介绍第四代Intel Core处理器家族Haswell，采用22nm技术，支持多种设备形态，提升性能和能效。

22nm, 102 GB/sec L4 eDRAM, 50%电池寿命延长

JSSC 2015第1期Other

INFORMATION FOR AUTHORS Content The IEEE Journal of Solid-State Circuits publishe s papers each month in the broad area of solid-state circuits with particular emphasis on transisto r-level design of inte-

IEEE JSSC期刊专注于集成电路设计，包括电路建模、技术、系统设计、布局和测试，鼓励实验验证。

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JSSC 2015第1期Other

Integrated Line Driver for Digital Pulse-Width Modulation Driven AMOLED Displays on Flex

集成扫描线驱动器采用数字脉宽调制技术驱动柔性AMOLED显示，实现高占空比和低功耗。

300kHz时钟频率，40%静态功耗降低

JSSC 2015第1期RF & Wireless

JANUARY 2015 VOLUME 50 NUMBE R 1 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE 2014 IEEE INTERNATI ONAL SOLID-STATE CIRCUITS CONFERENCE

IEEE ISSCC 2014亮点论文，涵盖处理器、数字技术、存储器及生物医学等多个领域。

7.6 Tb/s IO带宽, 28nm CMOS, 22nm

JSSC 2015第1期RF & Wireless

New Associate Editors I T IS with pleasure that I welcome Dr Ali M Niknejad

IEEE JSSC期刊欢迎新副编辑Ali M Niknejad和Vivek De，介绍其专业背景和贡献。

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JSSC 2015第1期Clocking & PLLs

Steamroller Module and Adaptive Clocking System in 28 nm CMOS

介绍AMD Steamroller模块及自适应时钟系统在28nm CMOS工艺中的物理设计实现。

28nm CMOS, 29.47mm², 236 million transistors

JSSC 2015第1期Clocking & PLLs

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated V oltage Regulation, and Resonant Clocking Eric J. Fluhr , Member , IEEE, Steve Baumgartner, David Boe rstler, John F. Bulzacchelli , Member , IEEE, Timothy Diemoz, Daniel Dreps, George En glish, Joshua Friedrich

IBM 12核POWER8处理器采用22nm SOI工艺，集成电压调节器，提供7.6Tb/s I/O带宽和90.5%能效。

22nm SOI, 7.6Tb/s I/O带宽, 90.5%峰值能效

JSSC 2015第1期MemoryFlash Memory

Three-Dimensional 128 Gb MLC V ertical NAND Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming Ki-Tae Park, Sangwan Nam, Daehan Kim, Pansuk Kwa k, Doosub Lee, Y oon-He Choi, Myung-Hoon Choi, Dong-Hun Kwak, Doo-Hyun Kim, Min-Su Kim, Hyun-Wook Park, Sang-Won Shim, Kyung-Min Kang, Sang-Won Park, Kangbin Lee, Hyun-Jun Y oon, Kuihan Ko, Dong-Kyo Shim, Y ang-Lo Ahn, Jinho Ryu, Donghyun Kim, Kyunghwa Y un, Joonsoo Kwon, Seunghoon Shin, Dae-Seok Byeon, Kihwan Choi, Student Member , IEEE, Jin-Man Han, Kye-Hyun Kyung, Jeong-Hyuk Choi, and

首次实现128Gb 3D垂直NAND闪存，采用环绕栅极结构和屏障工程材料，优化编程分布与功耗。

50MB/s写入吞吐量，3K次耐久性（嵌入式应用）；35K次耐久性，36MB/s写入吞吐量（数据中心应用）

JSSC 2015第2期RF & WirelessHigh-Speed LinkEqualizer

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology Ping-Chuan Chiang , Student Member , IEEE, Jhih-Y u Jiang, Hao-Wei Hung, Chin-Y

本文介绍了一种用于100 GbE系统的4×25 Gb/s全集成收发器芯片组，采用65 nm CMOS工艺。

65 nm CMOS, 4×25 Gb/s, 100 GbE标准

JSSC 2015第2期Power ManagementCharge PumpEnergy Harvesting

A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efﬁciency Improvement

提出一种0.13微米工艺的低压能量收集电荷泵，采用自适应死区时间和动态体偏置技术提升效率。

0.15V输入电压，效率提升17%，输出电流提升240%

JSSC 2015第2期RF & WirelessPLL

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS Hyosup Won, Taehun Y oon, Jinho Han, Joon-Y eong Lee, Jong-Hyeok Y oon, Taeh oK i m ,J e o n g - S u pL e e , Sangeun Lee

40nm CMOS工艺下实现低功耗100Gb以太网收发器IC，功耗仅0.87W。

40nm CMOS, 0.87W, 28Gb/s, BER<10^-12

JSSC 2015第2期Clocking & PLLsPLL

A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators

一种采用磁耦合技术的25 GHz快速锁定数字LC PLL，适用于低功耗有线应用。

40 nm CMOS, 25 GHz, 392 fs jitter, 64 mW power, 0.1 mm² area

JSSC 2015第2期RF & WirelessEqualizer

A 25 Gb/s 5.8 mW CMOS Equalizer

一款采用45nm工艺的低功耗25Gbps CMOS均衡器设计

25Gbps, 58mW, 1V供电, 24dB损耗补偿

JSSC 2015第2期RF & Wireless

A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5–11.5 Gb/s

本文提出了一种用于8.5-11.5 Gb/s多标准应用的功耗和面积高效的双路径接收器模拟前端设计。

40nm CMOS, 195 mW (ADC路径), 55 mW (切片路径), 0.82 mm²

JSSC 2015第2期RF & WirelessHigh-Speed Link

A 6 Gb/s Transceiver With a Nonlinear Electronic Dispersion Compensator for Directly Modulated Distributed-Feedback Lasers Kyeongha Kwon, Jonghyeok Y oon

设计了一种6 Gb/s收发器，采用非线性电子色散补偿器，用于直接调制分布式反馈激光器。

6 Gb/s, 68 mW, 1 V supply, 14.69 dB optical SNR gain

JSSC 2015第2期Other

A Cascode Miller-Compensated Three-Stage Ampliﬁer With Local Impedance Attenuation for Optimized Complex-Pole Control Min Tan , Student Member , IEEE

提出一种采用级联米勒补偿和局部阻抗衰减块的三级放大器，优化了复杂极点的频率与Q因子平衡。

0.13μm CMOS, 0.0032 mm²面积, 10.5μA静态电流, 3.49MHz单位增益频率, 0.86V/μs压摆率, 0.9μs建立时间

JSSC 2015第2期RF & Wireless

A Compact, Supply-V oltage Scalable 45–66 GHz Baseband-Combining CMOS Phased-Array Receiver

本文提出了一种紧凑型四元素相控阵接收器，采用基带移相技术，实现55 GHz频段的38%带宽。

45 nm SOI CMOS, 1.1 V/0.6 V, 30 mW/14 mW per element, 26.2 dB/20.2 dB element gain, 5.5 dB/9.8 dB minimum/maximum NF

JSSC 2015第2期Data ConvertersSAR ADCDAC

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC Hyeok-Ki Hong , Student Member , IEEE ,W a nK i m , Student Member , IEEE , Hyun-Wook Kang, Sun-Jae Park, Michael Choi, Ho-Jin Park

45nm CMOS工艺下7位1GS/s非二进制2b/周期SAR ADC，具有容错能力。

45nm CMOS, 1.25V, 1GS/s, 41.6dB SNDR, 6 ENOB, 80fJ/conversion-step, 7.2mW

JSSC 2015第2期Clocking & PLLs

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating Y oun

65nm CMOS工艺下实现的全并行非二进制LDPC解码器，支持动态时钟门控，吞吐量达1.22Gb/s。

65nm CMOS, 1.0V/675mV, 700MHz/400MHz, 1.22Gb/s/698Mb/s, 3.03nJ/b/89pJ/b/iteration

JSSC 2015第2期mm-WavePhased Array

A High-Power and Scalable 2-D Phased Array for Terahertz CMOS Integrated Systems Y

本文介绍了一种适用于毫米波和太赫兹频率的高功率辐射的二维相控阵架构。

峰值等效全向辐射功率（EIRP）为+17.1 dBm，相位噪声在1 MHz偏移频率下为-93 dBc/Hz

JSSC 2015第2期Data ConvertersDelta-Sigma ADCPLL

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8–3.5 GHz DCO

首款基于二阶频率数字转换器(FDC)的全集成数字分数PLL，替代传统TDC方案

65nm CMOS, 0.56mm², 21mW@1.0/1.2V, 123dBc/Hz@1MHz

JSSC 2015第2期Other

Cell-Based V ariable-Gain Ampliﬁers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology Hang Liu, Xi Zhu, Chirn

提出一种基于单元级联的dB线性可变增益放大器设计方法，实现高精度、低功耗和宽带宽。

0.18µm CMOS, 56dB增益范围, <0.3dB增益误差, 1.12mW功耗

JSSC 2015第2期Data ConvertersSAR ADC

Comments and Corrections C o r r e c t i o nt o“ A7 0d BD R1 0b0 - t o - 8 0M S / s Current-Integrating SAR ADC With Adaptive Dynamic Range” Badr Malki, Takaya Yamamoto, Bob V erbruggen, Piet Wambacq, and Jan Craninckx In the above paper [1], the authors r egret that the paper [3] was not mentioned in the reference list, since it has introduced the parametric ampliﬁcation using a MOS transistor; this technique is called the pas- sive ampliﬁcation in Section III-B of [1]. While being listed in the orig-

该论文是对先前发表论文的更正和补充说明，主要涉及参考文献的遗漏问题。

70 dB DR, 10 b, 0-to-80 MS/s

JSSC 2015第2期Power ManagementCharge PumpEnergy Harvesting

FEBRUARY 2015 VOLUME 50 NUMBER 2 IJSCBC ISSN 0018-9200 A 0 87 W T r a ns c e i v

IEEE JSSC 2015年2月刊收录了多篇关于低功耗电路设计、能量收集、高速串行链路接收器、多级放大器优化、数字锁相环和非二进制LDPC解码器的论文。

0.15V输入能量收集电荷泵, 40nm CMOS, 195mW/55mW双路径接收器, 2.8–3.5 GHz DCO

JSSC 2015第2期RF & WirelessLNANeural Network Accelerator

Field-Programmable LNAs With Interferer-Reﬂecting Loop for Input

介绍了一种具有干扰反射环路的可编程低噪声放大器，可动态调整增益、噪声、线性度和功耗。

NF 2.4-3.6 dB, IIP3 14.5-15 dBm, 功耗13-20.2 mW

JSSC 2015第2期Other

Hybrid Temperature Sensor Network for Area-Efﬁcient On-Chip Thermal Map Sensing Seungwook Paek , Student Member , IEEE , Wongyu Shin , Student Member , IEEE , Jaeyoung Lee ,S t u d e n tM e m b e r ,I E E E,H y o - E u nK i m, Student Member , IEEE , Jun-Seok Park , Student Member , IEEE

提出混合温度传感器网络，高效获取芯片热分布图。

无

JSSC 2015第2期Memory

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-V ector Prediction

采用基于周期的电源门控技术的非易失性内存逻辑LSI，用于高效运动矢量预测。

90 nm MTJ/MOS工艺, 300 mm晶圆制造

JSSC 2015第3期RF & Wireless

A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications Shuli Geng, Dang Liu, Y anfeng Li, Huiying Zhuo

提出一种频谱高效跳频技术，提升IR-UWB收发机链路裕量，实现500Mb/s传输速率

500Mb/s, 7.25-9.5GHz, 13.3mW@1V, 26.6pJ/bit

JSSC 2015第3期RF & Wireless

A 32–48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology

65nm CMOS工艺下采用多相位序列化技术的3.248Gbs高效能发射器

65nm CMOS, 1.2V, 32-48Gb/s, 0.4mm², 88mW, 1.8pJ/bit

JSSC 2015第3期Data ConvertersDelta-Sigma ADC

A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

40nm CMOS工艺下实现的高带宽、高能效两步VCO型Delta-Sigma ADC

40nm CMOS, 0.9V, 1.6GHz采样率, 40MHz带宽, 59.5dB SNDR, 67.7dB SFDR, 2.57mW功耗

JSSC 2015第3期RF & WirelessPhased Array

A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology Pen-Jui Peng, Pang-Ning Chen, Chiro Kao, Y u-Lun Chen

一款基于65nm CMOS技术的94GHz 3D成像雷达引擎，采用4TX4RX波束成形扫描技术和精确测距技术。

65nm CMOS, 1.2V, 960mW功耗, 3.6x2.1mm芯片面积, 2m最大测距, 1mm深度分辨率

JSSC 2015第3期RF & WirelessCDRNeural Network Accelerator

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links Woo-Seok Choi , Student Member , IEEE , Tejasvi Anand , Student Member , IEE E, Guanghua Shu , Student Member , IEEE,A m r E l s h a z l y, Member , IEEE, and Pavan

一种具有可编程输入抖动滤波功能的突发模式数字接收器，实现快速开关操作和能量比例链路。

90nm CMOS, 2.2 Gb/s, 6.1 mW, 2.77-3.87 pJ/bit, 36 mV输入灵敏度

JSSC 2015第3期RF & WirelessESD

A Low-Power CMOS Receiver for 5 GHz WLAN

设计了一种用于5 GHz WLAN的低功耗CMOS接收器，功耗仅11.6 mW。

65nm CMOS, 11.6 mW, 6 dB噪声系数, -66 dBm灵敏度, 54 Mb/s数据速率

JSSC 2015第3期RF & Wireless

A Programmable 0.7–2.7 GHz Direct Receiver in 40 nm CMOS Mikko Englund , Student Member , IEEE, Kim B. Östman , Member , IEEE, Olli Vii tala, Student Member , IEEE

40纳米CMOS工艺下0.7-2.7 GHz宽带直接ΔΣ接收器设计

40 nm CMOS, 1.1 V, 90 mW, 峰值SNDR 46 dB, NF 5.9-8.8 dB, IIP3 -2 dBm

JSSC 2015第3期Power Management

A Reconﬁgurable Dual-Output Switched-Capacitor DC-DC Regulator With Sub-Harmonic Adaptive-On-Time Control for Low-Power Applications Zhe Hua , Student Member , IEEE,a n dH o i L e e, Senior Member , IEEE

一种可重构双输出开关电容DC-DC调节器，采用子谐波自适应导通时间控制，提高效率和减少纹波。

0.35 µm CMOS, 1.1V-1.8V输入, 2V/3V输出, 12mA每输出, 89.5%效率

JSSC 2015第3期RF & Wireless

An Energy Efﬁcient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schlüßler, Holger Eisenreich, and René Schüffny

提出一种高效能多Gbits网络芯片收发器架构，适用于MPSoC中的长距离互连。

65nm CMOS 1.25V 90Gbit/s 173fJ/bit/mm, 28nm CMOS 1.05V 72Gbit/s 81fJ/bit/mm

JSSC 2015第3期Data ConvertersDAC

An Interleaved Full Nyquist High-Speed DAC Technique

提出一种采用两路交织架构的9位11GS/s DAC，实现全奈奎斯特带宽内SFDR超过50dB。

9bit 11GS/s, SFDR>50dB, IM3<-50dBc, 0.04mm², 110mW@1.0V

JSSC 2015第3期RF & Wireless

An Ultra-Low Phase Noise Class-F2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability

提出一种新型F2类振荡器，通过增强二次谐波降低相位噪声，实现191 dBcHz FoM。

65nm CMOS, 1.3V, 7.2-8.8 GHz, 139 dBc/Hz @3MHz

JSSC 2015第3期RF & WirelessLNANeural Network Accelerator

Comments and Corrections Corrections to “A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Ampliﬁer With Complementary Trans conductance Linearization” Bum-Kyum Kim, Donggu Im, Jaeyoung Choi, and Kwyro Lee In the above paper [1], articles [2]–[4] on low-noise ampliﬁer struc- tures should have been included as references. The paper [1] adopts feedback topology for lossless input matching, which was origi- nally proposed in [2] and successfully extended to CMOS LNA in [3] and [4]. The authors would like to thank Professor Leonid Belostotski for pointing out this missing information.

论文更正了低噪声放大器结构的相关参考文献。

1 GHz, 13 dB NF

JSSC 2015第3期Power ManagementProcessor/CPU

Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process

首款14nm三栅极工艺的紧凑型BJT热传感器，具有高速度和优异性能指标。

14nm tri-Gate, 0.0087mm², >50kS/sec, 1.1mW, 0.5°C分辨率

JSSC 2015第3期Other

Compact Cascadable g m-C All-Pass True Time Delay Cell With Reduced Delay V ariation

提出一种紧凑可级联的gm-C全通真延时单元，适用于1-2.5 GHz频段，具有低延迟变化和高线性度。

160 nm CMOS, 550 ps最大延迟, 13 ps步进, 1-2.5 GHz频段

JSSC 2015第3期Other

Integrated All Electrical Pulse Wave V elocity and Respiration Sensors Using Bio-Impedance

提出一种无线集成传感器，通过全电学方法监测脉搏波速度和呼吸。

0.11μm CMOS, 1.2V, 1.28mW, 5mm×2.5mm

JSSC 2015第3期RF & Wireless

MARCH 2015 VOLUME 50 NUMBER 3 IJSCBC ISSN 0018-9200 REGULAR PAPERS A Low-Power C

2015年3月IEEE JSSC期刊收录了多篇低功耗、高性能的集成电路设计论文。

多种性能指标（如：500 Mb/s IR-UWB, 191 dBc/Hz FoM）

JSSC 2015第3期Image Sensors

Selective Change Driven Vision Sensor With Continuous-Time Logarithmic Photoreceptor and Winner-Take-All Circuit for Pixel Selection Fernando Pardo, Jose A. Boluda, and Francisco V egara

选择性变化驱动视觉传感器通过高速胜者全取电路实现高效运动检测。

64×64像素阵列，2μs时间分辨率

JSSC 2015第4期Wireline I/O

340 mV–1.1 V , 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4)2 Polynomials in 22 nm Tri-Gate CMOS

一款22纳米三栅极CMOS工艺的纳米AES硬件加速器，具有低功耗和高能效特性。

1.133 GHz最大操作频率，13 mW总功耗，289 Gbps/W能效

JSSC 2015第4期Other

A4 . 7 8m m2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous

一款集成64个采集通道的神经调控SoC，面积和功耗均为同类最低。

65nm CMOS, 1.2V-1.8V, 50Hz平均放电率, 150µA差分电流

JSSC 2015第4期Other

APRIL 2015 VOLUME 50 NUMBER 4 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE 2014 SYMPOSIUM ON VLSI CIRCUITS

IEEE JSSC 2015年4月特刊聚焦VLSI电路研讨会，涵盖高速串行链路、芯片间光学连接、时钟抖动测量及GHz级PLL设计等前沿技术。

40Gb/s, 28nm CMOS, 2.7GHz-7GHz

JSSC 2015第4期Data ConvertersSAR ADCDAC

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector Yu a n Z h o u, Student Member , IEEE,B e n w e iX u, Student Member , IEEE, and Y

一款12位160MS/s的两步SAR ADC，采用背景位权校准技术，实现高转换效率和低功耗。

12位, 160MS/s, 4.96mW, 0.042mm², 86.9dB SFDR, 66.7dB SNDR

JSSC 2015第4期Data ConvertersDelta-Sigma ADCDAC

A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band Shiyu Su , Student Member , IEEE, Tu-I Tsai, Praveen Kumar Sharma , Student Member , IEEE,a n d Mike

提出一种12位1GS/s双速率混合DAC，采用8GS/s展开流水线Delta-Sigma架构，实现高动态范围。

12位分辨率，1GS/s Nyquist速率，8GS/s Delta-Sigma速率，91-76 dB SFDR（500 MHz带宽）

JSSC 2015第4期RF & WirelessEnergy Harvesting

A 13.56 MHz Wireless Power Transfer System With Reconﬁgurable Resonant Regulating Rectiﬁer and Wireless Power Control for Implantable Medical Devices Xing Li

提出一种13.56MHz无线能量传输系统，采用可重构谐振调节技术，适用于生物医学植入设备。

102mW接收功率，92.6%效率，130µs稳定时间

JSSC 2015第4期Data ConvertersDelta-Sigma ADCDAC

A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS

一款功耗优化的连续时间ΔΣ调制器，适用于超过50MHz的输入带宽。

73 dB动态范围, 80 MHz带宽, 23 mW功耗

JSSC 2015第4期Clocking & PLLsPLL

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS Chang-Hyeon Lee, Lindel Kabalican, Y an Ge, Hendra Kwantono, Greg Unruh, M

提出一种28nm CMOS分数-N LC-PLL，采用多层金属技术实现面积缩减，频率范围2.7-7 GHz，功耗14 mW。

28nm CMOS, 2.7-7 GHz, 14 mW, RMS jitter 0.56 ps (整数模式), 1.1 ps (分数模式)

JSSC 2015第4期Data ConvertersCMOS Image Sensor

A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit Shunsuke Okura, Osamu Nishikido, Y usuke Sadanaga, Y asuhiro Kosaka, Nori hiko Araki, Kazuhiro Ueda, and

一款用于工业应用的37M像素、1300fps、50G像素高速读出CMOS图像传感器

15.3mm×8.6mm光学尺寸, 3.7M像素, 1300fps, 5.0G像素/s读出速率, 1H读出时间1.0μs

JSSC 2015第4期Power ManagementPLL

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Ampliﬁer-Based TDC Ahmed Elkholy , Student Member , IEEE , Tejasvi Anand , Student Member , IEEE , Woo-Seok Choi , Student Member , IEEE ,A m rE l s h a z l y,M e m b e r, IEEE ,a n d Pavan

一种采用高分辨率TDC和真分数分频器的低噪声宽带数字分数N锁相环。

65nm CMOS, 3.7mW, 4.5GHz输出频率, 3MHz带宽, 490fs积分抖动

JSSC 2015第4期RF & WirelessHigh-Speed LinkEqualizer

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

本文介绍了一种40 Gb/s的串行链路收发器，采用28 nm CMOS工艺，优化了芯片间通信并补偿20 dB信道损耗。

28nm CMOS, 40 Gb/s, 23.2 mW/Gb/s, 0.27 UI水平眼图开口, 120 mV垂直眼图开口

JSSC 2015第4期Clocking & PLLsPLLVCO

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method Romesh Kumar Nandwana , Student Member , IEEE , Tejasvi Anand , Student Member , IEEE , Saurabh Saxena , Student Member , IEEE , Seong-Joong Kim ,S t udent Member , IEEE, Mrunmay Talegaonkar , Student Member , IEEE , Ahmed Elkholy , Student Member , IEEE , Woo-Seok Choi , Student Member , IEEE ,A m rE l s h a z l y, Member , IEEE ,a n d Pavan

提出混合相位/电流模式相位插值器(HPC-PI)以提升基于环形振荡器的分数N锁相环相位噪声性能。

65nm CMOS, 4.25至4.75GHz, 104 dBc/Hz带内相位噪声, 1.5 ps集成抖动, 2.4 mW/GHz能效, FoM 225.8 dB

JSSC 2015第4期Other

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS Chen Sun ,S t u d e n tM e m b e r ,I E E E, Michael Georgas, Jason Orcutt, Benjamin M oss, Member , IEEE, Yu - H s i n C h e n, Student Member , IEEE, Jeffrey Shainline, Mark Wade, Karan Mehta, Kareem Nammari, Erman Timurdogan , Student Member , IEEE, Daniel Miller, Ofer Tehar-Zahav, Zvi Sternberg, Jonathan Leu

在0.18µm体CMOS工艺中实现单片集成硅光互连芯片，支持5Gb/s数据传输。

350fJ/bit发射能耗，71µApp接收灵敏度(BER=10^-12)，5Gb/s速率，45Gb/s波分复用

JSSC 2015第4期RF & Wireless

A Power-Harvesting Pad-Less Millimeter-Sized Radio

一款65nm CMOS工艺的无焊盘毫米波无线供电单芯片收音机，适用于物联网和无线标签应用。

3.7mm x 1.2mm芯片尺寸，50cm通信距离，>12Mbps数据速率，待机功耗<1.5µW

JSSC 2015第4期Digital Circuits

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding Phil Knag , Student Member , IEEE, Jung Kuk Kim , Student Member , IEEE, Thomas Chen , Student Member , IEEE

本文介绍了一种用于图像和视频特征提取的ASIC芯片，具备片上学习功能。

65nm CMOS, 1.0V, 310MHz, 1.24 Gpixel/s

JSSC 2015第4期Other

A System Based on Capacitive Interfacing of CMOS With Post-Processed Thin-Film MEMS Resonators Employing Synchronous Readout for Parasitic Nulling Liechao Huang , Student Member , IEEE , Warren Rieutort-Louis , Student Member , IEEE , Alexandra Gualdino, Laura Teagno, Yingzhe Hu ,S t u d e n tM e m b e r ,I E E E

提出基于电容耦合和同步读出的CMOS与薄膜MEMS谐振器接口方案，提升高频谐振峰检测能力。

>20 dB SNR

JSSC 2015第4期Memory

A V ocabulary Forest Object Matching Processor With 2.07 M-V ector/s Throughput and 13.3 nJ/V ector Per-V ector Energy for Full-HD 60 fps Video Object Recognition Kyuho Jason Lee , Student Member , IEEE , Gyeonghoon Kim , Student Member , IEEE

提出一种基于词汇森林的高效对象匹配处理器，通过集成片上数据库消除外部内存访问，显著提升处理速度和能效。

65nm CMOS, 2.07 M-vector/s throughput, 13.3 nJ/vector per-vector energy, 95.7% matching accuracy

JSSC 2015第4期Other

An Impedance and Multi-Wavelength Near-Infrared Spectroscopy IC for Non-Invasive Blood Glucose Estimation Kiseok Song , Student Member , IEEE, Unsoo Ha , Student Member , IEEE

提出了一种结合阻抗光谱和多波长近红外光谱的IC，用于高精度无创血糖估计。

0.18 µm CMOS, 38 mW峰值功耗, 12.1 mW最大辐射发射功率

JSSC 2015第4期RF & Wireless

An RF Receiver for Intra-Band

一种用于带内载波聚合的高效射频接收器架构，采用单接收路径和单合成器。

45 nm CMOS, 70 dB 图像抑制比, 3.8 dB 噪声系数, 15 mW 功耗

JSSC 2015第4期Other

Digital Object Identiﬁer 10.1109/JSSC.2015.2415551

无摘要

JSSC 2015第4期Data Converters

Dynamic Architecture and Frequency Scaling in 0.8–1.2 GS/s 7 b Subranging ADC Kentaro Y oshioka, Member , IEEE, Ryo Saito, Takumi Danjo, Sanroku

提出动态架构与频率缩放技术，实现高速ADC的超线性功耗缩放。

65nm CMOS, 1220 MS/s, SNDR 36.2 dB, 峰值FoM 85 fJ/conv.

JSSC 2015第4期Power ManagementBuck ConverterVCO

High Frequency Buck Converter Design Using Time-Based Control Techniques Seong Joong Kim , Student Member , IEEE , Qadeer Khan , Student Member , IEEE , Mrunmay Talegaonkar

采用时间控制技术设计高频降压转换器，实现小面积低功耗。

180nm CMOS, 0.6-1.5V输出, 10-25MHz开关频率, 94%峰值效率

JSSC 2015第4期Other

Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits T HIS S

2014年VLSI电路研讨会精选论文介绍，涵盖集成电路设计和技术开发的前沿成果。

无

JSSC 2015第4期RF & WirelessHigh-Speed Link

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs Joshua Liang, Moha mmad Sadegh Jalali , Student Member , IEEE

通过片上测量技术实现亚皮秒级时钟和数据抖动的精确测量。

RMS随机抖动0.85ps至1.89ps，正弦抖动0.89ps至5.1ps，误差小于0.6ps

JSSC 2015第5期Power ManagementVCOTDC

A0 . 2 2p srms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter Wonsik Y u, Student Member , IEEE , KwangSeok Kim , Student Member , IEEE ,a n d

提出一种四阶ΔΣ时间数字转换器，实现高分辨率和宽信号带宽。

65nm CMOS, 0.22ps rms噪声, 15MHz带宽, 300MS/s, 6.24mW

JSSC 2015第5期Power Management

A -Hopping Reconﬁgurable RGB LED Driver With Automatic Detection and Predictive Peak

提出一种低成本可重构RGB LED驱动芯片，支持自动检测和快速电压跳变。

0.35µm CMOS, 198 ns/V跳变速度, 1MHz开关频率, 8.6倍能效提升

JSSC 2015第5期RF & WirelessLNA

A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS Hajir Hedayati, Wing-Fat Andy Lau, Nams oo Kim, Vladimir Aparin, and Kamra n Entesari , Member , IEEE

一款高性能宽带接收器，采用双路径设计和新型滤波技术，显著提升线性度和噪声性能。

2 GHz频率下1.8 dB NF，50 dB增益，+5 dBm OOB IIP3，36 mW功耗

JSSC 2015第5期RF & Wireless

A 25 dBm Outphasing Power Ampliﬁer With Cross-Bridge Combiners

本文提出了一种采用交叉桥接合器的25 dBm D类异相功率放大器，显著提高了回退效率。

55%峰值功率附加效率（900 MHz），45%（2.4 GHz），-53 dBc ACPR（DPD后）

JSSC 2015第5期Clocking & PLLsVCOClock Generation

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance

本文介绍了一种52 GHz频率合成器，采用二次谐波提取技术，实现了46.4–58.1 GHz的频率范围。

46.4–58.1 GHz频率范围，相位噪声低于–118 dBc/Hz，功耗66 mW，1 V电源

JSSC 2015第5期Power ManagementPLL

A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter Kuba Raczkowski, Nereo Markulic , Student Member , IEEE, Benjamin

28nm CMOS工艺下实现的高性能分数分频子采样锁相环，具有低相位噪声和宽调谐范围。

28nm CMOS, 0.9V/1.8V供电, 13mW功耗, 280fs RMS抖动, -104dBc/Hz带内相位噪声

JSSC 2015第5期mm-Wave

A Compact 77% Fractional Bandwidth CMOS Band-Pass Distributed Ampliﬁer With Mirror-Symmetric Norton Transforms V enumadhav Bhagavatula , Mazhareddin Taghivand , Student Member , IEEE ,a n d Jacques

本文提出了一种在40纳米CMOS工艺中实现的高分数带宽毫米波带通分布式放大器设计。

34 mW功耗，7 dB功率增益，24-to-54 GHz频率范围，77%分数带宽

JSSC 2015第5期RF & Wireless

A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS Brecht François , Student Member , IEEE

本文介绍了一种全集成功率检测器，用于监测5 GHz RF PA的输出功率，具有高精度和宽动态范围。

±0.5 dB精度，32.5 dB动态范围，VSWR 2.8:1

JSSC 2015第5期RF & Wireless

A Fully Integrated Wideband FM Transceiver for Low Data Rate

一款全集成宽带FM收发器，适用于低数据速率自主无线传感系统。

90nm RF-CMOS, 1V, 100 kb/s, 6 nJ/bit

JSSC 2015第5期RF & WirelessNeural Network Accelerator

A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching Anders Nejdel , Student Member , IEEE , Henrik Sjöland , Senior Member , IEE E,a n d Markus Törmänen , Senior Member , IEEE

一种采用噪声消除技术的无电感频率选择性输入匹配无线接收器前端，工作频率0.7至3.8 GHz。

65nm CMOS, 1.2V, 22.8–34.9 mA, 噪声系数1.6-3.2 dB, IIP2 > +75 dBm, IIP3 > +1 dBm

JSSC 2015第5期RF & WirelessDelta-Sigma ADC

A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications Rahmi Hezar

本文提出了一种基于PWM的全数字发射机，采用45nm CMOS工艺，实现高效能和高线性度。

23 dBm输出功率，47% PAE，20 MHz OFDM信号下23% PAE

JSSC 2015第5期RF & Wireless

A Wideband Highly Integrated and Widely Tunable Transceiver for In-Band Full-Duplex Communication Dong Y ang, Hazal Yüksel ,S t u d e n tM e m b e r ,I E E E

一款宽带高集成度可调谐收发器，支持同频全双工操作。

0.1–1.5 GHz频率调谐范围，噪声系数低至5.5 dB，发射功率达7.1 dBm

JSSC 2015第5期RF & WirelessPLL

An IEEE 802.15.6 Standard Compliant 2.5 nJ/Bit Multiband WBAN Transmitter Using Phase Multiplexing and

本文介绍了一种符合IEEE 802.15.6标准的多频带WBAN发射器，采用注入锁定技术实现低功耗π/4 DQPSK调制。

2.4 mW功耗，10 dBm RF输出功率，2.5 nJ/bit能效，1.2 Mbps数据速率，3.21% RMS EVM

JSSC 2015第5期RF & WirelessPower AmplifierNeural Network Accelerator

An Integrated CMOS Passive Self-Interference Mitigation Technique for FDD Radios Tong Zhang , Student Member , IEEE, Apsara Ravish Suvarna, V

提出一种用于FDD无线电的集成无源自干扰抑制技术，通过四端口消除器实现发射泄漏抑制。

40nm CMOS, 5MHz带宽, >20dB TX泄漏抑制

JSSC 2015第5期Medical & Bio

Capacitive Proximity Communication With Distributed Alignment Sensing for Origami Biomedical Implants

本文提出了一种用于Origami植入物的电容式邻近互连方案，通过分布式对齐感应实现芯片间通信。

10–60 Mbps, 0.180 pJ/bit

JSSC 2015第5期MemoryEmerging Memory

Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology

提出一种高密度1TNR RRAM阵列架构，解决互连线压降问题并验证可行性。

未明确提及

JSSC 2015第5期RF & WirelessPower Amplifier

Design of A Transformer-Based Reconﬁgurable Digital Polar Doherty Power Ampliﬁer Fully Integrated in Bulk CMOS Song Hu , Student Member , IEEE

本文设计了一种基于变压器的可重构数字极坐标Doherty功率放大器，采用65nm CMOS工艺，实现了高输出功率和效率。

65nm CMOS, +27.3 dBm峰值输出功率, 32.5%峰值效率, 2.1 mm²面积, 24.9%带宽

JSSC 2015第5期Other

Digital Object Identifier 10.1109/JSSC.2015.2426891

无摘要提供，无法生成概要

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JSSC 2015第5期Clocking & PLLsDLL

Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power

提出一种基于漏电流的数字控制振荡器和快速重锁MDLL，用于超低功耗传感器平台。

65nm CMOS, 423nW@3.2MHz, FoM=0.132nW/MHz

JSSC 2015第5期OtherPhased Array

Dynamic Polarization Control

实现首个集成动态极化控制的105.5 GHz CMOS SOI相控阵辐射器。

105.5 GHz, 32 nm CMOS SOI, 7.8 dBm EIRP, 0.9 mW总辐射功率

JSSC 2015第5期Other

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs Ryu Ogiwara

针对64 Mb和128 Mb链式FeRAM的高可靠性参考位线偏置设计，通过改进带隙基准电路和电梯电路，显著提升信号窗口。

信号窗口提升22 mV（64 Mb）和40 mV（128 Mb），工作电压范围1.5 V ±0.2 V

JSSC 2015第5期Other

INFORMATION FOR AUTHORS Content The IEEE Journal of Solid-State Circui ts publishes papers each month in the b road area of solid-state circuits with particular emphasis on transisto r-level design of inte-

IEEE JSSC期刊论文投稿指南，涵盖集成电路设计与验证要求。

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JSSC 2015第5期RF & Wireless

Introduction to the Special Section on the 2014 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

2014年IEEE射频集成电路研讨会精选论文，涵盖无线收发器、射频前端、毫米波设计等。

7 dB功率增益，24–54 GHz，34 mW，IIP3 11 dBm，噪声系数6.2 dB

JSSC 2015第5期RF & Wireless

MA Y 2015 VOLUME 50 NUMBER 5 IJSCBC (ISSN 0018-9200) SPECIAL SECTION ON THE 2014 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM

IEEE JSSC 2015年第五期特刊聚焦射频集成电路（RFIC）创新设计

未明确提及

JSSC 2015第5期MemorySRAM

SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

提出一种动态管理能量与质量权衡的电压可调SRAM，适用于容错应用，实现35%的节能。

28 nm CMOS 32 kb SRAM, 220 mV低于基准电压

JSSC 2015第5期Other

The IEEE J OURNAL OF SOLID-STATE CIRCUITS is published by the IEEE Solid-State Circuits Society. All IEEE members ar e eligible for membership and will receive this J OURNAL

IEEE JSSC期刊的出版信息及编委会成员介绍

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JSSC 2015第6期Clocking & PLLsVCO

85-to-127 GHz CMOS Signal Generation Using a Quadrature VCO With Passive Coupling and Broadband Harmonic Combining for Rotational Spectroscopy Jing Zhang , Student Member , IEEE , Navneet Sharma

采用65nm CMOS工艺的85至127 GHz信号生成器，通过无源耦合和四次谐波倍频实现宽带信号生成。

65nm CMOS, 1.5V, 30–45 mW, 15至23 dBm输出功率, 108至102 dBc/Hz相位噪声

JSSC 2015第6期RF & Wireless

A4 5 W Injection-Locked FSK Wake-Up Receiver With Frequency-to-Envelope Conversion for Crystal-Less Wireless Body

一款用于无线体域网的超低功耗FSK唤醒接收器，采用0.18μm CMOS工艺，功耗仅45μW。

0.18μm CMOS, 0.7V, 312kb/s, 45μW

JSSC 2015第6期Data ConvertersSAR ADCDAC

A 0.003 mm 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching Jen-Huan Tsai, Hui-Huan Wang, Y ang-Chi Y en, Chang-Ming Lai, Y en-Ju Chen, Po-Chuin Huang, Ping-Hsuan Hsieh, Hsin Chen, and Chao-Cheng Lee

本文提出了一种28nm CMOS工艺下的10位240MS/s SAR ADC，采用数字误差校正和DAC切换技术提升性能。

28nm CMOS, 1V, 240MS/s

JSSC 2015第6期Data ConvertersSAR ADCDAC

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR

本文提出了一种低功耗、高分辨率的SAR ADC，采用多种技术提升SNR和SFDR。

42 mW, 50 MS/s, 13 bit, 71 dB SNDR, 85 dB SFDR

JSSC 2015第6期Data ConvertersTime-Interleaved ADCPLL

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope

提出恒定斜率充电法实现高线性度数字时间转换器（DTC）。

65nm CMOS, 10 bit DAC, 19 ps to 189 ps delay, 19 fs to 185 fs resolution, 0.17% INL at 189 ps, 1.8 mW

JSSC 2015第6期Other

A High-V oltage Class-D Power Ampliﬁer With Switching Frequency Regulation for Improved High-Efﬁciency Output

设计了一种高效率高压D类功放，通过自适应调节开关频率优化全功率范围效率。

93% efficiency at 45 W, efficiency down to 4.5 W and 0.45 W

JSSC 2015第6期RF & Wireless

A Noise-Cancelling Receiver Resilient t oL a r g eH a r m o n i cB l o c k e r s

提出一种增强型噪声消除接收器架构，提升对谐波干扰的抵抗能力。

28nm CMOS

JSSC 2015第6期RF & WirelessEnergy Harvesting

An 86% Efﬁciency 12 µW Self-Sustaining PV Energy Harvesting System With Hysteresis Regulation and Time-Domain MPPT for IOT

提出一种用于物联网节点的86%效率、12µW自持光伏能量收集系统

12µW功耗，86%峰值效率，0-21µW输出功率

JSSC 2015第6期RF & WirelessCMOS Image Sensor

An Energy/Illumination-Adaptive CMOS Image Sensor With Reconﬁgurable Modes of Operations Jaehyuk Choi, Seokjun Park, Jihyun Cho, and Euisik Y oon

一种能量光照自适应的CMOS图像传感器，具有可重构操作模式，适用于无线传感器节点。

99.2 dB动态范围

JSSC 2015第6期Data ConvertersPipeline ADC

An Ultra-Low-V oltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Ampliﬁers

本文介绍了一种0.55V、7位、160MS/s的流水线ADC，采用动态放大器和插值架构提升性能。

90nm CMOS, 0.55V, 160MS/s, 2.43mW, ENOB 6.0 bits

JSSC 2015第6期Power Management

Design of On-Chip Gate Drivers With Power-Efﬁcient High-Speed Level Shifting and Dynamic Timing Control for High-V oltage Synchronous Switching Power Converters Zhidong Liu , Student Member , IEEE

设计高效高速电平转换的片上栅极驱动器，用于高压开关电源转换器。

0.5µm 120V CMOS, 5V信号转换至100V/40V, FoM提升10倍/2.9倍

JSSC 2015第6期RF & Wireless

JUNE 2015 VOLUME 50 NUMBER 6 IJSCBC ISSN 0018-9200 Ne w A s s o c i a te Edi t o

IEEE JSSC 2015年6月刊收录了多篇关于高性能接收器、ADC和信号生成的论文。

如：50 MS/s 13位SAR ADC, 85-to-127 GHz信号生成

JSSC 2015第6期MemoryFlash Memory

Layer-Aware Program-and-Read Schemes for 3D Stackable V ertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process V ariations Chun-Hsiung Hung

该论文提出了三种电路级技术来解决3D垂直栅极NAND闪存的跨层工艺变异问题。

8层3DVG NAND，200mV跨层失配，编程周期减少25%，SM损失减少56%

JSSC 2015第6期Data ConvertersProcessor/CPU

V ariation-Tolerant, Ultra-Low-V oltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique Seongjong Kim and

提出一种超低电压微处理器设计，通过低开销EDAC技术提升电压可扩展性和容错能力。

65nm, 42%最低能耗降低, 38%能耗降低, 2.3倍吞吐量提升

JSSC 2015第7期Wireline I/OEqualizer

A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS Shayan Shahramian and Anthony

提出一种混合IIR和离散时间DFE的10Gb/s低功耗接收器设计。

28nm CMOS, 150mVpp-diff, 10Gb/s, 4.1mW, 24dB信道损耗

JSSC 2015第7期Data ConvertersPipeline ADC

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration

一种采用分离ADC校准技术的12位195MS/s流水线ADC，实现82dB SFDR和53mW功耗。

12bit, 195MS/s, 82dB SFDR, 64.8dB SNDR, 53mW, 1V supply

JSSC 2015第7期Power ManagementNeural Network Accelerator

A 28 nm FDSOI Integrated Reconﬁgurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efﬁciency Avishek Biswas, Student Member , IEEE , Yildiz Sinangil , Student Member , IEEE ,a n d

28nm FDSOI工艺的可重构开关电容升压DC-DC转换器，峰值效率88%

28nm FDSOI, 1V输入, 1.2-2.4V输出, 10µA-500µA负载, 88%峰值效率

JSSC 2015第7期RF & WirelessPhased Array

A 30/35 GHz Dual-Band Transmitter for Phased Arrays in Communication/Radar Applications

一款用于通信/雷达相控阵系统的30/35 GHz双频段发射机，具有高相位和幅度分辨率。

0.25 µm BiCMOS, 3.3 V, 222–241 mA, +14.5 dBm

JSSC 2015第7期Other

A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass

本文提出了一种基于超级源极跟随器拓扑的4阶低通模拟滤波器，采用0.18 µm CMOS工艺实现，具有33 MHz截止频率和70 dB SNR。

33 MHz截止频率，70 dB SNR，770 µA总电流，1.8 V电源电压

JSSC 2015第7期mm-Wave

A 40–67 GHz Power Ampliﬁer With 13 dBm and 16% PAE in 28 nm CMOS LP

提出一种针对毫米波宽带功率放大器的设计方法，实现高效率和宽带宽。

28nm CMOS, 13 dBm, 16% PAE, 40–67 GHz

JSSC 2015第7期Clocking & PLLsPLLNeural Network Accelerator

A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process Abhirup Lahiri, Nitin Gupta, An and Kumar, and

本文提出一种低功耗CP-PLL，采用双路径环路滤波器减少电阻噪声，集成抖动530 ps。

28nm FD-SOI, 1.62V模拟供电, 0.65V数字供电, 600 µA电流, 530 ps集成抖动

JSSC 2015第7期Power ManagementNeural Network Accelerator

A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System Sechang Oh, Student Member , IEEE, Y

一种用于植入式压力传感的双斜率电容-数字转换器，具有高能效和紧凑设计。

180nm CMOS, 3.6V, 44.2dB SNR, 6.4ms转换时间, 110nW功耗

JSSC 2015第7期Clocking & PLLsVCONeural Network Accelerator

A Programmable Frequency Multiplier-by-29 Architecture for Millimeter Wave Applications Clément Jany, Alexandre Siligaris, Jose

提出一种毫米波频率29倍频器，用于生成IEEE 802.15.3c标准的60 GHz频段信号。

40nm CMOS, 32mW, 0.07mm², 104dBc/Hz@1MHz offset

JSSC 2015第7期Clocking & PLLs

A Thermistor-Based Temperature Sensor for a Real-Time Clock With 2 ppm

基于多晶硅热敏电阻的温度传感器设计，用于实时时钟频率补偿

0.12°C精度，2ppm频率稳定性，0.09mm²面积，31μW功耗

JSSC 2015第7期RF & WirelessPLL

A WCDMA/WLAN Digital Polar Transmitter With Low-Noise ADPLL, Wideband PM/AM Modulator, and Linearized PA

本文提出了一种集成低噪声ADPLL和宽带PMAM调制器的WCDMA/WLAN数字极化发射机。

1 dB输出压缩点22.8 dBm，系统效率27.6%，64-QAM信号EVM 4%

JSSC 2015第7期RF & Wireless

A mm-Precise 60 GHz Transmitter in 40 nm CMOS for Discrete-Carrier Indoor Localization Paramartha Indirayanti, Student Member , IEEE , Tuba Ayhan , Student Membe r , IEEE, Marian V erhelst, Member , IEEE,W i m D e h a e n e, Senior Member , IEEE

40纳米CMOS工艺下实现毫米级精度的60GHz室内定位发射机

40nm CMOS, 0.9V, 5.4μs符号持续时间, 0.7-2.7mm精度, 5m测量距离

JSSC 2015第7期RF & WirelessEqualizer

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity Harald Kröll, Student Member , IEEE , Stefan Zwicky, Benjamin Weber, Chri stoph Roth, David Tschopp

支持接收分集的GSM/EDGE基带ASIC，满足3GPP最严苛的下行链路性能要求。

130nm CMOS, 3.9-14mW功耗, 112dBm灵敏度

JSSC 2015第7期Clocking & PLLs

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced

一款32nm CMOS工艺的全数字电源噪声分析器，具有20 GHz采样带宽和1 mV分辨率。

32nm CMOS, 20 GHz采样带宽, 1 mV分辨率

JSSC 2015第7期Clocking & PLLs

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering Marco Garampazzi, Student Member , IEEE, Paulo M. Mendes , Senior Member , IEEE,N i c o l aC o d e g a, Member , IEEE

提出一种互补p-n类B振荡器，通过磁耦合二次谐波尾谐振器优化相位噪声，实现195.6 dBc/Hz的峰值FoM。

195.6 dBc/Hz FoM, 6.3 mW功耗, 7.35-8.4 GHz振荡频率

JSSC 2015第7期Other

Area Efﬁcient Integrated Gate Drivers Based on High-V oltage

提出三种全集成自举电路方案，通过高压电荷存储减少面积并提升性能。

电压跌落<1V, 电容75.8pF+18.9pF

JSSC 2015第7期Clocking & PLLsPLLProcessor/CPU

Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC

本文介绍了一种用于3 GHz 64位ARMv8 8核SoC的时钟分布与同步网络设计。

40nm CMOS, 3.0 GHz, 0.8 ps/mV rms, 9 ps period jitter and skew

JSSC 2015第7期Other

Comments and Corrections Corrections to “A Power-Efﬁcient Sw itched-Capacitor Stimulating Syste mf o r Electrical/Optical Deep -Brain Stimulation” Hyung-Min Lee, Ki Y ong Kwon, Wen Li, Bryan Howell, Warren M. Grill, and Mays am Ghovanloo Two authors were omitted in the above paper [1]. We regret the error. Bryan Howell and Warren M. Grill should be the four t ha n dﬁ f t ha u -

该论文对先前发表的论文进行了作者名单的更正。

无

JSSC 2015第7期Power ManagementNeural Network Accelerator

Fully Integrated Wide Input V oltage Range Capacitive DC-DC Converters: The Folding

提出改进型Dickson转换器实现宽输入范围电容式DC-DC转换，采用折叠结构降低动态损耗。

90nm工艺, 50mW输出功率, 峰值效率76.6%(2:1模式), 平均效率>60%

JSSC 2015第7期RF & Wireless

Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC)

IEEE JSSC特刊介绍第40届欧洲固态电路会议精选论文，涵盖模拟电路、数据转换器、RF和毫米波构建模块等领域。

33 MHz截止频率，18 dBm-IIP3，770 μA总电流，1.8 V电源电压

JSSC 2015第7期Other

JUL Y 2015 VOLUME 50 NUMBER 7 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE 40TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)

本文介绍了第40届欧洲固态电路会议的特刊及相关论文。

33 MHz, 70 dB SNR, 88%峰值效率

JSSC 2015第7期Power Management

Single-Inductor Quad-Output Switching Converter With Priority-Scheduled Program for Fast Transient Response and Unlimited Load Range in 40 nm CMOS Technology Wei-Chung Chen, Student Member , IEEE, Yi-Ping Su, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin

提出一种优先级调度程序的单电感四输出开关转换器，优化能量分配并提升性能。

40nm CMOS, 0.2%交叉调节, 15μs瞬态响应, <30mV纹波

JSSC 2015第8期RF & WirelessVCO

350 mV , 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS Ankur Guha Roy , Student Member , IEEE , Siladitya Dey , Student Member , IEEE , Justin B.

提出了一种在65nm CMOS工艺下实现的新型低电压增强摆幅Class-D VCO，工作频率5GHz，最低供电电压300mV。

65nm CMOS, 0.35V, 5GHz, 137.1dBc/Hz@3MHz, 2.1mW

JSSC 2015第8期Medical & Bio

AUGUST 2015 VOLUME 50 NUMBE R 8 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE IEEE 2014 CUSTOM INTEGRA TED CIRCUITS CONFERENCE Introduction to the Special Issue on the IEEE 2014 Custom Integrated Circuits Conference . . . . A. Mazzanti and E. Alon 1739 A mm-Sized Implantable Medical Device (IMD) With Ultras onic Power Transfer and a Hybrid Bi-Directional Data

IEEE JSSC 2015年8月特刊聚焦低功耗无线应用、医疗设备及高性能音频放大器等前沿技术。

如：55nm CMOS, 105 dB SNR, 0.0031% THD+N

JSSC 2015第8期RF & Wireless

A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS

20nm CMOS FPGA中嵌入的0.5-16.3 Gb/s全自适应无线收发器

28 dB损耗背板16.3 Gb/s BER<10^-12

JSSC 2015第8期RF & WirelessBoost ConverterEnergy Harvesting

A 10 mV-Input Boost Converter With Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting With 220 mV Cold-Start and 14.5 dBm, 915 MHz RF Kick-Start

130nm CMOS工艺的10mV输入升压转换器，用于热电能量收集。

10mV输入，53%-83%效率，220mV冷启动，14.5dBm RF启动

JSSC 2015第8期Wireline I/ODRAM

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques Keunsoo Song, Sangkwon Lee, Dongkyun Kim, Y oungbo Shim, Sangil Park, Bokr im Ko, Duckhwa Hong, Y ongsuk Joo, Wooyoung Lee, Y ongdeok Cho, Wooyeol Shin, Jaew oong Y un, Hyengouk Lee, Jeonghun Lee, Eunryeong Lee, Namkyu Jang, Jaemo Y ang, Hae-k ang Jung, Joohwan Cho, Hyeongon Kim, and

本文提出了一种LPDDR4设计，通过多通道架构和低摆幅接口等技术，实现了39%的能效提升和4.3 Gbps的数据速率。

1.1 V, 4.3 Gbps

JSSC 2015第8期RF & WirelessEqualizer

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology Timothy O. Dickson , Senior Member , IEEE,Y o n g L i u, Member , IEEE, Sergey V. Rylov , Member , IEEE

一款功率可扩展的14 pJbit 1612 Gbs源同步IO，采用DFE接收器，32nm SOI CMOS工艺。

12 Gb/s每通道，1.4 pJ/b效率（0.75英寸Megtron-6 PCB），1.9 pJ/b效率（20英寸Megtron-6 PCB）

JSSC 2015第8期Analog CircuitsOp-Amp

A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3 Bo Wu, Student Member , IEEE, and Y

40纳米CMOS工艺下实现的可编程带宽带通滤波器，采用新型零电容扩展技术

85-225 MHz中心频率，5%-40%带宽比，31 dBm IIP3，33 mA@1.5V

JSSC 2015第8期RF & Wireless

A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology

本文提出了一种基于LC梯型滤波器的4抽头FFE结构，用于50-64 Gb/s串行化发射机。

64.5 Gb/s, 3.1 pJ/bit

JSSC 2015第8期RF & Wireless

A 5.8 nW CMOS Wake-Up Timer for Ultra-Low-Power

提出一种超低功耗振荡器，用于紧凑型无线传感器的唤醒定时器。

58 nW, 45 ppm/°C, 1%/V

JSSC 2015第8期Data ConvertersVCO

A Highly Digital VCO-Based ADC Architecture for Current

一种基于VCO的高度数字化ADC架构，用于电流传感应用，实现二阶噪声整形。

4μA输入电流范围，900pA精度，77.8μA功耗

JSSC 2015第8期Data Converters

A Micro-Power Two-Step Incremental Analog-to-Digital Converter Chia-Hung Chen, Yi Zhang , Student Member , IEEE,T a o H e ,P a t r i c k Y . C h i a n g, Member , IEEE,a n d

提出一种低功耗两步增量式模数转换器，实现高能效高分辨率数据转换。

65nm CMOS, 2.2V输入, 250Hz带宽, 99.8dB动态范围, 91dB SNDR, 10.7µW功耗

JSSC 2015第8期Clocking & PLLs

A Multi-Phase Sub-Harmonic Injection Locking Technique for Bandwidth Extension in Silicon-Based THz Signal Generation Taiyun Chi,S t u d e n tM e m b e r ,I E E E,J u n L u o,S t u d e n tM e m b e r ,I E E E, Song Hu , Student Member , IEEE,a n d

提出多相次谐波注入锁定技术，扩展振荡器锁定范围并实现太赫兹信号生成

498 GHz输出功率16.6 dBm，相位噪声87 dBc/Hz@1MHz，频率调谐范围485.1-510.7 GHz

JSSC 2015第8期Medical & Bio

A mm-Sized Implantable Medical Device (IMD) With Ultrasonic Power Transfer and a Hybrid Bi-Directional Data Link Jayant Charthad, Student Member , IEEE , Marcus J. Weber , Student Member , IEEE , Ting Chia Chang , Student Member , IEEE, and Amin Arbabian ,M e mber , IEEE

毫米级植入式医疗设备，采用超声波能量传输和混合双向数据通信链路。

4 mm × 7.8 mm, 100 μW DC负载, FDA诊断限5%的声强

JSSC 2015第8期Clocking & PLLsVCOClock Generation

An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation Saman Saeedi, Student Member , IEEE

提出一种低功耗一阶频率合成器架构，适用于高速片上时钟生成，工作频率8-9.5 GHz。

8 GHz输出时钟，集成rms抖动490 fs，峰峰值周期抖动2.06 ps，总rms抖动680 fs，参考杂散-64.3 dBc，功耗2.49 mW@1V

JSSC 2015第8期RF & WirelessEnergy Harvesting

An Energy Harvesting 2 26 0G H zT r a n s c e i v e r With Scalable Data Rate of 38–2450 Mb/s for Near-Range Communication Mazhareddin Taghivand, Kamal Aggarwal, Y ashar Rajavi, and Ada S. Y. Poon , Senior Member , IEEE

一款集成能量收集功能的60 GHz CMOS收发器，支持OOK调制和可编程数据速率。

40 nm CMOS, 1.62 mm², 38 to 2450 Mb/s, BER < 5×10⁻⁵

JSSC 2015第8期Power Management

Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efﬁciency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS Rinkle Jain,M e m b e r ,I E E E, Stephen T. Kim, V aibhav V aidya, Krishnan Ravichandran

22纳米三栅CMOS中采用开关电导调制技术的多比率开关电容电压调节器，实现宽电压电流范围内效率最大化及纹波抑制。

22nm CMOS, 50mV输出纹波, 效率提升15%

JSSC 2015第8期RF & Wireless

Dual-Carrier Aggregation Receiver With Reconﬁgurable Front-End RF Signal Conditioning Run Chen, Student Member , IEEE

一种支持双载波聚合的可重构接收器，采用开关电容技术实现前端射频信号调理。

频率范围0.1至1 GHz，双通道频率间隔可调0至100 MHz，近带阻塞抗扰度提升15 dB

JSSC 2015第8期Other

Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Ampliﬁer With Global Feedback and Digital Control in 55 nm CMOS

该论文提出了一种采用55纳米CMOS工艺的第四阶PWM闭环D类音频放大器，通过数字域反馈环路设计实现了高信噪比和低失真。

105 dBA SNR, 0.0031% THD+N, 92 dB PSRR, 85%效率, 1.5 W输出功率

JSSC 2015第8期Power Management

Introduction to the Special Issue on the IEEE 2014 Custom Integrated

IEEE JSSC特刊收录2014年CICC会议的17篇论文，涵盖混合信号技术、数据转换器、电源管理等前沿领域。

65nm工艺/4mm×7.8mm尺寸/5.8nW功耗/45ppm℃温度稳定性

JSSC 2015第9期Other

A0 . 0 2m m 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad

一种基于65nm CMOS工艺的超紧凑开关电容低通滤波器，具有0.5至10 MHz带宽可调性。

65nm CMOS, 0.02mm² die size, 0.5-10MHz带宽可调, 59.2dB SFDR, +17.6dBm IIP3, 19.5nV/√Hz输入噪声

JSSC 2015第9期Data ConvertersSAR ADCNeural Network Accelerator

A6 0d BS N D R3 5M S / sS A RA D CW i t h Comparator-Noise-Based Stochastic Residue Estimation Bob V erbruggen, Member , IEEE, Jorgo Tsouhlarakis, Takaya Y amamoto

提出一种基于比较器噪声的随机残差估计SAR ADC，实现60.9 dB SNDR和12 µW/MHz动态功耗。

60.9 dB SNDR, 35 MS/s, 12 µW/MHz

JSSC 2015第9期Image Sensors

A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques Y u-Jung Chen, Chao-Hsien Hsu, Chung-Y ao Hung, Chia-Ming Chang, Shan-Yi C huang, Liang-Gee Chen , Fellow, IEEE,a n d S h a o - Y iC h i e n, Member , IEEE

一款130.3毫瓦的16核移动GPU，采用三种像素近似技术和基于瓦片的渲染架构，实现功耗与视觉质量的权衡。

130.3 mW, 16-core, TSMC 45 nm

JSSC 2015第9期Data Converters

A 15-Channel Digital Active Electrode System for Multi-Parameter

一种用于便携式设备的多参数生物电位信号采集的15通道数字有源电极系统。

60 nV/sqrt(Hz)输入参考噪声, 350 mV电极偏移容限, 102 dB CMRR

JSSC 2015第9期Power Management

A 26 W 97%-Efﬁciency Fast-Settling Dimmable LED Driver With Dual-nMOS-Sensing Based Glitch-Tolerant Synchronous Current Control for High-Brightness Solid-State Lighting Applications Zhidong Liu, Student Member , IEEE,a n dH o iL e e, Senior Member , IEEE

提出一种高效快速稳定的可调光LED驱动器，采用双nMOS传感技术，峰值效率达97%。

输入电压5V-45V，工作频率4MHz，电感8.2μH，输出功率26W，效率97.2%

JSSC 2015第9期Image Sensors

A 30 µW 30 fps 110 × 110 Pixels Vision Sensor Embedding Local Binary Patterns Andrew Berkovich, Student Member , IEEE, Michela Lecca

一款低功耗视觉传感器，通过局部二值模式（LBP）实现图像局部结构描述，适用于纹理和物体识别。

30 µW, 30 fps, 110 × 110 pixels, 83 pW/pixel

JSSC 2015第9期Clocking & PLLs

A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS Davide

一款支持不连续频率调制的33 GHz扩频时钟发生器，用于降低电磁干扰。

3.3 GHz工作频率，3.2 ps输出抖动，29.3 mW功耗

JSSC 2015第9期Clocking & PLLsPLL

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten

40纳米CMOS工艺下实现42mW功耗、200fs抖动的60GHz亚采样PLL

42mW功耗, 200fs抖动, 60GHz频率

JSSC 2015第9期Power ManagementDelta-Sigma ADCNeural Network Accelerator

A Closed-Loop Interface for a High-Q Micromechanical Capacitive Accelerometer With 200 ng/ Hz Input Noise Density Honglin Xu, Xiaowei Liu, and

本文提出了一种用于高Q值微机械电容式加速度计的闭环接口电路，采用0.5微米CMOS工艺，实现了高分辨率和低噪声。

23 mW功耗，7 V电源，250 kHz采样时钟，1.896 V/g灵敏度，200 ng/√Hz噪声底，0.15%非线性，1.2g输入范围，300 Hz带宽，18 μg偏置不稳定性

JSSC 2015第9期Other

A DC-100 GHz Active Frequency Doubler With a Low-V oltage

90nm SiGe-BiCMOS工艺下实现DC-100 GHz宽带有源倍频器，采用非对称偏置核心结构

12dB@10GHz转换增益，0dB@100GHz，25dBc@12.5GHz杂散抑制，55.5mA@4.5V

JSSC 2015第9期Image Sensors

A Dynamic Vision Sensor With 1% Temporal Contrast Sensitivity and In-Pixel Asynchronous Delta Modulator for

提出一种具有1%时间对比敏感度和像素内异步调制的动态视觉传感器。

60×30阵列, 31.2μm像素间距, 720μW功耗, 100k事件/s输出率

JSSC 2015第9期Power ManagementBuck ConverterNeural Network Accelerator

A Low-Power Dual-Frequency SIMO Buck Converter Topology With Fully-Integrated Outputs and Fast Dynamic Operation in 45 nm CMOS Chih-Wei Chen, Student Member , IEEE

提出一种双频单电感多输出降压转换器拓扑，实现高效低功耗电源管理

45nm CMOS, 1.8V输入, 2MHz/120MHz双频, 73%峰值效率

JSSC 2015第9期Clocking & PLLsVCONeural Network Accelerator

A Reference-Less Single-Loop Half-Rate Binary CDR Mohammad Sadegh Jalali , Student Member , IEEE

提出一种无参考单环路半速率二进制CDR，工作范围8.5-12.1 Gb/s，捕获范围提升36%。

8.5-12.1 Gb/s, 11 mW, 65nm CMOS

JSSC 2015第9期Digital CircuitsNeural Network Accelerator

A Sub-µg Bias-Instability MEMS Oscillating Accelerometer With an Ultra-Low-Noise Read-Out Circuit in CMOS Ya n g Z h a o, Student Member , IEEE,J i a n Z h a o, Student Member , IEEE,X i W a n g, Student Member , IEEE, Guo Ming Xia, An Ping Qiu, Y an Su, and Y ong Ping Xu , Senior Membe r , IEEE

提出一种超低噪声MEMS振荡加速度计，采用新型TIA前端电路和位移控制策略，实现0.6 µg偏置不稳定性和2 µg/√Hz噪声基底。

0.6 µg偏置不稳定性(Allan方差), 2 µg/√Hz噪声基底, 140 Hz/g灵敏度, ±20 g满量程, 3.5 mW功耗

JSSC 2015第9期Clocking & PLLs

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

提出一种无需参考时钟的全速率线性CDR，通过非对称相位检测器提升捕获范围，实现稳健的频率和相位获取。

输出数据随机抖动0.336 ps，带外抖动容限0.34 UI

JSSC 2015第9期Digital CircuitsNeural Network Accelerator

An Asymmetric-V oltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded

提出一种基于不对称电压偏置的电流模式传感方案，用于快速读取嵌入式闪存。

3.9 ns读取时间（1.2 V，512行）

JSSC 2015第9期Other

An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4 C( 3 )F r o m 40 C to 130 C

65nm CMOS嵌入式远程温度传感器，采用数字β补偿技术，适应多种BJT。

65nm CMOS, 温度范围-40°C至130°C, 可处理500Ω以上串联电阻, β值低至1.5

JSSC 2015第9期Clocking & PLLsClock Generation

Comments and Corrections Errata for “A TDC-Free Mostly-Digit al FDC-PLL Frequency Synthesizer With a 2.8–3.5 GHz DCO” Several errors were made by IEEE dur ing the typesetting process of [1] through no fault of the authors. Although the authors m ade IEEE aware of these errors prior to publication of [1], an oversight by IEEE prevented three of the errors from being corrected. The errors corrupted the Equations (1), Fig. 11, and Table I in [1], cor rected versions of which are as follows: Fig. 11. Representative measured FDC-PLL phase noise spectrum, the corre -

本文为IEEE JSSC期刊论文的勘误，修正了排版过程中的错误。

无

JSSC 2015第9期RF & WirelessPLLPAM-4

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

设计用于PAM4和NRZ数据的56 Gbps SerDes收发器，验证了下一代400 GbE的设计可行性。

56 Gb/s, 400 GbE

JSSC 2015第9期RF & WirelessPower Amplifier

Dual-Mode CMOS Doherty LTE Power Ampliﬁer With Symmetric Hybrid Transformer Ercan Kaymaksut, Student Member , IEEE

40nm CMOS工艺的双模Doherty LTE功率放大器，采用对称混合变压器实现高效率与低功耗。

40nm CMOS, 1.5V, 28dBm输出, 34%峰值PAE, 23.3% PAE@23.4dBm LTE

JSSC 2015第9期Data ConvertersVCO

Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC

通过滤波抖动技术实现50MHz带宽10位ENOB的VCO基ADC线性化

65nm CMOS, 10 ENOB, 50 MHz带宽, 82 mW, 90 fJ/conv.step

JSSC 2015第9期Other

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register Takeshi Aoki, Y uki Okamoto, Takashi Nakagawa, Munehiro Kozuma, Y oshiyuk i Kurokawa, Takayuki Ikeda, Naoto Y amade, Y utaka Okazaki, Hidekazu Miyairi

基于结晶氧化物半导体的多上下文FPGA实现常关计算，提升能效。

1.0µm氧化物半导体/0.5µm CMOS, 2.5V, 20MHz, 功耗降低27.7%

JSSC 2015第9期Other

SEPTEMBER 2015 VOLUME 50 NUM BER 9 IJSCBC ISSN 0018-9200 REGULAR PAPERS A DC-100

本文介绍了多种CMOS技术下的高性能电路设计，包括功率放大器、滤波器、ADC和PLL等。

DC-100 MHz, 59.2 dB SFDR, 60 dB SNDR, 35 MS/s, 200 fs抖动

JSSC 2015第10期Other

170 GHz SiGe-BiCMOS Loss-Compensated Distributed Ampliﬁer Paolo V alerio Testa, Guido Belﬁore, Robert Paulo

本文介绍了一种基于0.13μm SiGe BiCMOS工艺的170 GHz宽带行波放大器，实现了10 dB增益和170 GHz带宽。

0.13μm SiGe BiCMOS, 10 dB gain, 170 GHz bandwidth, 108 mW power consumption, 0.38 mm² area

JSSC 2015第10期Data ConvertersDelta-Sigma ADC

A0 . 4V6 3 W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator Y ounghyun Y oon

提出一种0.4V低电压Δ-Σ调制器，采用混合开关积分器，无需时钟提升或自举开关。

0.4V, 63µW, 76.1dB SNDR, 20kHz带宽

JSSC 2015第10期Data Converters

A6 5n mC M O S7 b2G S / s2 0 . 7m WF l a s hA D C With Cascaded Latch Interpolation Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung

提出一种采用65nm CMOS工艺的7位2GS/s闪存ADC，通过级联锁存插值技术实现高效转换。

7位分辨率，2GS/s采样率，20.7mW功耗，157fJ/conversion-step

JSSC 2015第10期Data ConvertersPipeline ADC

A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Ampliﬁers

提出自偏置环形放大器方案，实现高效能比较器流水线ADC。

100 MS/s, 56.6 dB SNDR, 2.46 mW

JSSC 2015第10期Data Converters

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory Dong-Hwan Jin, Ji-Wook Kwon, Hyeon-June Kim, Sun-Il Hwang, Minchul Shin

提出一种用于多层相变存储器的15微米间距读出电路，采用两步5位对数ADC架构，实现高速高精度读取。

15 µm间距, 87-ENOB, 13 Mcells/sec, 1.2 V供电

JSSC 2015第10期Power ManagementTDC

A 1 × 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical Tomography Juan Mata Pavia, Mario Scandini, Scott Lindner, Martin Wolf, and Edoardo C harbon, Senior Member , IEEE

介绍了一种采用130nm 3D IC CMOS技术制造的1×400背面照射SPAD传感器，具有497 ps分辨率和30 pJ/采样的TDC。

497 ps分辨率，30 pJ/采样，13.3 ms/s转换率

JSSC 2015第10期RF & Wireless

A 240 GHz Fully Integrated Wideband QPSK Receiver in 65 nm CMOS

65nm CMOS工艺下实现的240 GHz宽带QPSK接收器，支持16 Gbps数据传输

噪声系数15 dB，转换增益25 dB，最大数据速率16 Gbps

JSSC 2015第10期RF & Wireless

A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS

65纳米CMOS工艺下实现的240 GHz宽带QPSK发射机，支持16 Gbps数据传输

16 Gbps, 14 pJ/bit, 1 dBm EIRP

JSSC 2015第10期Image Sensors

A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR Applications Josep Maria Margarit , Student Member , IEEE, Germán V ergara, Víctor Villamayor, Raúl Gutiérrez-Álvarez, Carlos Fernández-Montojo, Lluís Terés, and Francisco

提出一种基于VPD PbSe光电导体的单片非制冷高速成像器，具有10位动态范围校准和FPN补偿功能。

80 × 80成像器，135 µm像素间距，68%填充因子，2 kfps帧率，亚µW像素功耗

JSSC 2015第10期RF & WirelessTransceiver

A 50–450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP , +12 dBm P , and 15 dB Noise Figure In-Y

基于宽带源跟随器的50450 MHz可调RF双二阶滤波器设计

0.18μm CMOS, 1.8V, 14mA, 50-450MHz可调, 26dBm IIP3, 15dB噪声系数

JSSC 2015第10期RF & WirelessPLL

A 60 GHz, 802.11ad/WiGig-Compliant Transceiver for Infrastructure and Mobile Applications in 130 nm SiGe BiCMOS

一款完全集成、符合802.11ad/WiGig标准的60 GHz收发器，采用130 nm SiGe BiCMOS技术，覆盖57至66 GHz频段。

RX NF <5.5 dB, TX OP1dB >13.5 dBm, PLL RMS jitter <7 ps

JSSC 2015第10期RF & WirelessCMOS Image Sensor

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs Numa Couniot, Student Member , IEEE , Guerric de Streel , Student Member , IEEE , François Botman, Student Member , IEEE, Angelo Kuti Lusala ,M ember , IEEE

一款适用于物联网无线传感器节点的超低功耗65纳米CMOS图像传感器

0.5V工作电压, 17 pJ/帧像素, 42 dB动态范围, 0.66%固定模式噪声

JSSC 2015第10期MemoryDRAM

A Refresh-Less eDRAM Macro With Embedded V oltage Reference and Selective Read for an Area and Power Efﬁcient Viterbi Decoder Woong Choi, Student Member , IEEE , Gyuseong Kang , Student Member , IEEE ,a n d

提出一种基于2T增益单元的无刷新eDRAM设计，用于IEEE 802.11n WLAN的Viterbi解码器。

65nm CMOS工艺，24 kb eDRAM，面积节省44%，功耗节省39%

JSSC 2015第10期RF & WirelessDAC

An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS Ameya Bhide,S t u d e n tM e m b e r ,I E E E

本文提出了一种用于60 GHz无线电基带的11 GS/s 1.1 GHz带宽交织ΔΣ DAC，采用65 nm CMOS工艺实现。

11 GS/s, 1.1 GHz带宽, 53 dB SFDR, -49 dBc IM3, 39 dB SNDR, 117 mW功耗

JSSC 2015第10期Wireline I/O

Comments and Corrections Correction to “A 0.41 pJ/Bi t 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS” Shayan Shahramian and Anthony Chan Carusone In the above paper [1], a mistake was made during printing and Fig. 9(b) was overwritten with Fig. 9(a). The correct Fig. 9 is shown below. In addition, Equation (4) should read: (4) IEEE regrets the errors.

对论文中图9和公式(4)的印刷错误进行更正。

JSSC 2015第10期Other

Corrections to “A 0.02 mm 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MH z Bandwidth Scalability Exploiting a Recyclin gS C - B u f f e rB i q u a d ” P. V. Ananda Mohan, Y aohua Zhao, Pui-In Mak, Rui P. Martins, and Franco Maloberti In the above paper [1], the authors found that the -domain transfer function in (3) should be corrected as Manuscript received July 27, 2015; ac cepted August 10, 2015. Date of pub- lication September 03, 2015; date of current version September 24, 2015.

该论文对第四阶SC LPF的传输函数进行了修正，并探讨了其带宽可扩展性。

59.2 dB SFDR, 0.5-to-10 MHz bandwidth

JSSC 2015第10期Other

Digital Object Identiﬁer 10.1109/JSSC.2015.2480239

无摘要信息，无法提供概要。

无关键性能指标信息。

JSSC 2015第10期mm-Wave

Introduction to the Special Section on the 2014 Compound Semiconductor Integrated

2014年IEEE JSSC特刊介绍化合物半导体集成电路的最新进展。

130 nm SiGe, 57-66 GHz, 8 dBi增益, 接收NF > 5.5 dB, 发射OP 1dB > +13.5 dBm

JSSC 2015第10期Power ManagementBuck-Boost

Inverting Buck-Boost DC-DC Converter for Mobile AMOLED Display Using Real-Time Self-Tuned Minimum Power-Loss Tracking (MPLT) Scheme With Lossless Soft-Switching for Discontinuous

提出一种用于移动AMOLED显示的反向升降压DC-DC转换器，实现91%的最高能效。

0.35μm BCD, 2.9-4.5V输入, 3.8-5.9V输出, 1MHz频率, 91%效率

JSSC 2015第10期Memory

Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme Byung-Do Y ang

提出一种低功耗高效内存扩展的三态内容寻址存储器（TCAM），通过数据重定位方案优化IPv6地址存储。

1.2 V 0.13 µm CMOS, 200 MHz, 1.3 fJ/bit/search

JSSC 2015第10期RF & Wireless

Low Flicker Noise, Odd-Phase Master LO Active Mixer Using a Low Switching Frequency Scheme Dongju Lee, Student Member , IEEE

提出一种低闪烁噪声和失配上变频的有源混频器，采用奇级联开关对降低开关频率需求。

0.11 µm CMOS, 1.2 V, < 4 kHz 闪烁噪声转角, 9.4 dBm IIP3, 7.2 dB 转换增益, > 60 dBm IIP2, 1.8 GHz LO频率

JSSC 2015第10期Other

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Ampliﬁer With Enhancements of DC Gain, GBW and Slew Rate Zushu Y an, Student Member , IEEE

采用嵌套电流镜技术的单级放大器，实现高增益、带宽和压摆率，适用于显示驱动。

0.18μm CMOS, 72-84 dB DC增益, 0.0028-1.24 MHz GBW, 0.15-15 nF负载

JSSC 2015第10期Other

OCTOBER 2015 VOLUME 50 NUMBER 10 IJSCBC (ISSN 0018-9200) SPECIAL SECTION ON THE 2014 COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM Introduction to the Special Section on the 2014 Compou nd Semiconductor Integrated Circuit Symposium . . . . W. Khalil 2227 SPECIAL SECTION PAPERS

IEEE JSSC 2015年10月刊聚焦高频集成电路设计，涵盖SiGe BiCMOS和CMOS技术的放大器、收发器及混频器。

17 GHz/60 GHz/240 GHz工作频率，130 nm SiGe BiCMOS/65 nm CMOS工艺

JSSC 2015第10期Power ManagementEnergy Harvesting

Self-Powered 30 µW to 10 mW Piezoelectric Energy Harvesting System With 9.09 ms/V Maximum Power Point Tracking Time Minseob Shim, Student Member , IEEE , Jungmoon Kim , Student Member , IEEE , Junwon Jeong, Student Member , IEEE, Sejin Park ,S t u d e n tM e m b e r ,I E E E

提出一种自供电压电能量收集系统，采用单周期最大功率点感应技术。

0.35µm BCDMOS, 2.7V, 10µW, 90kHz, 10-mH电感

JSSC 2015第11期Clocking & PLLs

140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology Ryan Clarke, Student Member , IEEE , Mitchell R. LeRoy , Student Member , IEEE , Srikumar Raman, Student Member , IEEE , Tuhin

本文提出了一种新型时钟分配技术，使用时钟倍增器实现140 Gb/s的串行器。

90nm BiCMOS, 3.4V, 140 Gb/s, 5.78W

JSSC 2015第11期RF & WirelessEnergy Harvesting

A2 4 µW, Batteryless, Crystal-free, Multinode Synchronized SoC “Bionode” for Wireless Prosthesis Control Hansraj Bhamra, Student Member , IEEE, Y oung-Joon Kim,Student Member , IEEE, Jithin Joseph, John Lynch, Oren Z. Gall, Henry Mei, Student Member , IEEE, Chuizhou Meng, Jui-Wei Tsai

一款无电池、无晶振、多节点同步的无线体感传感器SoC，用于实时肌电信号遥测

0.18µm CMOS, 24µW功耗, 2.025mm²面积

JSSC 2015第11期Data ConvertersSAR ADCDelta-Sigma ADC

A 0.022 mm 98.5 dB SNDR Hybrid Audio Modulator With Digital ELD Compensation in 28 nm CMOS Tze-Chien Wang, Y u-Hsin Lin

28nm CMOS工艺下，紧凑型混合连续时间ΔΣ调制器，数字ELD补偿，音频应用。

28nm CMOS, 0.022mm², 98.5dB SNDR, 171.8dB FOM

JSSC 2015第11期Other

A 0.7 V 24 µA Hybrid OTA Driving 15 nF Capacitive Load With 1.46 MHz GBW Kai Ho Mak, Student Member , IEEE, Ming Wai Lau, Student Member , IEEE

采用六级信号电流增强器提升OTA性能，实现高增益带宽和低功耗。

0.13µm CMOS, 0.7V, 24µA, 1.46MHz GBW, 100dB gain

JSSC 2015第11期Other

A 10.4 mW Electrical Impedance Tomography SoC for Portable Real-Time Lung V entilation Monitoring System Sunjoo Hong, Student Member , IEEE , Jaehyuk Lee , Student Member , IEEE

一款用于便携式实时肺部通气监测的104 mW电阻抗断层成像SoC。

0.18 µm CMOS, 1.8V, 10.4 mW, 20 frames/s

JSSC 2015第11期Data ConvertersSAR ADC

A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS

一款用于IEEE 802.11ac应用的低成本SAR ADC，采用20 nm CMOS工艺，具有高能效和小面积。

20 nm CMOS, 0.9 V/1 V, 160 MS/s/320 MS/s

JSSC 2015第11期Other

A 16-Channel Patient-Speciﬁc Seizure Onset and Termination Detection SoC With Impedance-Adaptive Transcranial Electrical Stimulator Muhammad Awais Bin Altaf, Student Member , IEEE, Chen Zhang, Student Member , IEEE, and Jerald Y oo,Senior Member , IEEE

一款16通道非侵入式闭环癫痫发作起止检测SoC，集成双通道电荷回收模拟前端和双检测器架构分类处理器。

0.18µm CMOS, 0.9µA/channel, NEF 3.29/channel, 2.45µW, 95.7%灵敏度, 98%特异性, 1s延迟

JSSC 2015第11期RF & WirelessEqualizerDRAM

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel

提出一种65nm CMOS工艺的16.8 Gbps单端收发器，用于SiP基DRAM接口。

65 nm CMOS, 16.8 Gbps, BER < 1e-12, 5.9 pJ/bit

JSSC 2015第11期RF & WirelessDLLClock Generation

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

首款基于乘法延迟锁定环的分数-N频率合成器，实现低相位噪声和抖动。

65nm CMOS, 1.6-1.9GHz, 190Hz分辨率, 3mW功耗, 1.4ps RMS抖动

JSSC 2015第11期Power ManagementCharge PumpNeural Network Accelerator

A 1 V Input, 3 V-to-6 V Output, 58%-Efﬁcient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efﬁciency by Using Parasitics Jen-Huan Tsai, Sheng-An Ko, Chia-Wei Wang, Y ang-Chi Y en, Hui-Huan Wang, P

提出一种集成混合6级电压倍增器，无需高压器件，实现高效小面积电荷泵。

1V输入，3-6V输出，48-58%效率，0.05mm²面积

JSSC 2015第11期Other

A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode

开发了一种1毫米间距、80×80通道、322Hz帧率的多点触控分布传感器，采用两步双模电容扫描方案提高扫描速率。

41 dB信噪比（SNR），>5倍更紧的传感器通道间距，>10倍更快的触控点扫描，>10倍和>4倍更高的能量和面积效率

JSSC 2015第11期RF & WirelessCDR

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process Sang-Hyeok Chu, Student Member , IEEE ,W o o r h a m B a e, Student Member , IEEE , Gyu-Seob Jeong, Student Member , IEEE, Sungchun Jang, Sungwoo Kim , Student Member , IEEE, Jiho Joo

本文介绍了一种22至26.5 Gb/s的全数字时钟数据恢复光学接收器，采用65nm CMOS工艺，具有低功耗和高性能。

65nm CMOS, 26.5 Gb/s, 254 mW, 1.28 ps抖动, 106 A灵敏度

JSSC 2015第11期Digital Circuits

A 27 mW Reconﬁgurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor Injoon Hong, Student Member , IEEE , Gyeonghoon Kim , Student Member , IEEE , Y ouchang Kim, Student Member , IEEE, Donghyun Kim ,M e m b e r ,IEEE

提出一种27mW可重构无标记对数相机姿态估计引擎，用于移动增强现实应用。

65nm CMOS, 27mW功耗

JSSC 2015第11期RF & WirelessPLLCDR

A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery Zheng-Hao Hong, Y ao-Chia Liu , Student Member , IEEE

一款19-27 Gbps接收器，采用连续时间线性均衡器和2抽头判决反馈均衡器嵌入时钟数据恢复电路，实现高效能和小尺寸。

40 nm CMOS, 3.12 pJ/bit, 27 Gbps

JSSC 2015第11期Power ManagementBoost ConverterEnergy Harvesting

A 400 nW Single-Inductor Dual-Input–Tri-Output DC–DC Buck–Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting Guolei Y u,Student Member , IEEE,K i nW a iR o yC h e w ,Student Member , IEEE, Zhuo Chao Sun, Student Member , IEEE, Howard Tang, Student Member , IEEE

一款400nW单电感双输入三输出BuckBoost转换器，用于室内远程传感器系统的能量管理。

400nW静态功耗，83%峰值效率（100µW输出）

JSSC 2015第11期RF & Wireless

A 40 nm CMOS E-Band Transmitter With Compact and Symmetrical Layout Floor-Plans

40纳米CMOS工艺下实现紧凑对称布局的E波段发射器设计

40 nm CMOS, 12 dBm输出功率, 15%效率, 15 GHz带宽

JSSC 2015第11期RF & Wireless

A 5.2 mW IEEE 802.15.6 HBC Standard Compatible Transceiver With Power Efﬁcient Delay-Locked-Loop Based BPSK Demodulator Hyunwoo Cho, Student Member , IEEE

一款低功耗IEEE 802.15.6人体通信兼容收发器，采用130nm CMOS工艺，功耗仅52mW。

130nm CMOS, 1.2V, 5.2mW

JSSC 2015第11期Data ConvertersDelta-Sigma ADC

A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ C Chan-Hsiang Weng, Chun-Kuan Wu

提出一种嵌入热敏电阻的连续时间ΔΣ温度传感器，实现高效温度采集。

1.5V, 64.5μW, 0.01°C rms, 100μs转换时间

JSSC 2015第11期RF & WirelessRadar

A Direct-Sampling Pulsed Time-of-Flight Radar With Frequency-Deﬁned V ernier Digital-to-Time Converter in 65 nm CMOS Y u-Hsien Kao

本文介绍了一种高分辨率直接采样脉冲雷达，用于精确测量飞行时间（TOF）。

65nm CMOS, 2mm²芯片面积, 88.4mW功耗, 10GHz前端带宽, 666GS/s等效采样率

JSSC 2015第11期RF & WirelessTransceiver

A Fully-Integrated Reconﬁgurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS Xiaobao Y u, Meng Wei, Y un Yin, Ying Son g, Siyang Han, Qiongbing Liu, Zongmi ng Jin, Xiliang Liu

一款全集成可重构双频段收发器，适用于短距离无线通信，具有高性能和高效能。

sub-GHz PA OP1dB 16.3 dBm, 2.4 GHz PA OP1dB 14.1 dBm, PAE 25%

JSSC 2015第11期Other

A High-Linearity, 30 GS/s Track-and-Hold Ampliﬁer and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process Kristian N. Madsen , Member , IEEE, Timothy D. Gathman , Member , IEEE

采用InP-on-CMOS工艺实现的高速、高线性度30 GS/s跟踪保持放大器与时序交错采样保持电路。

IIP3 19 dBm @30 GS/s, 53 dBc @5 GS/s, 24 mW/通道

JSSC 2015第11期Power ManagementBuck Converter

A Monolithic Capacitor-Current-Controlled Hysteretic Buck Converter With Transient-Optimized Feedback Circuit Shih-Hsiung Chien,S t u d e n tM e m b e r ,I E E E, Ting-Hsuan Hung, Szu-Y u Huang , Student Member , IEEE,a n d

提出一种用于便携设备的单片电容电流控制迟滞降压转换器，优化瞬态响应。

0.35 µm CMOS, 0.88 mm², 96%效率, 500 mW输出功率

JSSC 2015第11期Clocking & PLLsDLL

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

一款采用65nm CMOS技术的宽范围低功耗全数字延迟锁定环，具有循环半延迟线架构。

3 MHz至1.8 GHz, 94μW至9.5mW, 0.0153mm²面积

JSSC 2015第11期Digital CircuitsProcessor/CPU

Compact and Supply-V oltage-Scalable Temperature Sensors for Dense On-Chip

提出了一种紧凑且电压可调的温度传感器电路，用于高性能微处理器和SoC的动态热管理。

65nm CMOS, 0.6V, 最坏情况误差7.0°C（64个实例）

JSSC 2015第11期Power Management

Low Swing-Sample-and-Couple Sense Ampliﬁer and Energy-Efﬁcient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time V ariations

提出一种低摆幅采样耦合感应放大器和自增强写入终止方案，以提高ReRAM的读取性能和能效。

28nm CMOS, 0.27V, 404ns

JSSC 2015第11期Other

NOVEMBER 2015 VOLUME 50 NUMBER 11 IJSCBC (ISSN 0018-9200) SPECIAL SECTION ON THE 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)

IEEE JSSC期刊论文合集，涵盖固态电路、温度传感器、阻抗成像等多个领域的最新研究。

如：0.65 pJ°C温度传感器分辨率FoM, 10.4 mW功耗

JSSC 2015第11期RF & Wireless

RF Transconductor Linearization Robust to Process, V oltage and Temperature V ariations Harish Kundur Subramaniyan , Student Member , IEEE, Eric A. M. Klumperink , Senior Member , IEEE

提出一种基于电阻退化的鲁棒线性化技术，改善CMOS逆变器的线性度，提高IIP3性能。

IIP3从2dBm提升至8dBm，功耗增加67%

JSSC 2015第11期Other

Wide-Supply-Range All-Digital Leakage V ariation Sensor for On-Chip Process and Temperature Monitoring A. K. M.

提出一种全数字片上电路，用于独立监测nMOSFET和pMOSFET的漏电流变化，适用于工艺和温度变化的跟踪。

65nm CMOS, 0.8V, 76nW

JSSC 2015第12期RF & WirelessVCO

A 10 mW Bluetooth Low-Energy Transceiver With On-Chip Matching

一款采用经典双频VCO架构、55nm CMOS工艺的低功耗蓝牙收发器，功耗低于同类产品。

55nm CMOS, 接收功耗11mW@-94dBm, 发射功耗10mW@0dBm

JSSC 2015第12期Data ConvertersPipeline ADCOp-Amp

A 12b 250 MS/s Pipelined ADC With Virtual Ground

提出虚拟地参考缓冲技术提升12位250MS/s流水线ADC性能

65nm CMOS, 1.2V, 250MS/s, 67.0dB SNDR, 49.7mW

JSSC 2015第12期Data ConvertersSAR ADCNeural Network Accelerator

A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS

一款14位35MS/s SAR ADC，通过环路嵌入式输入缓冲器实现74.5 dB SNDR和99 dB SFDR。

14位, 35MS/s, 74.5 dB SNDR, 99 dB SFDR, 54.5 mW

JSSC 2015第12期Data ConvertersPipeline ADC

A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Ampliﬁer Based SAR-Assisted Pipeline ADC

本文提出了一种基于65nm CMOS工艺的13位50MS/s全差分环形放大器SAR辅助流水线ADC，具有高增益和低功耗特点。

65nm CMOS, 1mW, 50MS/s, 70.9dB SNDR

JSSC 2015第12期RF & WirelessOptical I/O

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS Hao Li, Student Member , IEEE , Zhe Xuan

65nm CMOS工艺下实现的25 Gb/s WDM硅光发射器，具有4.4V输出摆幅和波长稳定功能。

25 Gb/s, 113.5 mW/通道, 7 dB消光比, 4.4 V输出摆幅

JSSC 2015第12期RF & WirelessNeural Network Accelerator

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic

一款用于低延迟光子交换网络的25 Gbs突发模式接收器，具有快速锁定和高灵敏度特性。

25 Gb/s, -10.9 dBm灵敏度, 4.4 pJ/bit能效, 31 ns锁定时间

JSSC 2015第12期RF & WirelessHigh-Speed LinkEqualizer

A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS

一款28 Gbs多标准串行链路收发器，适用于背板应用，采用28nm CMOS工艺，功耗低至295mW。

28nm CMOS, 1.25V, 295mW

JSSC 2015第12期Power Management

A 3-Phase Resonant Switched Capacitor Converter Delivering 7.7 W at 85% Efﬁciency Using 1.1 nH PCB Trace Inductors Christopher Schaef, Student Member , IEEE, and Jason T. Stauth , Member , IEEE

提出一种三相谐振开关电容转换器，实现77W输出功率和85%效率。

77W输出功率, 85%效率, 0.91W/mm²功率密度

JSSC 2015第12期Data ConvertersCharge PumpPLL

A 3.5 GHz Digital Fractional- N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion

65nm CMOS工艺下3.5GHz数字分数分频锁相环，性能媲美模拟PLL。

65nm CMOS, 1V, 15.6mW, 0.34mm², -60dBc最大带内分数杂散, -81dBc最差参考杂散, -93/-126/-151 dBc/Hz@100kHz/1MHz/20MHz相位噪声

JSSC 2015第12期Power ManagementBuck Converter

A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator Seong Joong Kim , Student Member , IEEE , Romesh Kumar Nandwana , Student Member , IEEE , Qadeer Khan, Robert C. N. Pilawa-Podgurski , Member , IEEE, and Pavan

提出一种基于时间补偿的高频多相降压转换器，有效减少相位失配，提高效率。

65nm CMOS, 0.6V-1.5V输出, 30-70MHz开关频率, 87%峰值效率

JSSC 2015第12期Other

A 4.5 mW CT Self-Coupled Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation Chen-Y

一种采用自耦合技术的低功耗连续时间调制器，实现90.4dB SNDR和2.2MHz带宽。

55nm LP CMOS, 1.2V/1.8V, 4.5mW, 2.2MHz BW, 90.4dB SNDR

JSSC 2015第12期RF & WirelessDAC

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS Massimo Brandolini, Y oung J. Shin, Karthik Raviprakash, Tao Wang ,M e m b e r ,I E E E, Rong Wu, Student Member , IEEE , Hemasundar Mohan Geddada ,M e mber , IEEE, Y en-Jen Ko, Y en Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Ace r Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Dominique Yi-Chun Chen, Bryan Juo-Jung Hung, Gius

本文介绍了一种28nm CMOS 10位SHA-less流水线/SAR混合ADC，用于直接采样系统，功耗低至150mW。

28nm CMOS, 1.8V/1V, 5GS/s, 150mW, 0.5mm²

JSSC 2015第12期Clocking & PLLsNeural Network Accelerator

A 60 V Auto-Zero and Chopper Operational Ampliﬁer With 800 kHz Interleaved Clocks and Input Bias Current Trimming Y

一款采用0.18μm CMOS工艺的60V自零和斩波运算放大器，具有800kHz交错时钟和低噪声特性。

4.5–60V, 0.02μV/°C, 145dB CMRR, 6.8nV/√Hz, 3.1MHz带宽, 840μA

JSSC 2015第12期RF & WirelessHigh-Speed Link

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links Tejasvi Anand, Student Member , IEEE, Mrunmay Talegaonkar, Ahmed Elkhol y, Student Member , IEEE, Saurabh Saxena

提出一种支持快速开关的嵌入式时钟收发器，实现能效与通信量成正比。

65nm CMOS, 7Gb/s, 20ns锁定时间, 能效9.1pJ/bit至20.5pJ/bit

JSSC 2015第12期RF & Wireless

A Blocker-Tolerant Inductor-Less Wideband Receiver With Phase and Thermal

一种无电感宽带接收器架构，通过相位和热噪声抵消技术优化噪声、线性度和功耗。

28nm CMOS, 噪声系数低于14 dB, 频率范围100 MHz至2.8 GHz

JSSC 2015第12期Data ConvertersDelta-Sigma ADC

A Continuous-Time Sturdy-MASH Modulator in 28 nm CMOS

提出一种连续时间SMASH调制器，实现宽带宽和高动态范围

28nm CMOS, 1.8GHz采样频率, 50MHz带宽, 85dB动态范围, 74.9dB SNDR

JSSC 2015第12期Power ManagementNeural Network Accelerator

A Light-Load-Efﬁcient 11/1 Switched-Capacitor DC-DC Converter With 94.7% Efﬁciency While Delivering 100 mW at 3.3 V Hans Meyvaert, Student Member , IEEE , Gerard Villar Piqué , Member , IEEE

本文展示了一种轻载高效的11/1开关电容DC-DC转换器，峰值效率达95.5%。

37.4V–39V输入, 3.3V输出, 95.5%峰值效率

JSSC 2015第12期RF & WirelessPLL

A SiGe Terahertz Heterodyne Imaging Transmitter With 3.3 mW Radiated Power and Fully-Integrated Phase-Locked Loop

采用130nm SiGe BiCMOS技术实现320GHz高功率太赫兹发射器，辐射功率3.3mW，效率0.54%。

320GHz, 3.3mW辐射功率, 22.5dBm EIRP, 610mW功耗, 0.54%效率

JSSC 2015第12期Power ManagementBuck Converter

An Error-Based Controlled Single-Inductor 10-Output DC-DC Buck Converter With High Efﬁciency Under Light Load Using Adaptive Pulse Modulation Min-Y ong Jung, Sang-Hui Park, Student Member , IEEE, Jun-Suk Bang

提出一种基于误差控制的单电感10输出DC-DC降压转换器，实现高效率和快速负载瞬态响应。

峰值效率88.7%，负载瞬态响应0.17 mV/mA，交叉调节0.1 mV/mA

JSSC 2015第12期RF & Wireless

An In-Band Full-Duplex Radio Receiver With a Passive V ector Modulator Downmixer for Self-Interference Cancellation Dirk-Jan van den Broek, Student Member , IEEE, Eric A. M. Klumperink, Senior Member , IEEE

提出一种使用无源矢量调制器的全双工无线电接收机，实现高达27 dB的自干扰消除。

71.5 dB SINDR, 16.25 MHz BW

JSSC 2015第12期RF & Wireless

An Incremental-Charge-Based Digital Transmitter With Built-in Filtering Pedro Emiliano Paro Filho , Student Member , IEEE,M a r k I n g e l s, Member , IEEE

提出一种基于增量电荷域的数字发射机架构，具有内置滤波功能，显著提升带外噪声性能。

28nm CMOS, 0.9V, 128MS/s, 155dBc/Hz@45MHz, 41.3mW@1dBm

JSSC 2015第12期Clocking & PLLs

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers Ahmed Elkholy, Student Member , IEEE, Mrunmay Talegaonkar, Student Member , IEEE, Tejasvi Anand, Student Member , IEEE, and Pavan

提出一种低抖动、低功耗的LC注入锁定时钟倍频器，采用数字频率跟踪环路确保鲁棒性。

65nm CMOS, 0.25mm², 6.75–8.25 GHz, 190 fs rms, 2.25 mW

JSSC 2015第12期RF & WirelessEqualizer

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop

设计并制造了一种7.5 Gb/s混合NRZ/多音调收发器，用于多滴总线内存接口。

7.5 Gb/s, 1 pJ/bit, 45 dB loss at 2.5 GHz

JSSC 2015第12期RF & Wireless

Integrated Wideband Self-Interference Cancellation in the RF Domain for FDD and Full-Duplex Wireless Jin Zhou, Student Member , IEEE, Tsung-Hao Chuang, Student Member , IEEE, Tolga Dinc, Student Member , IEEE

提出一种用于FDD和FD无线应用的集成宽带自干扰消除技术，通过可调谐的高Q值RF带通滤波器和线性N-path Gm-C滤波器实现。

0.8–1.4 GHz, >20 MHz 20 dB cancellation bandwidth, +25–27 dBm OOB IIP3, +90 dBm OOB IIP2

JSSC 2015第12期Clocking & PLLsNeural Network AcceleratorOp-Amp

DECEMBER 2015 VOLUME 50 NUMBE R 12 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE 2015 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE Introduction to the December Special Issue on the 2015 IEEE In ternational Solid-State Circ uits Conference . . . . . . . . . . . . .

2015 IEEE国际固态电路会议特刊介绍及多篇模拟电路论文摘要

60V, 800kHz, 30-70MHz, 94.7%效率

JSSC 2015第12期RF & Wireless

RF-Powered Transceiver With an Energy- and Spectral-Efﬁcient IF-Based Quadrature

本文介绍了一种5.8 GHz射频供电收发器，采用基于IF的正交反向散射技术，实现低功耗和高频谱效率。

2.5 Mb/s传输速率，113 µW功耗，0.6 V电源供电

JSSC 2015第12期RF & WirelessTransceiver

Reconﬁgurable Receiver With Radio-Frequency Current-Mode Complex Signal Processing Supporting Carrier Aggregation Run Chen, Student Member , IEEE

一种适用于带内载波聚合的可重构软件定义无线电接收器，采用电流模式复数信号处理技术。

0.5-3GHz工作频率，支持三通道聚合，通道间隔0-100MHz可调

JSSC 2015第12期RF & Wireless

Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor

针对蓝牙低能耗应用的亚毫瓦级电流复用接收器前端设计

130nm CMOS, 0.8V, 0.6mW, NF=15.8dB, IIP3=17dBm

JSSC 2015第12期Data Converters

Wideband Rapid Interferer Detector Exploiting Compressed Sampling With a Quadrature Analog-to-Information Converter Rabia Tugce Y azicigil, Student Member , IEEE

利用压缩采样的宽带快速干扰检测器

65nm CMOS, 1.1V, 81mW, 1GHz带宽, 20MHz分辨率, 4.4µs检测时间