JSSC 年份

2023

306 篇期刊论文

JSSC 2023第1期Wireline I/OFlash Memory
A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface Jong Hak Y uh , Y en-Lung Jason Li, Heguang Li, Y oshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Gwang Y eong Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Y ap, Demin Wang, Steve Kim, Y onggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, Taekeun Han, Masatoshi Okumura, Jiwen Liu , Jeongduk John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Akihiro Matsuda, Chen Chen , Indra K. V ., V . S. N. K. Chaitanya G., V enky Ramachandra, Y osuke Kato, Ravi J. Kumar, Huijuan Wang, Farookh Moogat, In-Soo Y oon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Kosuke Y anagidaira, Takuyo Kodama
1Tb 4位/单元162层3D闪存，采用中央阶梯结构和CTW架构，实现15Gb/mm²面密度和60MB/s编程吞吐量。
15Gb/mm²面密度，60MB/s编程吞吐量，65µs最佳tR，2.4Gb/s IO速度
JSSC 2023第1期RF & WirelessOptical I/OPAM-4
A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP
3D集成的硅光子-CMOS平台实现100Gbps PAM4光发射机
28nm CMOS, 0.9V, 100Gbps, 240mW, 2.4pJ/bit
JSSC 2023第1期Other
A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication Ji-Soo Chang , Eunsang Jang, Y oungkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Uijong Song, Chang-Y eon Cho, Giyeong Ko, Hyunseok Hwang, Junseo Lee, Han-Sol Lee , Y ong-Il Kwon
开发了一种集成指纹传感器前端、高速处理器和安全元件的单芯片生物识别智能卡SoC。
792.5 ms总处理时间（包括防伪指纹认证）
JSSC 2023第1期RF & WirelessTime-Interleaved ADCEqualizer
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels Ahmad Khairi , Y
一篇关于在5纳米FinFET工艺中实现224Gb/s PAM4 ADC基SerDes接收器的论文
5nm FinFET, 224Gb/s, 1.41 pJ/b
JSSC 2023第1期MemoryDRAM
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX Optimized WCK Operation and A
首款采用T-coil技术的16Gb GDDR6 DRAM，通过合并多路复用器TX和优化WCK操作实现27Gb/s/pin带宽
27 Gb/s/pin with 1.35 V
JSSC 2023第1期Digital Circuits
A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10- μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration Sumeet
开发了一种高效能、多程序运行时可重构的通用数字信号处理器（UDSP）。
16-nm, 784-Core
JSSC 2023第1期Wireline I/ODRAM
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based
介绍了一种192-Gb 896-GB/s的HBM3 DRAM，采用低功耗高可靠性设计。
192-Gb 896-GB/s 1.0-V
JSSC 2023第1期MemoryDRAM
A 1ynm 125V 8Gb 16GbsPin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MA
提出基于GDDR6的1.25V 8Gb 16Gbps内存加速器，支持深度学习操作并优化性能。
1.25V, 8Gb, 16Gbps/pin, 1TFLOPS
JSSC 2023第1期RF & WirelessHigh-Speed LinkEqualizer
A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS Bingyi Y e
一款用于中短距离电气链路的112Gb/s PAM-4收发器，采用RX四抽头FFE和两阶段16路交织技术。
28nm CMOS, 112Gb/s, BER<1e-11, 20.8dB信道损耗, 2.29pJ/b能效
JSSC 2023第1期RF & Wireless
A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS
提出一种200Gb/s模拟DP-QPSK相干光接收机，采用四路时间交错采样和子采样方案，实现低功耗和高能效。
28nm CMOS, 200Gb/s, 4.6pJ/b
JSSC 2023第1期Clocking & PLLsPLL
A 56-GHz Fractional- N PLL With 110-fs Jitter Yu Z h a o , Member , IEEE
一种采用28nm CMOS工艺的56GHz分数N锁相环，具有110fs抖动和低相位噪声。
56GHz, 110fs抖动, -98dBc/Hz@1MHz, 23mW功耗, 0.1mm²面积
JSSC 2023第1期Digital Circuits
A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for
首款用于癫痫预测的神经信号处理器，集成预处理、特征提取、可重构SVM核和后处理单元，提升预测性能。
92.0%灵敏度, 0.57/h误报率, 8.44ms训练延迟, 2.31mW功耗, 6.05MHz频率
JSSC 2023第1期OtherNeural Network Accelerator
A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC
一款4纳米工艺的多模式8k-MAC神经处理单元，支持多种精度计算并优化硬件利用率。
4.26 TFLOPS/W (FP16), 11.59 TOPS/W (INT8), 1.72 TFLOPS/mm², 3.45 TOPS/mm²
JSSC 2023第1期Clocking & PLLs
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68
提出一种基于环形振荡器的超低抖动注入锁定时钟乘法器，采用功率门控注入方法实现宽注入带宽和低抖动。
65nm CMOS, 14.3mW, 0.102mm², 97fs rms jitter at 8.16GHz
JSSC 2023第1期Clocking & PLLsDRAM
A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM Y
提出一种基于LMS算法的自适应滤波器，用于消除LPDDR5移动DRAM中的电源噪声引起的抖动。
28nm CMOS, 6.4 Gb/s, 60-mV PP 1-MHz supply noise, rms jitter从27.84 ps降至4.28 ps
JSSC 2023第1期Digital Circuits
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance Y uhao Ju , Student Member , IEEE,a n dJ i eG u , Senior Member , IEEE
提出一种结合深度学习与通用计算的脉动神经网络CPU处理器，提升机器学习任务性能。
65nm, 1.8TOPs/W, 95% PE利用率
JSSC 2023第1期Digital CircuitsNeural Network Accelerator
A Threshold Implementation-Based Neural Network Accelerator With Power and Electromagnetic Side-Channel Countermeasures
基于阈值实现的神经网络加速器，有效抵御功耗和电磁侧信道攻击。
28nm CMOS, 0.95V, 125MHz
JSSC 2023第1期Digital Circuits
An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in G
提出一种能效优化的Transformer处理器，通过动态弱相关性处理降低计算能耗
未明确说明（需查阅完整论文获取具体指标）
JSSC 2023第1期Digital Circuits
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge
DIANA是一款结合数字与模拟计算的端到端混合神经网络SoC，适用于边缘计算。
22nm技术, AIMC核心峰值效率600 TOP/s/W (I/W/O: 7/1.5/6 bit), 数字加速器14 TOP/s/W (I/W/O: 8/8/8 bit)
JSSC 2023第1期Other
DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC
提出一种低功耗实时深度信号处理SoC，用于高效获取密集RGB-D数据。
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JSSC 2023第1期Digital CircuitsProcessor/CPU
Deterministic Frequency and V oltage Enhancements on the POWER10 Processor Brian V anderpool , Phillip J. Restle
POWER10处理器通过数字下垂传感器和核心节流技术提升频率并降低电压。
15%频率提升，10%核心电压降低
JSSC 2023第1期Clocking & PLLs
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC Jae-Gon Lee , Y ounsik Choi, Hoyeon Jeon , Jong-Jin Lee
全自动硬件驱动时钟门控架构，显著降低动态功耗。
17%–50%的功耗降低
JSSC 2023第1期Data Converters
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)
2022 IEEE ISSCC精选论文特刊介绍，涵盖数字架构、机器学习、存储器及有线通信等领域。
5 nm FinFET, 224 Gb/s, 38 dBs loss equalization
JSSC 2023第1期MemoryCIM
ReDCIM: Reconfigurable Digital Computing- In-Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration
提出ReDCIM架构，实现高效、高精度、高灵活性的云端AI加速。
29.2 TFLOPS/W at BF16, 36.5 TOPS/W at INT8
JSSC 2023第1期Digital Circuits
RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypt o-Processor for Multiple-Mathematical Problems
RePQC是一款支持多种数学问题的后量子密码处理器，具有高灵活性和能效。
28nm CMOS, 3.4 uJ/Op, 48 kOPS
JSSC 2023第1期Other
Regenerative Breaking Optimal Energy Recycling for Energy Minimization in Duty-C
提出一种在睡眠模式下通过反向电流回收能量的架构，显著降低系统能量损耗。
59.4% E_loss reduction, 56.6% total system energy savings
JSSC 2023第1期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE固态电路期刊由IEEE固态电路协会出版，介绍了其组织结构和领导团队。
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JSSC 2023第2期Data ConvertersNeural Network Accelerator
A 0.0046-mm2 Two-Step Incremental Delta–Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation Daniel Wendler ,D a n i e lD eD o r i g o, Mohammad Amayreh , Alexander Bleitner
一种用于高密度CMOS神经元探针的ADC前端，具有原位数字化和电极偏移电压补偿功能。
0.0046 mm²面积, 4.88 μVrms噪声, 8.57 μW功耗
JSSC 2023第2期Power ManagementBuck-Boost
A −10 to −20-V Inverting Buck-Boost Drive GaN Driver With Sub-1-μA Leakage Current Vth Tracking Technique for 20-MHz Depletion-Mode GaN Metal–Insulator–Semiconductor High-Electron-Mobility Transistors Yong-Hwa Wen, Tz-Wun Wang, Tzu-Hsien Yang, Student Member , IEEE, Sheng-Hsi Hung, Kuo-Lin Zheng
提出一种反相降压-升压驱动GaN驱动器，采用Vth跟踪技术降低漏电流至亚1μA，并集成EMI抑制功能。
0.5µm CMOS, 10-20V, 20MHz, 120V/ns, 95.8%峰值效率
JSSC 2023第2期RF & Wireless
A 13.56-MHz Wireless Power and Data Transfer System With Current-Modulated Energy-Reuse Back Telemetry and Energy-Adaptive V oltage Regulation Minjae Kim
提出一种高效无线能量与数据传输系统，采用电流调制能量复用技术，提升植入式医疗设备性能。
13.56MHz, 1.8V, 1Mb/s, 42%能量节省
JSSC 2023第2期Other
A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs
一款16nm SoC，用于噪声鲁棒的语音和NLP边缘AI推理，采用贝叶斯声音处理技术
16nm FinFET, 25mm² SoC
JSSC 2023第2期Other
A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN Y
提出一种低功耗实时手势识别系统，结合混合分类器和多数投票方案，显著提升识别精度。
65nm CMOS, 0.6V, 184μW @ 25MHz
JSSC 2023第2期Other
A 211-to-263-GHz Dual- LC -Tank-Based Broadband Power Amplifier With 147-dBm PSA
本文提出了一种基于双LC谐振腔的宽带功率放大器，采用低损耗四路功率合成器，实现了211至263 GHz的高效功率放大。
峰值功率增益16.4 dB，饱和输出功率14.7 dBm，峰值效率3.13%
JSSC 2023第2期Memory
A 389 TOPS/W, Always ON Region Proposal Integrated Circuit Using In-Memory C o m p u t i n gi n6 5n mC M O S Sumon Kumar Bose , Student Member , IEEE
提出一种基于9T-SRAM存内计算的区域提议网络，用于神经形态视觉传感器的能效优化。
389 TOPS/W能效, 1259 ft/s吞吐量@1Meps事件率
JSSC 2023第2期Digital Circuits
A 40-nm 91-mW 90-fps Learning-Based Full HD Super-Resolution Accelerator Hsueh-Y
40纳米工艺下91毫瓦功耗的90帧/秒全高清超分辨率加速器
40nm CMOS, 200MHz, 90fps, 91mW
JSSC 2023第2期Other
A 4068-MHz Active Rectifier With Cycle-Based On-Off-Delay Compensation for High-C
提出一种40.68MHz主动整流器，采用周期定时控制提升效率和电压转换比。
最大输出功率207mW，最大PCE 86%，最大VCR 96.3%
JSSC 2023第2期Medical & BioBiosignal
A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 V pp and T-CMRR of 105 dB in 180-nm CMOS
一种具有高共模干扰容忍度的433μW生物电位放大器
105 dB TCMRR, 18 Vpp CMI容忍度, 1.90 µVrms输入噪声, 433 µW功耗
JSSC 2023第2期Data ConvertersSAR ADCNeural Network Accelerator
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction Y uekang Guo
一款40nm CMOS工艺的60-MS/s 5-MHz带宽噪声整形SAR ADC，集成高线性输入缓冲器。
40nm CMOS, 2.5V/1.1V双电源, 60MS/s, 5MHz BW, 8.06mW
JSSC 2023第2期Other
A CMOS Wideband Watt-Level 4096-QAM Digital Power Amplifier Using Reconfigurable P
40nm CMOS工艺宽带瓦级4096-QAM数字功率放大器，采用可重构功率合成变压器。
40nm CMOS, 1.1/2.5V, 峰值输出功率32.67dBm, 峰值效率45.1%, 支持4096-QAM
JSSC 2023第2期RF & WirelessPLL
A D-Band Joint Radar-Communication CMOS Transceiver Wei Deng Senior Member IEE
一款采用28nm CMOS技术的D波段雷达-通信联合收发器，具有双功能模式复用器、高输出功率PA和高增益混频器。
28nm CMOS, 46GHz带宽, 13dBm输出功率, 8.3dBm OP1dB, -111.3dBc/Hz相位噪声
JSSC 2023第2期Digital Circuits
A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite
提出一种动态精度位串行计算硬件加速器，用于求解偏微分方程
65nm CMOS, 1V, 25.6MHz, 1.59nJ/iteration
JSSC 2023第2期Power ManagementLDO
A Feedforward Controlled Digital Low-Dropout Regulator With Weight Redistribution Algorithm and Body V oltage Control for Improving Line Regulation With 99.99% Current Efficiency and 0.5-mV Output V oltage Ripple Bo-Hao Chen , Tzu-Ying Wu, Kuo-Lin Zheng
提出一种采用前馈控制和权重再分配算法的数字LDO，以提高线路调节性能。
稳态输出电压纹波<0.5mV，瞬态<4mV，负载瞬变下冲<30mV
JSSC 2023第2期RF & WirelessDAC
A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS Chunxiao Hu ,Y u nY i n , Member , IEEE
一款全集成宽带数字极化发射器，采用C-DAC数字相位转换器和宽带开关变压器数字功率放大器。
40nm CMOS, 1.1V, 1.5GHz, 20.1dBm峰值输出功率, 23.7%系统效率
JSSC 2023第2期Clocking & PLLsVCO
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS
一种基于圆形三重耦合变压器技术的低相位噪声毫米波四核VCO
相位噪声-104.7 dBc/Hz @1MHz偏移，FoM 186.5 dBc/Hz @59.1GHz
JSSC 2023第2期mm-Wave
A mm-Wave Signal Generation and Background Phase Alignment Technique for
提出一种毫米波信号生成与相位自对准技术，用于可扩展相控阵系统。
65nm CMOS, 258mW, 35GHz, 140°调谐范围, 20ns切换时间, 86fs抖动
JSSC 2023第2期Other
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs
提出一种用于超结MOSFET的主动斜率控制门驱动IC，通过离散时间反馈技术降低开关损耗。
dV/dt可控至3, 4.5, 4.9 V/ns，开关损耗降低25%，开启延迟减少74%
JSSC 2023第2期OtherEnergy Harvesting
Configurable Hybrid Energy Synchronous Extraction Interface With Serial Stack Resonance for Multi-Source
提出一种可配置混合能量同步提取接口电路，支持多源能量采集
0.18-µm CMOS工艺
JSSC 2023第2期OtherClock Generation
New Associate Editor I
Jaehyouk Choi教授被任命为IEEE JSSC期刊的新副编辑，专注于模拟/混合信号集成电路研究。
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JSSC 2023第2期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊的出版信息及编委会成员介绍
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JSSC 2023第3期Other
AAD-KWS A Sub-- W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS
一款集成声学活动检测器的亚微瓦级关键词识别芯片，实现高精度与超低功耗。
28nm CMOS, 0.4V供电, MFCC 8kHz/其他200kHz, 0.36μW(静默)/0.8μW(正常)
JSSC 2023第3期Power Management
A 0.5-ms 47.5-nJ Resistor-to-Digital Converter for Resistive BTEX Sensor Achieving 0.1-to-5 ppb Resolution Y
一种用于BTEX气体检测的高能效电阻-数字转换器
110nm CMOS, 1.5V, 0.5ms测量时间, 95μW功耗
JSSC 2023第3期Other
A 112-Gb-s -82-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged P
16nm FinFET CMOS工艺下112Gb/s 4-PAM线性TIA，支持下一代数据中心光接收器。
63-dBΩ增益，32-GHz带宽，16.9 pA/√Hz噪声密度，0.9V供电，47mW功耗
JSSC 2023第3期Data ConvertersSAR ADC
A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier
一款采用三态SAR逻辑和开环逆变器残差放大器的13位高速流水线-SAR ADC。
40nm CMOS, 1.1-1.2V, 600-675MS/s, 62.8dB SNDR, 7.05mW
JSSC 2023第3期Clocking & PLLsPLLVCO
A 16-GHz DPLL Using Feedforward Phase-Error Cancellation
提出了一种采用前馈相位误差消除技术的16GHz数字锁相环，提升了相位噪声性能。
40nm CMOS, 1.1V, 5mW, 788fs rms jitter, -57.84dBc reference spur
JSSC 2023第3期Digital CircuitsNeural Network Accelerator
A1 . 8 - G Input-Impedance 0.15-μV Input-Referred- Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted
一种采用局部正反馈环的斩波放大器，实现高输入阻抗和低输入波纹。
0.18μm CMOS, 5V, 1.07mA, 1.8GΩ输入阻抗, 0.15μV输入波纹
JSSC 2023第3期OtherSAR ADCDelta-Sigma ADC
A 20-μs Turn-On Time, 24-kHz Resolution, 1.5–100-MHz Digitally Programmable Temperature-Compensated
提出一种基于快速锁定频率锁定环和Δ-Σ分数分频器的可编程温度不敏感时钟发生器
1.5–100 MHz可编程频率范围, 24-kHz分辨率, 140-ps峰峰值周期抖动, 6.8-ppm/°C温度不敏感性
JSSC 2023第3期RF & Wireless
A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband N
本文提出了一种23-40GHz相控阵接收器，采用14位相位增益管理器和宽带噪声消除低噪声放大器。
40nm CMOS, 52mW每元件, 3.8dB最小噪声系数
JSSC 2023第3期Clocking & PLLsPLL
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital P
提出一种低抖动、低带外噪声的双核分数-N数字PLL，采用新技术优化功耗与噪声。
28nm CMOS, 0.47mm², 8.5-10.5GHz, 36mW, 72fs抖动, -59.7dBc杂散
JSSC 2023第3期MemorySRAMCIM
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI
提出一种新型SRAM-CIM结构，提升能效并降低计算延迟。
28nm CMOS, 7.2ns计算延迟, 22.75 TOPS/W能效
JSSC 2023第3期Memory
A 915-1220 TOPS/W, 976-1301 GOPS Hybrid In-Memory Computing Based Always-On Image Processing for Neuromorphic Vision Sensors
提出一种基于混合内存计算的始终开启图像处理器，用于神经形态视觉传感器的图像恢复和区域提议。
915-1220 TOPS/W, 976-1301 GOPS
JSSC 2023第3期Power ManagementBoost ConverterBuck-Boost
A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current Donghee Cho
一种高效单模式双路径升降压转换器，适用于锂离子电池供电的移动设备。
94.8%峰值效率(175mΩ DCR电感), 95.58%效率(1A负载,19mΩ DCR电感)
JSSC 2023第3期Power Management
A Highly Integrated Hybrid DC-DC Converter With nH-Scale IPD Inductors
提出一种使用nH级电感的高集成度混合DC-DC转换器，峰值效率达91.2%。
130nm BCD, 9.6-12V输入, 2.15-3.3V输出, 峰值效率91.2%, 峰值功率密度1.36W/mm³
JSSC 2023第3期RF & WirelessSAR ADCHigh-Speed Link
A Jitter-Robust 40 Gb-s ADC-Based Multicarrier Receiver Front-End With 4-GS-s Baseband Pipeline-SAR ADCs in 22-nm FinFET
一种抗抖动40Gb/s基于ADC的多载波接收前端，支持三频带信号传输。
22nm FinFET, 40Gb/s, 4GS/s, BER<10-5, 3.05pJ/bit
JSSC 2023第3期Image Sensors
A Pixelated Monolithic CMOS PPG Sensor for Spatial
提出一种像素化单片CMOS PPG传感器，用于空间特征采集
114dB动态范围, 23.3µW@1V
JSSC 2023第3期Power Management
A Series-Parallel Switched-Photovoltaic DC-DC Converter
一种串联-并联切换光伏DC-DC转换器，通过周期性地将光伏电池并联以平衡电压并在不匹配条件下提取最大功率。
0.18µm CMOS, 峰值收获效率91.3%（50%电流不匹配下）
JSSC 2023第3期Other
A Threshold-Based Bioluminescence Detector With a CMOS-Integrated Photodiode Array in 65 nm for a Multi-Diagnostic
一种基于阈值、采用65nm CMOS工艺的光电二极管阵列生物发光检测器，用于微型可摄入胶囊。
59-nW active power, 25-fA/count resolution, 59-fA MDS
JSSC 2023第3期Other
A Wideband Energy-Efficient Multi-Mode CMOS
一款适用于多模式/多频段无线通信的宽带高效数字发射机。
40nm CMOS, 0.95V, 23.18-dBm RF峰值功率, 66.26%/52.59%效率
JSSC 2023第3期Other
An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and
一种基于深度学习的能效优化超分辨率加速SoC，用于移动平台的高质量图像重建。
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JSSC 2023第3期Power Management
Fully Integrating a 400 V-to-12 V DC-DC Converter in High-Voltage CMOS
首款全集成400V至12V DC-DC转换器，采用高压CMOS工艺，提升功率密度和效率。
119 mW/mm²功率密度，63.6%效率，33:1转换比
JSSC 2023第3期RF & Wireless
Millimeter-Wave Quadrature Mixed-Mode Transmitter With Distributed Parasitic Canceling and LO Leakage Self-Suppression Bingzheng Y ang , Member , IEEE, Huizhen
提出一种毫米波正交混合模式发射机，具有分布式寄生消除和LO泄漏自抑制功能。
24.03 dBm饱和输出功率，31.5%峰值系统效率，支持400-MHz 64QAM信号
JSSC 2023第3期RF & Wireless
Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and
本文介绍了一种全固态直接飞行时间激光雷达系统，通过创新的发射器和接收器设计，实现了低功耗和高分辨率。
12.5V供电下20.3W光脉冲输出，128×128 SPAD阵列
JSSC 2023第3期MemoryCIM
T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training
T-PIM是一种支持端到端设备上训练的高效能存内计算加速器
未明确提及具体性能指标
JSSC 2023第3期MemorySRAMCIM
TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and V ariable Precision Quantization Ruiqi Guo , Zhiheng Y ue ,X i nS i , Hao Li, Te Hu, Limei Tang, Y abing Wang
提出TT@CIM处理器，通过张量分解和位级稀疏优化提升内存计算能效
28nm CMOS, 5.99-to-691.13-TOPS/W峰值能效
JSSC 2023第3期Other
Table of Contents
IEEE JSSC期刊特辑论文聚焦高效能计算与传感器技术。
915-1220 TOPS/W, 976-1301 GOPS, 13b 600-675MS/s, 72-fs-Total-Integrated-Jitter
JSSC 2023第4期RF & Wireless
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
5nm CMOS工艺下基于逆变器的短距离双向通信物理层，实现50.4Gb/s/线速率和0.297pJ/bit能效。
5nm CMOS, 750mV, 50.4Gb/s/wire, 0.297pJ/bit, 1.2mm片上通道
JSSC 2023第4期Wireline I/ODRAM
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features Yesin Ryu , Sung-Gi Ahn, Jae Hoon Lee, Jaewon Park, Yong Ki Kim , Hyochang Kim , Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Sukhan Lee, Kyoung-Hwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong , Sunghwan Joo , Dajung Cho, So Young Kim, Minsu Lee, Hyunho Kim , Minhwan Kim, Jae-San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O Kim, Kyomin Sohn , Sang-Joon Hwang
本文提出了一种16GB HBM3 DRAM设计，通过源同步总线和片上纠错技术实现1024 GB/s带宽。
16GB容量，1024 GB/s带宽，8 Gb/s/pin，105°C高温稳定运行
JSSC 2023第4期RF & WirelessPhased Array
A 28-GHz Four-Channel Beamforming Front-End IC With Dual-V ector V ariable Gain Phase Shifters for 64-Element Phased Array
28GHz四通道波束成形前端IC，采用双矢量可变增益移相器技术，实现高效率和低噪声。
28GHz, 13.3dBm OP1dB, 7.2dBm线性输出功率
JSSC 2023第4期Other
A 325 F2 Physical Unclonable Function Based on Contact Failure Probability With Bit Error Rate <0.43 ppm After Preselection With 0.0177%
基于接触失效概率的物理不可克隆函数（PUF）通过理论分析确定丢弃范围，实现高稳定性和小面积设计。
0.4999均匀性，比特错误率<0.43 ppm
JSSC 2023第4期RF & WirelessPower Amplifier
A 39-GHz CMOS Bidirec tional Doherty Phased- Array Beamformer Using Shared-LUT D
本文展示了一种39GHz CMOS相控阵波束成形器，针对5G DP-MIMO应用，采用共享LUT DPD技术和双向Doherty PA-LNA设计以提高能效和面积效率。
65nm CMOS, 18.9-dBm饱和输出功率, 17.8% PAE, 4.8-dB NF
JSSC 2023第4期Data ConvertersSAR ADC
A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier Hyunchul Y oon
提出一种PVT鲁棒的电容退化动态放大器，用于低功耗流水线SAR ADC，实现65dB SNDR和79.8dB SFDR。
65nm CMOS, 0.8-1.0V, 50MS/s, 65dB SNDR, 79.8dB SFDR, 0.46mW
JSSC 2023第4期Wireline I/O
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS
Intel 4 CMOS工艺下7Gbps抗侧信道攻击的乘法掩码AES引擎
7Gbps, 65%面积开销, 4%性能开销
JSSC 2023第4期RF & WirelessDACHigh-Speed Link
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links Timothy O. Dickson , Senior Member , IEEE, Zeynep
4nm FinFET CMOS工艺中实现72GS/s 8位DAC的200Gb/s有线发射机
8-bit分辨率, 72GS/s, 288mW@0.95V, INL±0.67LSB, DNL±0.43LSB
JSSC 2023第4期Data ConvertersSAR ADC
A 773-dB SNDR 625-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-
本文提出了一种采用连续时间噪声整形技术的SAR ADC，通过去除采样开关和占空比设计实现高性能。
65nm CMOS, 77.3-dB SNDR, 625-kHz带宽, 13.5 µW功耗
JSSC 2023第4期Power ManagementBuck Converter
A 904 Peak Efficiency 48V -to-1V GaNSi Hybrid Converter With Three-Level Hybrid D
提出一种高效48V至1V混合转换器，结合三电平降压与Dickson转换器，减少元件数量并提升效率。
48V输入, 0.7-1V输出, 12A负载, 90.4%峰值效率
JSSC 2023第4期Digital Circuits
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-V ector Scaled 4-bit Quantization in 5 nm
提出一种高效执行Transformer的DNN加速器，采用每向量缩放量化技术，实现高能效推理。
5nm工艺, 0.46V, 95.6 TOPS/W, 0.67V, 1734 inferences/s/W (BERT-Base), 4714 inferences/s/W (ResNet-50)
JSSC 2023第4期MemorySRAMCIM
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for
提出一种基于C-2C电容梯度的8位SRAM存内计算宏单元，实现高能效与计算精度平衡。
22FFL工艺, 32.2TOPS/W能效, 4.0TOPS/mm²面积效率, 0.5%计算误差
JSSC 2023第4期Other
A High-V oltage Generator and Multiplexer for Electrostatic Actuation in
提出一种用于微机器人静电驱动的高压生成与多路复用芯片，支持可编程物质应用。
286 nW功耗，103 V差分电压，155 V/s切换速度
JSSC 2023第4期Image SensorsCMOS Image Sensor
A Hybrid ToF Image Sensor for Long-Range 3D Depth Measurement Under High Ambient Light Conditions Kunihiro Hatakeyama , Y u Okubo, Tomohiro Nakagome, Masahiro Makino
一种新型混合飞行时间传感器实现30米长距离3D深度测量，适用于高环境光条件。
VGA分辨率，4-tap和1-drain像素，120帧/秒（单子帧操作），室内30米/室外20米（100 klux环境光）
JSSC 2023第4期Clocking & PLLs
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration Wei-Jhih Jian
一种无参考时钟、自校准的片上相位噪声测量电路，实现242-fs周期性抖动。
28nm CMOS, 15.83mW, 275fs rms抖动分辨率
JSSC 2023第4期Data ConvertersSAR ADC
A VTC/TDC-Assisted 4 × Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW
一种采用VTCTDC辅助的四路交织38 GS/s 7位SAR ADC，具有13 GHz有效分辨率带宽和60 mW功耗。
22nm FinFET CMOS, 3.8 GS/s, 38 dB SNDR, 60 mW, 24.4 fJ/step
JSSC 2023第4期Clocking & PLLsDLLNeural Network Accelerator
A V ery High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Delta Quadrature DLL for High-Speed Data
提出一种高线性度双相位插值器，结合低噪声宽带延迟锁相环，实现3.5-11GHz频段内的高精度时钟生成。
1.2V 65nm CMOS, 7GHz, 7.8mW, 48.1fs rms jitter, -257.4dB FoM
JSSC 2023第4期RF & WirelessEnergy Harvesting
A Wireless Hysteretic Controlled Wireless Power Transfer System With Enhanced Efficiency and Dynamic Response for Bioimplants Junyao Tang , Student Member , IEEE, Lei Zhao , Student Member , IEEE
提出一种采用无线滞环控制技术的6.78MHz无线能量传输系统，实现高效能与快速瞬态响应。
68.9%峰值端到端效率，轻载效率提升20%
JSSC 2023第4期OtherSAR ADCDelta-Sigma ADC
An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer
本文提出了一种时间交织架构，解决了连续时间ΣΔ调制器中噪声整形SAR量化器的速度-分辨率瓶颈问题。
28nm CMOS, 6.4mW功耗, 0.072mm²面积, 15.625MHz带宽, 81.6dB SNDR
JSSC 2023第4期OtherNeural Interface
An AC-Coupled 1st-Order - Readout IC for Area-Efficient Neural Signal Acquisition Xiaolin Y ang , Member , IEEE
一种用于高效神经信号采集的AC耦合一阶Δ-Σ读出IC
22nm FDSOI CMOS, 0.005mm²/通道, 12.57μW/通道, 7.7μVrms AP带噪声
JSSC 2023第4期MemorySRAMProcessor/CPU
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMO
八核RISC-V处理器在末级缓存附近进行乘加运算，显著降低能耗。
1.15-GHz, 52×能效提升(全连接层), 29×能效提升(卷积层), 4.25×延迟降低
JSSC 2023第4期MemorySRAM
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology Y
基于Intel 4 CMOS工艺的高能效高带宽6T SRAM设计
0.0300-µm² SRAM单元, 访问能耗降低>80%, 宏密度提升30%
JSSC 2023第4期Other
GalEPR A Galvanically Coupled Electron Paramagnetic Resonance Spectrometer for D
提出一种用于深层组织氧合和缺氧诊断的GalEPR光谱仪，显著提升频率与穿透深度。
14 GHz/50 mm frequency/depth
JSSC 2023第4期Other
Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI
2022年VLSI技术与电路研讨会特刊介绍，首次合并技术与电路会议并线上线下同步举行。
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JSSC 2023第4期RF & WirelessClock GenerationPhased Array
New Associate Editor I T
Bodhisatwa Sadhu博士成为IEEE JSSC期刊新副编辑，专注于RF和毫米波电路与系统研究。
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JSSC 2023第4期Other
Non-Linear CNN-Based Read Channel for Hard Disk Drive With 30% Error Rate Reduction and Sequential 200-Mbits/s Throughput in 28-nm CMOS
首款基于CNN的硬盘驱动器读取通道ASIC，错误率降低30.3%
200Mbits/s, 0.86nJ/bit, ~4TOPS/W
JSSC 2023第4期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE固态电路期刊的出版信息及编委会成员介绍
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JSSC 2023第4期Other
Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-M
提出超低功耗和小面积模拟音频特征提取芯片，用于关键词识别。
65nm CMOS, 80nW, 0.53mm²
JSSC 2023第5期RF & Wireless
A 107 pJb TX 260 pJb RX Ultralow-Power MEMS-Based Transceiver With Wake-Up in IS
一款基于MEMS的超低功耗收发器，集成唤醒功能，支持FSK/OOK调制。
65nm CMOS, -11.2dBm@915MHz, 6Mb/s(TX), 2Mb/s(RX), -77.5dBm灵敏度
JSSC 2023第5期RF & WirelessTransceiver
A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD
一款用于短距离可重构FDD无线网络的2Gbps超宽带收发器
8GHz信道下19.8mW功耗，9.9pJ/b能效，-5.5dBm输出功率，-67.5dBm灵敏度
JSSC 2023第5期Other
A 28-GHz, Multi-Beam, Decentralized
28GHz模块化多波束中继阵列解决毫米波通信非视距问题
28GHz, 625Mb/s总吞吐量, 四元件阵列独立三波束
JSSC 2023第5期RF & WirelessPAM-4
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS
提出一种48 Gb/s PAM-4接收器，采用可调预游标的波特率相位检测器，优化垂直眼图开口。
48 Gb/s, BER < 10^-11, 2.42 pJ/b
JSSC 2023第5期Power ManagementBoost Converter
A Bipolar-Output Switched-Capacitor DC–DC Boost Converter With Residual-Energy-Recycling Regulation and Low Dropout Post-Filtering Techniques Min-Woo Ko
一种高效能、低噪声的双极性输出升压转换器，用于移动应用中的薄膜晶体管电路供电。
峰值效率91.7%，输出噪声28.7 µV RMS，电源抑制比-75 dB
JSSC 2023第5期Clocking & PLLsPLL
A Cryo-CMOS PLL for Quantum
本文提出了一种用于量子计算控制的4.2K低温CMOS PLL。
40nm CMOS, 4.2K, 10GHz, 37fs rms jitter, -69dBc参考杂散, 2.7mW功耗
JSSC 2023第5期Other
A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-V oltage, Low-Power Applications
28nm CMOS工艺下静态无竞争差分触发器，适用于低电压低功耗应用。
28nm CMOS, 1-0.3V, 100 dies functional at 0.28V
JSSC 2023第5期RF & WirelessPhased Array
A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
一款四通道双向D波段相控阵收发器，支持200 Gb/s无线数据传输。
130nm SiGe BiCMOS, 300/500 GHz ft/fmax, 200 Gb/s, 12.5 pJ/bit
JSSC 2023第5期MemoryNeural Network Accelerator
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing Chun-Y en Y ao , Tsung-Y en Wu , Han-Chung Liang, Y u-Kai Chen
提出一种全比特灵活的内存计算宏单元，具有高能效和小面积。
28nm CMOS, 27.7 TOPS/mm², 291 TOPS/W
JSSC 2023第5期Other
A Hierarchical Self-Interference Canceller for Full-Duplex LPW AN Applications A
提出一种用于LPWAN基站的全双工自干扰消除芯片，采用分层消除技术实现高分辨率。
65nm CMOS, 1.2V, 44.28mW, 64dB RF SI消除
JSSC 2023第5期Other
A K -Band Full 360 ◦ Phase Shifter Using Novel Non-Orthogonal V ector
提出新型非正交矢量合成方法实现K波段360度低相位误差移相器
65nm CMOS, 1.2V, 16mW, 0.15mm², 0.75°-2.08°相位误差, 0.8-0.95dB增益误差
JSSC 2023第5期RF & WirelessPower Amplifier
A Millimeter-Wave Three-Way Doherty Power Amplifier for 5G NR OFDM
一种用于5G NR OFDM的毫米波三路Doherty功率放大器，具有高效率和低失真特性。
38 GHz, 13.7%/11.0% PAE at 9.5-/11.5-dB back-off, 11.3 dBm average output power, 14.7% average efficiency, -25-dB EVM
JSSC 2023第5期RF & WirelessPower Amplifier
A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-256-1024-QAM
采用自校准技术和存储电容阵列的SCPA，支持64-256-1024-QAM信号。
28.9-dBm峰值输出功率, 43.9%峰值效率, 1.8 GHz
JSSC 2023第5期Power ManagementEnergy Harvesting
A Sub-µW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS
提出一种超低功耗太阳能收集器架构，通过减少寄生电容切换损耗实现高效能量收集。
80%效率@1μW输出，峰值80.66%@2.4μW，1.8V稳压输出
JSSC 2023第5期RF & WirelessNeural Network Accelerator
A Time-Modulated Concurrent Steerable Multibeam MIMO Receiver Array With Spectral-Spatial Mapping Using One Beamformer and Single-Wire Interface
提出一种26-33 GHz宽带MIMO接收器阵列，利用时间调制实现多波束并发和快速波束扫描。
28 dB最大转换增益, 5.78 dB噪声系数, -38 dBm输入IP1dB, 支持2.4/4.2 Gb/s 16/64 QAM调制
JSSC 2023第5期Memory
An In-Memory-Computing Charge-Domain Ternary CNN Classifier Xiangxing Y ang , Member , IEEE
提出一种基于电荷域计算的三元神经网络分类器，实现高效低功耗的MNIST分类。
40nm LP CMOS, 549 FPS, 96 µW, 97.1% MNIST准确率, 0.18 µJ/分类
JSSC 2023第5期Other
An Integrated-Circuit Node for High-Spatiotemporal Resolution Time-Domain Near-I
一款用于非侵入式脑功能成像的集成芯片，支持高时空分辨率时间域光学成像。
70ps时间分辨率，100MHz激光重复频率，80mW总功率
JSSC 2023第5期Digital Circuits
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network
提出负裕度时序错误检测方法，提升神经网络加速器性能并降低功耗。
28-nm CMOS, 238%频率增益或59%功耗降低
JSSC 2023第5期Power ManagementTDC
CMOS SPAD Line Sensor With Fine-Tunable Parallel Connected Time-to-Digital Converters for Raman Spectroscopy Tuomo Talala
一款用于时间分辨拉曼光谱的256通道CMOS SPAD线传感器，具有可调时间分辨率和实时暗计数测量能力。
25.6–65 ps可调时间分辨率，3.2–8.2 ns动态范围，43.7 ps中值时间偏移，680 kHz最大激发脉冲率
JSSC 2023第5期Digital Circuits
DepFiN: A 12-nm Depth-First, High-Resolution CNN Processor for IO-Efficient Inference
DepFiN处理器采用深度优先执行模式优化高分辨率CNN推理，显著降低内存带宽和能耗。
12nm工艺，0.6V电压下20TOPS/W峰值能效，MC-CNN-fast网络3.95TOPS/W（含IO功耗）
JSSC 2023第5期RF & Wireless
Guest Editorial 2022 Radio Frequency Integrated Circuits Symposium T HIS Special
2022 RFIC研讨会精选论文扩展版，涵盖低功耗RF到高数据率毫米波无线系统创新。
28-nm CMOS, 65-nm CMOS, 45-nm SOI CMOS
JSSC 2023第5期MemorySRAM
In Situ Storing 8T SRAM-CIM Macro for Full-Array
提出一种双向8T SRAM-CIM宏单元，实现全阵列布尔逻辑运算和原位存储，提升计算效率和能效。
28nm CMOS, 0.66V, 1851.4 GOPS, 270.5 TOPS/W
JSSC 2023第5期RF & Wireless
Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter
提出一种非均匀时间逼近滤波器技术，用于毫米波接收机以抑制干扰信号。
28nm CMOS, 33.7GHz载频, >45dB干扰抑制, 100MSymbol/s 64-QAM信号下EVM -30.9dB
JSSC 2023第5期Memory
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference Bo Zhang , Student Member , IEEE
提出一种可编程存内计算加速器PIMCA，用于低精度DNN推理，实现高能效计算。
28nm CMOS, 1V, 42MHz, 437 TOPS/W, 49 TOPS
JSSC 2023第5期RF & WirelessPLL
PLL Fractional Spur’s Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter Kyumin Kwon , Student Member , IEEE,O m a rA .B .A b d e l a t t y, Student Member , IEEE, and David D. Wentzloff , Senior Member , IEEE
本文提出了一种用于蓝牙低能耗发射器的全数字锁相环设计，通过新型时间数字转换器和校准方案降低分数杂散。
频率范围1.8–2.7 GHz，功耗3.91 mW@2.4006 GHz，FoM -220.7 dB
JSSC 2023第5期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊的出版信息及编委会成员介绍
无
JSSC 2023第6期Digital CircuitsNeural Network Accelerator
A0 . 5 - m/√ Hz Dry-Electrode Bioimpedance Interface With Current Mismatch Cancellation and Input Impedance of 100 M  at 50 kHz Qinjing Pan
一种用于干电极生物阻抗监测的高输入阻抗、低噪声传感器接口IC
100 MΩ输入阻抗@50 kHz, 0.5-mV/√Hz灵敏度@1 Hz, 106 dB SNR
JSSC 2023第6期Power Management
A3 . 6 8a Frms Resolution Continuous-Time Bandpass  Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μmC M O S
提出一种超高分辨率、高能效的连续时间带通电容-数字转换器。
3.68 aFrms分辨率，183 dB Schreier品质因数
JSSC 2023第6期RF & Wireless
A 0.6–1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer
一种低功耗N路径谐波抑制变压器混频器优先接收器，适用于窄带物联网应用。
22nm FD-SOI, 0.6-1.8mW, 300MHz-3.0GHz, 3.4-4.8dB NF, 14-18dBm OOB-IIP3
JSSC 2023第6期Data ConvertersDelta-Sigma ADC
A 12-V 287- μW 940-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC Lingxin Meng Y
一种低功耗高精度的12V 2.87μW 94.0dB SNDR离散时间2-0 MASH ΔΣ ADC
55nm CMOS, 12V, 2.87μW功耗, 94.0dB SNDR, 96.9dB动态范围, 1kHz带宽, OSR=125
JSSC 2023第6期RF & Wireless
A − 124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency
本文提出了一种抗干扰高灵敏度的BFSK多通道唤醒接收器，适用于LPWAN应用。
55nm CMOS, -124 dBm sensitivity, 781 µW (always-on mode), 114 µW (duty-cycling mode)
JSSC 2023第6期Clocking & PLLsPLL
A 20-GHz PLL With 20.9-fs Random Jitter Yu Z h a o , Member , IEEE
一款20GHz整数N分频PLL，采用双沿采样相位检测器和新型反馈分频器重定时方法，实现209fs随机抖动。
28nm CMOS, 20.9fs rms抖动(10kHz-40MHz), -66dBc杂散, 12mW功耗
JSSC 2023第6期Data Converters
A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC Y
提出一种15位自定时增量式ADC，适用于事件驱动应用，功耗低至496μW。
93-dB SNR, 0.37 ms转换时间, 4.96-µA电流, 1-V电源, Schreier FoM 177.3 dB
JSSC 2023第6期RF & WirelessEnergy Harvesting
A 6.78-MHz Wireless Power Transfer System With Inherent Wireless Phase Shift Control Without Feedback Data Sensing Coil Xianglong Bai ,Y a nL u , Senior Member , IEEE
提出一种6.78MHz无线电力传输系统，采用差分D类功放和延迟调谐整流器，实现高效无线相位控制。
峰值端到端效率77%，最大输出功率0.9W（3.3V输出）
JSSC 2023第6期Clocking & PLLsPLLNeural Network Accelerator
A Low-Spur Fractional-N PLL Based on a Time-Mode
介绍了一种基于时间模式算术单元的低抖动、低杂散分数N锁相环。
182-fs rms jitter, 3.5-mW power consumption, worst fractional spur below −59 dBc
JSSC 2023第6期Other
A Pitch-Matched Low-Noise Analog Front-End With Accurate Continuous Time-Gain Compensation for High-Density Ultrasound Transducer Arrays Peng Guo , Student Member , IEEE, Zu-Y ao Chang, Emile Noothout, Hendrik J. V os , Member , IEEE, Johan G. Bosch , Member , IEEE, Nico
本文提出了一种紧凑型超声接收器模拟前端电路，具有线性dB连续增益控制。
180nm BCD, 0.8mW, 1.31pA/√Hz
JSSC 2023第6期Data ConvertersSAR ADC
A Single-Channel V oltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS
提出一种采用异步流水线逐次逼近技术的8位8GS/s时域ADC，突破传统速度限制
28nm CMOS, 0.9V/0.7V, 8GS/s/5.05GS/s, 39.2dB/37.6dB SNDR
JSSC 2023第6期Power Management
A Thermoelectric Energy-Harvesting Interface With Dual-Conversion Reconfigurable DC–DC Converter and Instantaneous Linear Extrapolation MPPT Method
提出一种具有双转换可重构DC-DC转换器和基于时间的瞬时线性外推MPPT方法的热电能收集接口。
0.2V输入电压下峰值端到端效率90.48%，MPPT误差最大2.0%
JSSC 2023第6期RF & Wireless
A mm-Wave Frequency Modulated Transmitter Array for Superior Resolution in Angular Localization Supporting Low-Latency Joint Communication and Sensing Naga Sasikanth Mannem , Student Member , IEEE,E l h a mE r f a n i ,Member , IEEE, Tzu-Y
提出一种毫米波调频发射阵列，实现超高分辨率角度检测和通信一体化。
28-GHz四元件多模式FMA发射阵列
JSSC 2023第6期Digital Circuits
An Energy-Efficient Doubl e Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices
首款支持双棘轮协议且具备后向保密性的物联网节能加密处理器
40nm CMOS, 0.56V, 16MHz, 1.03mm², 227k gates, 1.18mW
JSSC 2023第6期Power ManagementLDO
An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and
一种无需输出电容的可综合数字LDO，采用比较器触发振荡器实现高效调节。
28nm CMOS, 0.5-1.0V, 160-480mA, 7.7-241µA, 1.4ns响应时间
JSSC 2023第6期Power ManagementBuck Converter
An SC-Parallel-Inductor Hybrid Buck Converter With Reduced Inductor V oltage and Current
提出一种降低电感电压和电流的SC-并联电感混合降压转换器，采用系列连接飞电容和并联SC路径，实现高效能和小体积。
峰值效率92.9%，峰值电流密度0.3 A/mm²，最大输出电流1.2A
JSSC 2023第6期mm-Wave
Broadband mm-Wave Current/V oltage Sensing-Based VSWR-Resilient True Power/Impedance Sensor Supporting Single-Ended Antenna Interfaces David Munzer , Student Member , IEEE, Naga Sasikanth Mannem , Student Member , IEEE, Jeongseok Lee , Student Member , IEEE,a n dH u aW a n g, Senior Member , IEEE
提出一种宽带毫米波电流电压传感器，支持单端接口，抗VSWR干扰，用于高性能射频前端。
34 GHz时功率传感误差≤±1 dB（3:1 VSWR），22–41 GHz时≤±3.4 dB（3:1 VSWR），动态范围>21.46 dB（27–41 GHz）。
JSSC 2023第6期Power Management
Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS
介绍了一种低功耗全集成毫米波参数上变频电路的设计方法。
60GHz, 1.5dB转换增益, 618µW功耗, 5GHz 3-dB IF带宽
JSSC 2023第6期RF & WirelessLNANeural Network Accelerator
Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting
提出一种基于逆变器的低温低噪声放大器，用于超导量子比特读出。
28nm CMOS, 4.2mW功耗, 6-8GHz工作频率, 0.4-0.7dB噪声系数
JSSC 2023第6期RF & Wireless
Dual-Photodiode Differential Receivers Achieving Double Photodetection Area for Gigabit-Per-Second Optical
本文提出两种双光电二极管差分光接收器，实现双倍光检测面积，支持千兆光无线通信。
2 Gb/s, BER 10^-9
JSSC 2023第6期RF & Wireless
Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Applications in a Zero-Change 45-nm CMOS-SOI Process
首款全集成电子-光子超声接收器阵列，用于内窥镜应用。
5.53 × 3.03 mm, 74 dB传感器工作范围, 9-bit SAR ADC
JSSC 2023第6期Other
Improving Linearity in CMOS Phase
提出一种改进线性度的CMOS相位插值器，采用积分模式实现高相位线性度。
13.3 GHz, 9-bit分辨率, 6-mW功耗, 0.006 mm²面积
JSSC 2023第6期OtherCMOS Image Sensor
New Associate Editor I
Neale A. W. Dutton 被任命为 IEEE JSSC 期刊的新任副编辑，专注于 CMOS 图像传感器研究。
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JSSC 2023第6期Other
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration
SamurAI是一款多功能物联网节点，结合低功耗事件驱动和嵌入式ML加速，满足多样化能耗和处理需求。
1.7-MOPS, 207-ns wake-up
JSSC 2023第6期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
本文介绍了IEEE固态电路学会的组织结构和领导团队。
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JSSC 2023第6期Digital CircuitsCIM
TranCIM: Full-Digital Bitlin e-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes
提出基于数字存内计算的Transformer加速器TranCIM，支持动态稀疏注意力计算，显著降低能耗。
15.59 µJ/Token (BERT-base模型), 能效比现有方案提升12.08×–36.82×
JSSC 2023第7期Clocking & PLLs
A1 -μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/◦C and Single-Point Trimmed 8.7-ppm/◦C Stability From − 40 ◦Ct o9 5 ◦C
提出一种无需相反温度系数电阻的RC振荡器，通过三点数字修调和温度补偿技术提高频率稳定性。
65nm CMOS, ±140 ppm频率误差(-40°C~95°C), 83-ppm/V电压灵敏度, 1.3-ppm Allan偏差, 1μW/MHz能效
JSSC 2023第7期Other
ASCH-PUF: A “Zero” Bit Error Rate CMOS Physically Unclonable Function With Dual-Mode Low-Cost Stabilization
提出一种零误码率的CMOS物理不可克隆函数ASCH-PUF，采用双模式自动自检自愈技术。
65nm CMOS, 0.7-1.4V, 0 BER (<1.77E−9), -20°C–125°C
JSSC 2023第7期Data ConvertersSAR ADCNeural Network Accelerator
A 1-GSs 68-b Cryo-CMOS SAR ADC for
一款用于量子计算的1GS/s 68位低温CMOS SAR ADC，支持多通道频率复用输入。
40nm CMOS, 1GS/s, 6-8位分辨率, 36.2dB SNDR, 200pJ/conv-step FOM
JSSC 2023第7期OtherEnergy Harvesting
A 1 mm 1 mm CGM System on Die Achieving 165-nAmM In Vivo Resolution and 040-mML
提出一种基于16反向散射技术的1mm²片上系统，实现高精度连续血糖监测。
65nm CMOS, 0.25%遥测误差, 0–40 mM/L检测范围, 1.65 nA/mM分辨率
JSSC 2023第7期RF & Wireless
A 220-GHz Sliding-IF Quadrature Transmitter and Receiver Chipset for High Data R
介绍了一种220 GHz滑动中频正交收发芯片组，支持高阶调制，采用0.13µm SiGe BiCMOS工艺。
0.13µm SiGe BiCMOS, fT/fmax=300/500 GHz, 42GHz RF带宽, 38dB CG, 8.5dBm Psat
JSSC 2023第7期RF & WirelessPAM-4
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces Y
一种25Gb/s单端PAM-4接收器，采用时间窗LSB解码器，提升高速内存接口能效。
28nm CMOS, 0.008mm², 0.34pJ/bit@25Gb/s
JSSC 2023第7期Digital Circuits
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor
28纳米8位浮点张量核心CNN训练处理器，提升能效与速度
28nm CMOS, 16.4 TFLOPS/W, 7.3× FLOPs reduction, 4.7× training latency speedup
JSSC 2023第7期Other
A 30-GHz Class-F Quadr ature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness
提出一种利用变压器实现Class-F操作的30GHz低相位噪声正交DCO，通过相位偏移解决闪烁噪声问题。
相位噪声-112dBc/Hz@1MHz, FoM -185dB, 调谐范围18%, 镜像抑制比>47dB
JSSC 2023第7期Power ManagementBoost ConverterNeural Network Accelerator
A 4–40 V Wide Input Range Boost Converter With the Protection Re-Cycling Technique for 200 W High Power LiDAR System in a Long-Distance Object Detection Si-Yi Li, Sheng Cheng Lee, Sheng-Hsi Hung, Zheng-Lun Huang, Ke-Horng Chen
提出一种采用保护再循环技术的高转换比升压转换器，适用于宽输入电压范围，保护eGaN功率FET并提升效率。
440V输入范围(4V-40V)
JSSC 2023第7期MemorySRAM
A 7-nm FinFET 12-TBsmm 2 3D-Stacked SRAM Module With 07-pJb Inductive Coupling I
7纳米FinFET工艺下开发的3D堆叠SRAM模块，采用电感耦合技术实现低功耗高速通信
0.7 pJ/bit, 8.5 Gb/s/link, 1.2-TB/s/mm2
JSSC 2023第7期Other
A Baseline-Tracking Single-Channel I/Q Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring Chan Sam Park , Student Member , IEEE, Hyunjoong Kim , Student Member , IEEE
提出一种具有宽范围精细基线跟踪能力的阻抗体积描记IC，用于颈带式心血管监测。
145.2-dB DR, 103.5-dB SNR
JSSC 2023第7期Data ConvertersDACSRAM
A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference
提出一种基于混合集成ADC和输入的位串行SRAM计算设计，提升能效和精度。
153–2453.76 TOPs/W
JSSC 2023第7期Data Converters
A Miniaturized 3-D-MRI Scanner Featuring an HV -SOI ASIC and Achieving a 10 × 8 × 8m m 3 Field of View
本文介绍了一种基于HV-SOI ASIC的微型3D MRI扫描仪，具有高分辨率和快速成像能力。
0.52-T永磁体, 6mm²芯片, 110×117×250μm³分辨率
JSSC 2023第7期Other
A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging Daniel Krüger
便携式CMOS自旋共振系统实现高分辨率光谱和成像
光谱分辨率<0.05 ppm (1.1 Hz), 成像分辨率67×67×83 µm³
JSSC 2023第7期RF & Wireless
A Reconfigurable Phase-Time Array Transmitter Achieving Keyless Secured Transmission and Multi-Receiver Localization for Low-Latency Joint Communication and Sensing
提出一种可重构相位时间阵列发射机，实现无密钥物理安全通信与快速多接收器定位。
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JSSC 2023第7期Analog Circuits
A Reflection-Mode N -Path Filter Tunable F r o m6t o3 1G H z Sandeep Hari , Student Member , IEEE, Cody J. Ellington
一篇关于6至31GHz反射模式N路径可调滤波器的IEEE JSSC论文，采用45nm SOI技术实现。
6-31GHz可调范围，最大3dB RF带宽0.47GHz，插入损耗<7dB
JSSC 2023第7期Clocking & PLLsVCO
A Wideband Mode-Switching Quad-Core VCO Using Compact Multi-Mode Magnetically Coupled LC Network
提出一种采用紧凑多模磁耦合LC网络的四核毫米波压控振荡器，实现宽调谐范围和低相位噪声。
12.1-32.0 GHz调谐范围，-103.2 dBc/Hz相位噪声，5.6-22.5 mW功耗
JSSC 2023第7期RF & Wireless
An Ultra-Low-V oltage 24-GHz Flicker-Noise-Free RF Receiver Front End Based on S
本文提出了一种基于超低电压的2.4GHz射频接收器前端架构，通过消除闪烁噪声，实现了窄带通信标准的零中频拓扑。
28nm CMOS, 0.5-0.6V, 36-40dB转换增益, 11.5dBm OIP3, 4.5dB噪声系数
JSSC 2023第7期RF & WirelessPhased Array
Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave
本文提出了一种用于5G/6G无线系统的可重构相控阵芯片间接口技术。
23 dB转换增益, 6.2 dB噪声系数, 116.5 mW功耗
JSSC 2023第7期RF & WirelessNeural Network Accelerator
Digital to RF Wideband Multi-Standard Multi-Path Transmitter Reza Ehsani Alashti
本文提出了一种基于八路径架构的多标准数字射频发射器，覆盖300 MHz至1.5 GHz频段，谐波和C-IMD3失真产物抑制优于-40 dBc。
0.18-µm CMOS, 0.58 mm², 10.6-17.6 dBm输出功率, 3.6%-19.7%效率
JSSC 2023第7期MemorySRAMNeural Network Accelerator
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing Y oshisato Y okoyama ,K o j iN i i , Senior Member , IEEE, Y uichiro Ishii
提出一种动态功耗降低技术，通过自适应字线脉冲控制减少双端口8T SRAM的读写功耗。
40nm/28nm/7nm Fin-FET, 读写功耗分别降低6%-13%和13%-28%, 无速度损失
JSSC 2023第7期Other
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices
提出自整流铁电隧道结交叉阵列，实现双模式操作（TCAM/BCAM/PUF），具有超高密度和低能耗。
2.05 fJ/search/bit, Hamming weight of 0.5000, >84.2% area reduction
JSSC 2023第7期Other
Guest Editorial IEEE 2022 European Solid-State Circuits Conference T HIS Special
2022年欧洲固态电路会议精选论文，涵盖智能电子技术的前沿研究。
28nm CMOS, <10KHz闪烁噪声角频率, <0.05ppm光谱分辨率, 67×67×83µm³成像分辨率, 4-40V电池电压波动保护
JSSC 2023第7期MemorySRAMNeural Network Accelerator
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization
IMPACT是一款22nm FD-SOI工艺的低精度边缘CNN加速器，具有813 TOPS/W的计算效率。
813 TOPS/W, 64 MHz, 4.2 POPS/W, 146 TOPS/mm2
JSSC 2023第7期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊的出版信息及编委会成员介绍
无
JSSC 2023第8期Other
A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm 2
一种基于时间交错多级开关电容的0.2-2 GHz可编程射频延迟元件，实现百纳秒级宽带延迟。
45nm SOI CMOS, 1V, 0.2-2GHz, 2.55-448.6ns可编程延迟, <0.12%延迟变化, 2.42ns延迟步进, 330ns/mm2面积效率, 26dB增益, 7.4dB噪声系数, 74mW功耗
JSSC 2023第8期RF & WirelessHigh-Speed Link
A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects
提出一种采用斐波那契编码的单端串扰消除技术的高密度互连收发器。
28nm CMOS, 0.90 Tb/s/in, 1.29 pJ/b, BER<10−12
JSSC 2023第8期Analog Circuits
A 100-to-10-kHz 5.4-to-216-µW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for MEMS
提出一种适用于物联网MEMS加速度计的动态放大器闭环读取电路，解决增益变化问题。
0.18-µm CMOS, 1.8V, 10 kHz to 1 MHz, 100 Hz to 10 kHz, 5.4 to 216 µW
JSSC 2023第8期Other
A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/◦C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI
提出一种基于自偏置CMOS的nA级温度无关电流基准，显著减小面积。
65nm: 0.7V, 1.1nA, 213ppm/°C; 22nm: 0.9V, 0.9nA, 565ppm/°C
JSSC 2023第8期Other
A 120-GHz Class-F Frequency Doubler With 7.8-dBm POUT in 55-nm Bulk CMOS
基于EKV模型设计55nm CMOS工艺的120GHz Class-F倍频器，输出功率达7.8dBm。
112–125 GHz带宽, 7.8 dBm输出功率, -0.46 dB转换增益, 6.8%效率, 88 mW功耗, 0.13 mm²核心面积
JSSC 2023第8期RF & WirelessPLL
A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation
一款采用异质结架构的300GHz CMOS接收器，集成三个PLL以缓解相位失配问题。
28nm CMOS, 噪声系数16-20dB, 增益17-21dB, 1dB压缩点-17.3dBm, 270GHz PLL相位噪声-105dBc/Hz@10MHz
JSSC 2023第8期RF & WirelessCharge Pump
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module
研究了一种改进SSO噪声和参考电压裕度的PAM-3收发器，采用地参考信号和电容峰值技术。
28nm CMOS, 33 Gb/s/pin, 1.09 pJ/b
JSSC 2023第8期Other
A 334 µW 0.158 mm 2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom–Cook Multiplication
本文提出了一种基于Toom-Cook乘法器的低功耗、小面积Saber后量子加密加速器。
0.158 mm², 334 µW
JSSC 2023第8期Data ConvertersSAR ADCNeural Network Accelerator
A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET
一款38GS/s 7位流水线-SAR ADC，采用速度增强型自举开关和输出电平移位技术
22nm FinFET, 38GS/s, 41.9fJ/conv.-step, 20GHz 3-dB带宽
JSSC 2023第8期RF & Wireless
A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength Abdelrahman H. Ahmed
提出一种支持528 Gb/s的双极化硅光子相干接收前端，优化噪声和谐波失真。
75.5 dB增益, 42 GHz带宽, 18.5 pA/√Hz输入参考噪声
JSSC 2023第8期RF & Wireless
A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base S
本文首次提出了一种适用于5G微基站的高线性度接收机，通过三种技术实现了宽频带和高线性度。
40nm CMOS, 1.3V, 100MS/s
JSSC 2023第8期RF & WirelessPower AmplifierNeural Network Accelerator
A Predistortion-Less Digital MIMO Transmitter With DTC-Based Quadrature
22nm FD-SOI工艺的无预失真数字MIMO发射机，采用DTC校准实现高线性与低功耗。
80MHz 1024QAM EVM<-39.4dB, 1.18Gbps, 1.64-3.28GHz
JSSC 2023第8期Clocking & PLLs
A Study of Injection Locking in Oscillators and
研究振荡器和分频器中注入锁定的时变模型及其优化应用。
26-73 GHz, 1.88-4.76 mW
JSSC 2023第8期Digital Circuits
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array Chengshuo Y u
提出一种基于32×32可重构PE阵列的时域波前计算加速器，用于解决最短路径等问题。
65nm CMOS, 776 pJ per task
JSSC 2023第8期Digital CircuitsNeural Network Accelerator
An 18-MS/s 76-dB SNDR Continuous-Time 16 Modulator Incorporating an Input V oltage Tracking GmC
提出一种高线性度连续时间16调制器，采用输入电压跟踪技术消除非线性。
18-MS/s, 76.5-dB SNDR, 93-dB SFDR, 3.21 mW
JSSC 2023第8期Clocking & PLLsPLLVCO
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL Yizhuo Wang, Jiahe Shi
提出一种双模式VCO，通过对称8字变压器和电容阵列补偿模式不平衡，实现宽带低抖动频率合成。
7.9–14.3 GHz, 14.1–17.2 mW, 0.18 mm², -115 dBc/Hz, <85 fs rms jitter
JSSC 2023第8期RF & WirelessPower Amplifier
Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS Johan Nguyen , Khaled Khalaf
设计了一款60 GHz 64-QAM极坐标发射机，采用28nm CMOS工艺，实现高效无线通信。
28nm CMOS, 64 GHz, 10.56-Gb/s, -27.8-dB EVM, 25.9% peak drain efficiency
JSSC 2023第8期Power ManagementEnergy HarvestingNeural Network Accelerator
Fully Integrated Frequency-Tuning Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting Chao Xie, Student Member , IEEE, Guangshu Zhao, Student Member , IEEE
提出首个全集成同步电荷提取接口，提升能量提取效率和输出功率。
最大输出功率提升率8.14×，带宽提升405%
JSSC 2023第8期OtherTransceiver
Low-Power Process and Temperature-Invariant Constant Slope-and-Swing Ramp-Based
提出一种低功耗、工艺和温度不变的高分辨率线性相位插值器，适用于多天线系统。
65nm CMOS, 503µW, 4.88ps分辨率, 1.6GHz, 0.021mm²
JSSC 2023第8期Other
New Associate Editor I
Ben Keller被任命为IEEE JSSC期刊的新副编辑，专注于数字电路和机器学习加速器研究。
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JSSC 2023第8期Image SensorsTDC
Spatially Resolved Event-Driven 24 × 24 Pixels SPAD Imager With 100% Duty Cycle for Low Optical Power Quantum Entanglement Detection Fabio Severini , Iris Cusini , Francesca Madonini , Davide Brescia, Robin Camphausen , Álvaro Cuevas
提出一种基于SPAD的高效单光子敏感成像器，实现100%占空比和低功耗量子成像。
25.8%探测效率，100%占空比，330ns读出时间
JSSC 2023第8期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE固态电路期刊由IEEE固态电路学会出版，提供会员信息和学会领导层介绍。
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JSSC 2023第8期MemoryEmerging Memory
TinyV ers: A Tiny V ersatile System-on-Chip With State-Retentive eMRAM for ML Inference at the
TinyVers是一款超低功耗多功能SoC，支持边缘设备的机器学习应用。
17.6 GOPS, 1.7 µW to 20 mW, 17 TOPS/W
JSSC 2023第9期Other
A 0.4-4 THz p-i-n Diode Frequency Multiplier in 90-nm SiGe BiCMOS
90nm SiGe BiCMOS工艺下实现的0.4-4 THz p-i-n二极管倍频器，具有高谐波辐射能力。
0.39 THz时EIRP 13 dBm，0.78 THz时EIRP -3.8 dBm，最高测至4.03 THz
JSSC 2023第9期Other
A 0.4-V 0.0294-mm 2 Resistor-Based Temperature Sensor Achieving ±0.24 ◦C p2p Inaccuracy From −40 ◦C to 125 ◦C and 385 fJ · K2 Resolution FoM in 65-nm CMOS Dan Shi , Ka-Meng Lei
一种基于电阻的超低压温度传感器，适用于能量收集物联网设备，具有高精度和低功耗。
65nm CMOS, 0.4V, 10.4µW, ±0.24°C (p2p), 385 fJ·K²
JSSC 2023第9期RF & Wireless
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated V oltage Modulation for Low-Power
一种采用集成电压调制技术的低功耗单端发射器，适用于内存接口。
16 Gb/s/pin, 0.85 pJ/bit, -12.6 dB 信道损耗
JSSC 2023第9期Other
A 1175155-GHz SiGe 12 Frequency Multiplier Chain With Push-Push Doublers and a G
一款基于SiGe工艺的D波段12倍频链，采用推挽式倍频器和三倍频器设计。
输出功率3.5 dBm，3-dB带宽37.5 GHz（117.5-155 GHz），功耗0.64 W
JSSC 2023第9期RF & WirelessPhased Array
A 1.2-mW/Channel Pitch-Matched Transceiver ASIC Employing a Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3-D
一种低功耗小面积微束形成收发器ASIC，用于3D经囟门超声成像。
12mW, 10MHz, 100µm-pitch
JSSC 2023第9期Data ConvertersNeural Network Accelerator
A 1 V 107 µW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC Zhaonan Lu H
一种1V供电、107µW功耗的15位伪伪差分增量缩放ADC
89.9dB SNR/0.378ms转换时间/1.07µW@1V
JSSC 2023第9期OtherDACNeural Network Accelerator
A 26.6–119.3-µW 101.9-dB SNR Direct Digitization Bio-Impedance Readout IC Tan-Tan Zhang
一种高功率噪声效率的直接数字化生物阻抗读出IC，采用ΔΣ调制和反馈电流导向DAC技术。
101.9-dB SNR, 4-Hz带宽, 0.1-Hz 1/f噪声角, 152.6-dB FoM
JSSC 2023第9期Other
A 33-Gbs SPAD-Based Quantum Random
提出一种基于SPAD的量子随机数生成器，采用量子随机触发器方法，并通过建模和补偿熵降级实现高效随机数生成。
3.3 Gb/s
JSSC 2023第9期Data ConvertersDelta-Sigma ADC
A 372 µW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization Yuekang Guo
提出一种嵌套式Delta-Sigma调制器结构，通过混合模拟数字设计实现高能效和低失真。
372 µW, 10 kHz带宽, 109.2 dB SNDR, 183.5 dB FoM S
JSSC 2023第9期Data ConvertersSAR ADC
A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion
提出一种用于DNN加速器的4位混合信号MAC宏，仅需一次ADC转换完成512次4×4位MAC运算。
65nm CMOS, 56.3 GOPS, 345.3µW, 164 TOPS/W
JSSC 2023第9期Data ConvertersSAR ADC
A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating
提出一种带宽自适应的流水线SAR ADC，采用三极联浮动反相放大器实现高能效和低噪声。
40nm CMOS, 40 MS/s, 821 µW, SNDR 75.7 dB
JSSC 2023第9期Data ConvertersPLL
A Calibration-Free Fractional- N Analog PLL With Negligible DSM
提出一种无需校准的分数N模拟PLL，通过过采样DSM显著降低量化噪声。
4.884 GHz, 154-fs rms jitter, FOM 255.8 dB
JSSC 2023第9期Clocking & PLLs
A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-
提出一种基于数字PLL的低功耗相位调制器，采用非均匀时钟补偿和相位域数字预失真技术，实现低误差向量幅度。
40nm CMOS, 2.7–3.9 GHz载波频率, 40MHz参考频率, -47dB EVM（64-PSK调制）
JSSC 2023第9期RF & Wireless
A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-
一种全反射Wi-Fi兼容反向散射通信系统，提升通信距离并实现低功耗。
65nm CMOS, 唤醒接收机功耗4.5µW, 灵敏度-43.5dBm, 同步接收机功耗4.8µW, 同步精度150ns, 反向散射功耗32-38µW, 通信距离13-23m
JSSC 2023第9期mm-Wave
A Highly Accurate and Sensitive mmWave Displacement-Sensing Doppler Radar With a Quadrature-Less Edge-Driven
一种高精度毫米波多普勒雷达，用于位移和振动传感，消除检测零点。
65nm CMOS, 39GHz, 110mW, 4µm静态精度, 39nm振动灵敏度(10kHz)
JSSC 2023第9期RF & WirelessPower Amplifier
A Ka-Band InP HBT MMIC Power Amplifier With 1981 IP3P dc LFOM at 48 GHz Kevin W
本文介绍了一种在48 GHz下具有19.8:1 IP3/Pdc线性度指标的Ka波段InP DHBT功率放大器设计。
36.1 dBm IP3, 21.2 dBm P1dB, 28.3% PAE
JSSC 2023第9期Clocking & PLLsPLLClock Generation
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated
一种基于数字Bang-Bang PLL的新型LO移相系统，具有高精度和低功耗特性。
28nm CMOS, 20mW功耗, 0.7毫度分辨率, 0.76° rms相位精度
JSSC 2023第9期Other
A Single-Trim Frequency Reference System With 0.7 ppm/°C From −63 ◦C to 165 ◦C Consuming 210 µW at 70 MHz Alexander S. Delke
提出一种单点温度修调和批量校准的高精度低功耗频率参考系统，替代晶体振荡器。
0.13µm HV CMOS SOI, 3V, 64µA, ±93ppm (-63°C~165°C), 0.69mm²
JSSC 2023第9期OtherEnergy Harvesting
A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric
提出一种共享电容同步开关整流器，无需电感或专用飞电容，实现高效压电能量收集。
78%电压翻转效率，7.58倍功率提升
JSSC 2023第9期RF & WirelessPower Amplifier
A Wideband Digital-Intensive Current-Mode Transmitter Line-Up
提出一种基于电流模式直接数字射频调制器的能效无线发射机架构。
40nm CMOS, 19.6-dBm RF peak output power, 20% overall TX system efficiency
JSSC 2023第9期Analog CircuitsLNA
Design Aspects of Single-Ended and Differential SiGe Low-Noise Amplifiers Operating Above fmax/2 in Sub-THz/THz
本文研究了基于130nm SiGe BiCMOS工艺的超高频低噪声放大器设计，探索了在fmax/2以上频率的性能表现。
235GHz单端LNA:7.8dB增益/18mW功耗, 290GHz差分LNA:12.9dB增益/68mA@2V
JSSC 2023第9期RF & Wireless
Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor
IEEE JSSC 2022年特刊展示BiCMOS和化合物半导体集成电路技术进展，包括InP HBT和SiGe BiCMOS时钟生成电路及5G功率放大器。
最高谐波频率4 THz，频率范围27 GHz–48 GHz
JSSC 2023第9期Wireline I/OOptical I/O
New Associate Editor I
Samuel Palermo教授成为IEEE JSSC期刊的新任副主编，专注于高速SerDes电路和硅光子互连技术。
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JSSC 2023第9期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
本文介绍了IEEE固态电路期刊的出版信息及固态电路学会的领导团队。
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JSSC 2023第10期RF & WirelessVCOEqualizer
A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter
提出一种高效能接收器，采用双反馈嵌套环CDR技术，提升高频抖动容限。
103 fJ/b/dB at 26 Gb/s
JSSC 2023第10期Data ConvertersSAR ADCTDC
A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain
一种采用环形TDC精细量化器的12位260MS/s流水线-SAR ADC，具有自动电压时间域对齐功能。
22nm CMOS, 0.8V, 260MS/s, 60.5dB SNDR, 77dB SFDR, 0.97mW
JSSC 2023第10期Data ConvertersSAR ADC
A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive V oltage TimeV
提出一种12位有效精度、二阶噪声整形SAR ADC，采用PVT不敏感的电压-时间-电压转换器。
1V电源电压, 10MS/s采样率, 73.8dB SNDR, 71.4µW功耗
JSSC 2023第10期Data ConvertersSAR ADC
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively
一款采用自适应偏置浮动逆变放大器（AB-FIA）和混合参考纹波抑制技术（H-RRM）的14位500MS/s单通道流水线-SAR ADC。
28nm CMOS, 6.34mW总功耗, 500MS/s, 0.018mm²面积
JSSC 2023第10期Image Sensors
A 1984-Pixels, 1.26 nW/Pixel Retinal Prosthesis Chip With Time-Domain In-Pixel Image Processing and Bipolar Stimulating Electrode Sharing Dong-Hwi Choi
一款1984像素视网膜假体芯片，采用时域像素内图像处理技术，显著降低功耗。
180 nm CMOS, 1.26 nW/pixel
JSSC 2023第10期MemoryEmerging MemoryNeural Network Accelerator
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference Wang Ye , Linfang Wang , Zhidao Zhou, Junjie An, Weizeng Li, Hanghang Gao, Zhi Li
28nm工艺的2T1R RRAM存内计算宏单元，提升边缘智能设备能效。
28nm HKMG, 1-bit IN/3-bit W/4-bit O, 30.34–154.04 TOPS/W
JSSC 2023第10期Data ConvertersSAR ADC
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward
一种校准自由的双通道时间交织噪声整形SAR ADC，采用二阶误差前馈技术，实现高分辨率和带宽。
28 nm CMOS, 1 V supply, 330 MHz operating frequency, 73.2 dB SNDR over 30 MHz bandwidth, 3.07 mW power consumption
JSSC 2023第10期RF & Wireless
A 37–43.5-GHz Phase and Amplitude Detection Circuit With 0.049 ◦ and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD
一种用于5G相控阵校准的高精度相位和幅度检测电路，采用39 GHz–150 kHz下变频方案。
65nm CMOS, 1V, 50mW, 1.43mm², 37-43.5GHz, <0.049°和0.036-dB RMS误差
JSSC 2023第10期OtherNeural Network Accelerator
A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os
提出一种新型电荷回收逻辑，用于单通道和多通道IO，显著降低功耗。
40nm CMOS, 2.56 Gb/s (TSV), 5.12 Gb/s (T-Line), 32.2%-47% 能效提升
JSSC 2023第10期Clocking & PLLsVCO
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique Yaqian Sun
提出一种紧凑低相位噪声的19GHz方形几何四核Class-F VCO，采用电感共享技术。
17.6-19.4GHz, -137.2dBc/Hz@10MHz, 46mW, 0.9V, FoM 186.1dBc/Hz
JSSC 2023第10期Other
A Hybrid Magnetic Current Sensor With a Multiplexed Ripple-Reduction Loop
一种混合磁电流传感器，结合霍尔板和线圈实现宽频带电流测量，并采用多路复用纹波抑制环路降低偏移。
0.18µm CMOS, 1.8V, 7.8mA, 4.6mm², 5MHz BW, ±2%增益变化, 1.6fW/Hz FoM
JSSC 2023第10期Image Sensors
A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using
提出一种0.56/0.8V多模视觉传感器，支持时序对比计算与局部二值模式特征提取
0.18µm CMOS, 0.56/0.8V, 540/819/540帧率
JSSC 2023第10期Data ConvertersDelta-Sigma ADC
A Multistep Multistage Fifth-Order Incremental Delta Sigma Analog-to-Digital Converter for Sensor Interfaces Jia-Sheng Huang , Shih-Che Kuo
提出一种多级多步第五阶增量型ΔΣ模数转换器，实现高精度低延迟的传感器信号转换。
180nm CMOS, 1.8V, 20kHz带宽, 358.4µW功耗, 91dB DR, 89.1dB SNDR, 107.5dB SFDR
JSSC 2023第10期Analog Circuits
A Process-Scalable Ultra-Low-V oltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less
提出一种采用时间域放大器的超低电压睡眠定时器，实现高精度温度校准和低功耗。
65nm CMOS, 0.4V, 63nW, 180kHz, 2.73ppm/°C
JSSC 2023第10期Clocking & PLLsNeural Network Accelerator
A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking Ahmad Sharkia , Student Member , IEEE
提出一种基于锯齿波调制器的低噪声分数频率合成技术。
65nm CMOS, 5GHz输入, 2.4899GHz输出, DJ PP降低≥7.2×
JSSC 2023第10期RF & Wireless
A Wide-Bandwidth Ultrasound Receiver and On-Chip Ultrasound Transmitter for Ultrasound
本文提出了一种用于超声胶囊内窥镜系统的宽带超声接收器和片上高压发射器，具有高能效和低功耗特性。
RX功耗2.3 mW，采用0.18 µm BCD工艺
JSSC 2023第10期Power ManagementLDO
A Wide-Load-Range and High-Slew Capacitor-Less NMOS LDO With Adaptive-Gain Nested Miller Compensation and Pre-Emphasis
提出一种宽负载范围、高转换速率的无电容NMOS LDO，采用自适应增益嵌套米勒补偿和预加重反向偏置技术。
180nm CMOS, 0.1-300mA负载范围, 17.5MHz带宽, 1.72ps FoM
JSSC 2023第10期Digital CircuitsNeural Network Accelerator
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET
提出一种基于存内计算和高斯随机数生成器的能效贝叶斯神经网络加速器。
32.2 TOP/sW峰值能效, 7.31 GSamp/s随机数生成吞吐量, 1170 GOP/s/W系统能效
JSSC 2023第10期Data Converters
An RC Delay-Based Pressure-Sensing System With Energy-Efficient Bit-Level Oversampling Techniques for Implantable IOP
提出一种基于RC延迟比较的压力传感系统，用于植入式眼压监测，具有高能效和分辨率。
0.24-mmHg分辨率，8.58-nJ·mmHg² FOM，12.79-µW功耗，11.52-ms转换时间
JSSC 2023第10期Other
C3MLS: An Ultra-Wide-Range Energy-Efficient Level Shifter With CCLS/CMLS
提出一种CCLS/CMLS混合电平转换器C3MLS，实现超宽范围高效能电平转换。
55nm CMOS, 0.3V-1.2V, 20.08ns延迟, 18.11fJ/转换, 0.12nW静态功耗
JSSC 2023第10期Other
Guest Editorial Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC)
2022年亚洲固态电路会议（A-SSCC）精选论文特辑介绍，涵盖模拟、电源、生物医学、射频电路及机器学习SoC等领域。
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JSSC 2023第10期Other
Laser V oltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design
提出一种基于标准单元的光传感器结构，用于检测数字电路中的激光电压探测攻击。
28nm CMOS, 220nm激光点检测, 150%面积开销（最坏情况）
JSSC 2023第10期Data ConvertersCIM
Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital–Analog Networks
提出了一种高效能神经形态内存计算处理器，支持脉冲神经网络，显著降低功耗和面积。
28nm CMOS, 2.9mm² die area, 0.72µJ/classification, 92.1% accuracy (CIFAR-10)
JSSC 2023第10期Digital CircuitsNeural Network Accelerator
SNPU: An Energy-Efficient Spike Domain Deep- Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit
提出一种高效能脉冲域深度神经网络处理器SNPU，采用两步编码和全稀疏处理单元提升能效。
输入脉冲编码功耗降低99.4%，操作减少43.5%与71.8%
JSSC 2023第10期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE固态电路期刊的出版信息及编委会成员介绍
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JSSC 2023第11期Data ConvertersVCO
A 0.004-mm 2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS Chenghao Zhang , Jiangbo Wei
基于门控环形振荡器的7位2GS/s时间域ADC，具有高能效和小面积。
28nm CMOS, 0.004mm², 2GS/s, 38.63dB SNDR, 50.66dB SFDR, 31.4fJ/conversion-step FoM
JSSC 2023第11期Power ManagementLDONeural Network Accelerator
A 0.45 mV/V Line Regulation, 0.6 V Output V oltage, Reference-Integrated, Error Amplifier-Less LDO With a 5-Transistor
提出一种0.7V输入、0.6V输出的双环路无误差放大器LDO，具有优异的线性和负载调节性能。
0.18µm CMOS, 0.7V输入, 0.6V输出, 0.45mV/V线性调整率, 0.35mV/mA负载调整率
JSSC 2023第11期Digital Circuits
A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification Tzu-Hsiang Hsu
提出一种0.8V智能视觉传感器，集成微型CNN和可编程传感器内处理电路，用于低功耗边缘设备实时推理。
0.8V, 128×128分辨率, 33.8pJ/pixel·frame, 93.6%准确率
JSSC 2023第11期Other
A 113.3-dB Dynamic Range 600 Frames/s SPAD X-Ray Detector With Seamless Global Shutter and Time-Encoded
一款具有1133dB动态范围和600帧无缝全局快门的SPAD X射线探测器
400 × 200像素阵列，49.5 µm像素间距，113.3 dB动态范围，127.2 mW功耗
JSSC 2023第11期Power ManagementBuck ConverterNeural Network Accelerator
A 12-to-1 Flying Capacitor Cross-Connected Buck Converter With Inserted D > 0.5 Control for Fast Transient Response Tingxu Hu, Student Member , IEEE
提出一种12:1飞电容交叉连接降压转换器，采用D>0.5控制实现快速瞬态响应。
12V输入/1.2V输出, 2MHz开关频率, 86.8%峰值效率, 110mV下冲(4A负载阶跃)
JSSC 2023第11期RF & WirelessNeural Network Accelerator
A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links Jaeyoung Seo , Sooeun Lee
一种20Gb/s/pin的单端DECS收发器，无需CDR或CDA电路，具有高时序容忍度和抗电源噪声能力。
20Gb/s/pin, 0.0024-mm², 0.18 pJ/b, 0.99 UI水平眼图
JSSC 2023第11期Other
A 47-nW V oice Activity Detector (V AD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-V olatile CAP-ROM
一款基于短时CNN和RNN的低功耗语音活动检测器，采用非易失性电容ROM存储权重。
65nm CMOS, 47nW, 0.022mm², 94%/91% hit rate
JSSC 2023第11期Other
A 65-nm CMOS Fluorescence Sensor for Dynamic Monitoring of
65纳米CMOS荧光传感器用于活细胞动态监测
65nm CMOS, 1.05fA最小检测电流, SNR>18dB
JSSC 2023第11期RF & WirelessNeural Network AcceleratorRadar
A 76–81 GHz 2 × 8 MIMO Radar Transceiver With Broadband Fast Chirp Generation and 16-Antenna-in-Package
一款76-81 GHz毫米波雷达收发器，采用2×8 MIMO天线封装，适用于汽车雷达应用。
65nm CMOS, 7.2 GHz调制带宽, 312 MHz/µs最大啁啾速率, 0.018%最佳线性度误差, 38.5米检测范围
JSSC 2023第11期Power Management
A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications
提出一种改进型KY转换器，通过连续飞电容充电电流提升效率至95%，适用于物联网应用。
95% peak efficiency, wide load range
JSSC 2023第11期RF & WirelessVCOHigh-Speed Link
A Highly Efficient 165-GHz 4FSK 17-Gb/s Transceiver System With Frequency Overlapping Architecture in 65-nm CMOS
一款高效165GHz 4FSK 17Gb/s收发器系统，采用频率重叠架构。
17Gb/s@18cm, 10.7pJ/bit, TX:62mW, RX:120mW
JSSC 2023第11期Image Sensors
A Low-Stimulus-Scattering Pixel-Sharing Sub-Retinal Prosthesis SoC With Time-Based Photodiode Sensing and Per-Pixel Dynamic V oltage Scaling
提出一种低刺激散射的像素共享亚视网膜假体SoC，采用模块化主动/返回电极方案和时间基光电二极管传感技术。
505通道，0.01mm²/像素，动态范围35.8dB，能耗降低64%
JSSC 2023第11期OtherDAC
A Polar-Modulation-Based Cryogenic Transmon Qubit State Controller in 28 nm Bulk CMOS for Superconducting
一种基于极性调制的28纳米体CMOS低温超导量子比特控制器
28nm CMOS, 3.5K工作温度, 1 GS/s XY路径驱动器SFDR 40 dB, Z路径驱动器SFDR 48 dB, 每量子比特功耗13.7 mW
JSSC 2023第11期Clocking & PLLs
A Three-Wafer-Stacked Hybrid 15-MPixel CIS + 1-MPixel EVS With 4.6-GEvent/s Readout, In-Pixel TDC, and On-Chip ISP and ESP Function
提出了一种三片堆叠的混合图像传感器，结合了1500万像素CIS和100万像素EVS，实现了高事件读取率。
EVS像素噪声率<1Hz, 对比度非均匀性3%, 事件读取速率4.6 GEvents/s
JSSC 2023第11期RF & Wireless
All Rivers Flow to the Sea: A High-Density Wireless Power Receiver With Split-Dual-Path and Hybrid-Quad-Path Step-Down
提出一种高密度无线功率接收器，采用分路双路径和混合四路径整流转换技术，实现高输出电流。
8.8-W最大输出功率，无线和有线充电峰值效率分别为85.2%和91%
JSSC 2023第11期OtherEnergy HarvestingNeural Interface
An 8-Shaped Antenna-Based Battery-Free Neural-Recording System Featuring 3 cm Reading Range and 140 pJ/bit Energy Efficiency Yunshan Zhang , Student Member , IEEE, Changgui Yang , Student Member , IEEE
基于8字形天线的无电池神经记录系统，实现3厘米无线通信范围。
65nm CMOS, 3cm通信范围, 140 pJ/bit能效
JSSC 2023第11期Data ConvertersDAC
An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC
一种用于移动OLED显示屏的超紧凑10位源驱动IC，采用LSB堆叠LV-to-HV放大DAC技术。
130nm CMOS, 1.5/5V, DNL -0.39/INL 0.9 LSB, 1-LSB 4.1mV, DVO 4.82mV
JSSC 2023第11期Other
An EMG Interface Comprising a Flexible a-IGZO Active Electrode Matrix and a 65-nm CMOS IC Enrico Genco, Student Member , IEEE, Carmine Garripoli , Jan-Laurens P. J. van der Steen, Gerwin H. Gelinck , Sahel Abdinia
提出一种基于柔性a-IGZO薄膜晶体管技术的4×4主动电极矩阵，用于监测肌肉收缩。
65nm CMOS, 1.2V, 20-dB in-band gain, 23-dB dc rejection
JSSC 2023第11期Wireline I/O
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s Ji-Young Kim
提出一种低功耗TSV I/O设计，用于HBM，数据速率达10Gb/s。
65nm CMOS, 0.179–0.185 pJ/b/pF, 5–10 Gb/s
JSSC 2023第11期Power ManagementProcessor/CPU
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DCDC V oltage R
提出一种集成误差恢复RISC-V核心和嵌入式DC-DC开关电容电压调节器的高能效微处理器。
28nm CMOS, 43 MHz, 0.57 pJ·µs
JSSC 2023第11期Other
An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing
一款用于384通道神经信号处理的在线尖峰排序IC，采用无监督几何感知OSort聚类技术，实现高精度和低功耗。
22nm FDSOI CMOS, 0.0013 mm²/通道, 1.78 µW/通道, 33.9 µs延迟, 97.7%准确率
JSSC 2023第11期mm-Wavemm-Wave PA
Deep-Learning-Based Inverse-Designed Millimeter-Wave Passives and Power
基于深度学习的毫米波无源器件和功率放大器逆向设计方法
无具体性能指标
JSSC 2023第11期Digital Circuits
Design and Characterization of a <4-mW/Qubit 28-nm Cryo-CMOS Integrated Circuit for Full Control of a Superconducting Quantum Processor
设计并表征了一款用于量子计算的28纳米低温CMOS集成电路，实现低功耗高精度量子控制。
28nm CMOS, 4 mW/qubit, 单量子位XY和Z平均门错误率0.17%-0.36%和0.14%-0.17%, 两量子位平均交叉熵基准循环错误率1.2%
JSSC 2023第11期Other
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)
2023年IEEE ISSCC会议精选论文特辑，聚焦固态电路设计创新。
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JSSC 2023第11期RF & WirelessPower Amplifier
H-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized Gmax-Core and Transmission Line-Based Zero-Degree Power Combining Networks Byeonghun Yun , Dae-Woong Park , and Sang-Gug Lee
65nm CMOS工艺下采用输出功率最大化Gmax核心的H波段高效功率放大器设计
245GHz时Psat 9.2dBm, OP1dB 6dBm, PAE 4.6%, 增益28dB
JSSC 2023第11期Other
New Associate Editor I
Fabio Sebastiano教授成为IEEE JSSC期刊的新副编辑，专注于低温电路、模拟和混合信号电路及传感器接口。
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JSSC 2023第11期Other
Subtractive Photonics in Bulk CMOS
提出在体CMOS工艺中通过减色法实现光子波导的新方法。
1550nm多模波导损耗4.1dB/cm
JSSC 2023第11期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，提供固态电路领域的最新研究成果。
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JSSC 2023第12期Data ConvertersSAR ADC
A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference
提出一种基于环形放大器的低功耗12位1GS/s混合架构ADC。
28nm CMOS, 62.5dB SNDR, 10.6mW, 169.2dB FoM S
JSSC 2023第12期Power ManagementBuck Converter
A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors
提出一种12至1V四输出开关电容降压转换器，采用共享直流电容器技术，实现高效率和小体积。
峰值效率90.4%，功率密度48 mA/mm³，效率85%
JSSC 2023第12期Data ConvertersDACNeural Network Accelerator
A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D
一种采用斩波电容反馈网络和电容DAC的数字输入D类音频放大器，实现120.9 dB动态范围。
180nm BCD, 120.9 dB DR, -111.2 dB THD+N, 15/26W@8/4Ω, 90%/86%效率
JSSC 2023第12期RF & WirelessPLLLNA
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET
一款集成PLL和ADC的D波段接收器，实现128Gb/s数据速率和1.95pJ/b能效。
22nm FinFET CMOS, 128Gb/s, 16-QAM, -15.2dB EVM, 246mW, 1.95pJ/b
JSSC 2023第12期Data ConvertersSAR ADCDAC
A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC
一款采用时间交织技术的28GS/s SAR ADC，通过时间域量化实现高能效转换。
28-GS/s采样率，51.79-dB SNDR，72.36-dB SFDR，18mW功耗
JSSC 2023第12期OtherVCO
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature
本文设计了一种紧凑的CMOS RC频率参考，采用温度补偿技术实现低温度系数。
180nm CMOS, 10MHz, ±2800 ppm (-45°C to 125°C)
JSSC 2023第12期RF & WirelessClock GenerationTransceiver
A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28-nm Process Wan Kim , Hyun-Gi Seok , Geunhaeng Lee , Sinyoung Kim, Jae-Keun Lee, Chanho Kim, Wonkang Kim, Wonjun Jung, Youngsea Cho, Seungyong Bae, Jongpil Cho, Hyuokju Na, Byoungjoong Kang, Honggul Han, Hyeonuk Son
本文介绍了一种符合IEEE 802.15.4/4z标准的全集成超宽带SoC，具备精确定位和安全通信功能。
28nm CMOS, 6.81 Mbps BPRF, 接收灵敏度-96.1 dBm, 发射峰值功率14.25 dBm
JSSC 2023第12期RF & Wireless
A Highly Integrated Distributed Mixer Receiver for Low-Power
一种新型分布式N-path混频器架构的低功耗无线接收机，实现亚150µW功耗和高性能。
22nm CMOS, 0.48mm², 0.4-0.9GHz, -85dBm灵敏度, -41dB SIR容忍度
JSSC 2023第12期Other
A Hybrid Magnetic Current Sensor With a Dual Differential DC
提出一种混合磁电流传感器，结合拾取线圈和霍尔板实现宽频带接触式电流测量。
0.18µm CMOS, 1.8V, 7.1mA, 43mA分辨率@5MHz带宽
JSSC 2023第12期RF & Wireless
A Low-Power 256-Element K a-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small
一款低功耗256单元Ka波段CMOS相控阵接收器，适用于LEO小卫星通信系统。
2.95 mW/单元, -20dBm IIP3, 3.6dB噪声系数, 0.24mm²/单元
JSSC 2023第12期Clocking & PLLsPLL
A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering Simone M. Dartizio , Member , IEEE
提出一种基于逆常数斜率DTC的低杂散低抖动分数N数字PLL。
28nm CMOS, 0.33 mm2, 17.2 mW, -70 dBc, 77 fs
JSSC 2023第12期Other
A Modular Switched-Capacitor Chip-Stacking Drive Platform for kV-Level
提出一种基于多芯片堆叠的开关电容驱动器，实现千伏级电压输出，效率高达97%。
180nm SOI CMOS, 3.7V输入, 400Vpp输出, 3kVpp输出, 97%效率
JSSC 2023第12期Data ConvertersSAR ADCNeural Network Accelerator
A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting
提出一种带集成输入缓冲器的两步式SAR ADC，采用预测电平移位技术实现轨到轨信号摆幅，性能优异。
12 MS/s, 91.3 dB SNDR, 94.1 dB DR, 6.6 Vpp差分摆幅, 4 MHz输入频率, 30.41 mW功耗
JSSC 2023第12期Power ManagementBuck ConverterNeural Network Accelerator
A Reconfigurable Single-Inductor Multi-Stage Hybrid Converter for 1-Cell
一种可重构单电感多级混合转换器，用于1节电池充电，支持5-24V宽输入电压范围。
最大输出电流5A，峰值效率94.8%（5V输入）和92.4%（24V输入）
JSSC 2023第12期Power ManagementEnergy Harvesting
A Scalable N-Step Equally Split SSHI Rectifier for Piezoelectric Energy Harvesting With Low-Q Inductor Yeon-Woo Jeong
提出一种可扩展的N步均分SSHI整流器，用于压电能量收集，显著提升功率提取效率。
功率提取效率提升1170%（相比全桥整流器）
JSSC 2023第12期Data ConvertersSAR ADC
A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain E
一种采用量化预测展开增益误差整形技术的二阶噪声整形流水线SAR ADC
28nm CMOS, 1V, 400MS/s, 25MHz带宽, 77.2dB SNDR, 2.03mW
JSSC 2023第12期Data Converters
A Sub-1 V Capacitively Biased BJT-Based Temperature Sensor With an Inaccuracy of ±0.15 ◦C (3σ ) From −55 ◦C to 125 ◦C
提出一种低于1V的BJT温度传感器，采用电容偏置技术，实现高精度和高效能。
0.18-µm CMOS, 0.95V, 810nW, ±0.15°C inaccuracy, 0.34pJ·K² FoM
JSSC 2023第12期Clocking & PLLs
A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From −40 ◦C to 85 ◦C After Accelerated Aging for 500 h at 125 ◦C
一种温度和老化补偿的RC振荡器，通过周期性锁定主振荡器频率到参考振荡器，实现长期稳定性。
65nm CMOS, 100MHz, 5.1ps rms抖动, 1.4µW/MHz
JSSC 2023第12期Analog Circuits
A Third-Order Quasi-Elliptic N-Path Filter With Enhanced Linearity Through
提出一种新型三阶准椭圆N路径滤波器，通过时钟增强线性度，实现高频操作与高功率处理能力。
1-5 GHz工作范围，+8.8 dBm带内P1dB，+23 dBm带内IIP3，+36 dBm带外IIP3
JSSC 2023第12期Power ManagementBoost Converter
A Three-Level Boost Converter With Fully State-Based Phase Selection Technique for High-Speed VCF Calibration and Smooth Mode Transition Seung-Ju Lee
提出一种采用全状态相位选择技术的三级电流模式升压转换器，优化飞跨电容电压校准和模式切换。
0.18-µm BCD工艺, 5.51 mm², 峰值效率95.3%, 输入2-6V, 输出5-32V, 最大负载电流0.5A
JSSC 2023第12期RF & WirelessPower Amplifier
A Transformer-Based Quadrature Doherty Digital Power Amplifier With 4.1 W Peak Power in 28 nm Bulk CMOS
采用8路串联变压器和IQ重用技术的Doherty数字功率放大器，实现高输出功率和高效率。
28 nm CMOS, 1.1/2.2 V, 4.1 W (36.1 dBm) peak output power, >30% peak PAE, 2.7–3.2 GHz
JSSC 2023第12期RF & WirelessPLLDRAM
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution
一种基于单LC-VCO的5G FR1宽带LO生成器，采用子采样架构和数字校准技术实现低相位噪声。
65nm CMOS, 超低抖动, 覆盖5G FR1全频段
JSSC 2023第12期Other
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)
2023年IEEE ISSCC会议精选论文特辑，涵盖RF、无线、模拟、电源管理和数据转换器电路。
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JSSC 2023第12期RF & Wireless
Harmonic-Resilient Fully Passive Mixer-First Receiver for Software-Defined Radios
一款用于5G新无线电应用的低损耗全被动谐波抑制混频器优先接收器
噪声系数3.5–5.5 dB, 带外输入三阶截点13–27 dBm, H3/H5阻塞器1dB压缩点10/4 dBm
JSSC 2023第12期Other
On-Chip Condition-Adaptive 1 f 3 EMI Control for Switching Power ICs Lixiong Du , Student Member , IEEE
本文提出了一种自适应1 f 3 EMI控制技术，用于汽车电源电路，有效应对输入电压和负载电流的剧烈变化。
180-nm HV BCD工艺，EMI减少17.2 dB，fSW扩展10%至32%
JSSC 2023第12期Clocking & PLLs
Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance
提出一种可扩展的多核振荡器，通过抵消共模谐振降低相位噪声，适用于毫米波频段。
28GHz, 193.3dBc/Hz FoM@1MHz(四核), 192.7dBc/Hz FoM@1MHz(20核)
JSSC 2023第12期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，提供固态电路领域的最新研究和技术进展。
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