JSSC 年份

2014

290 篇期刊论文

JSSC 2014第1期Other
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 C Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takay uki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Y oshiyuki Kawashima
40纳米嵌入式分栅MONOS闪存宏单元，支持160MHz高速读取，适用于汽车微控制器。
160MHz随机读取操作，170°C下超过1000万次编程/擦除耐久性
JSSC 2014第1期Power Management
A0 . 5V 4 W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor Mohammad Alhawari, Nadya A. Albelooshi, and Michael H. Perrott , Senior Member , IEEE
基于非均匀量化器的0.5V CMOS光数字转换器，实现高灵敏度和低功耗
0.5V CMOS, 4 W功耗, 30 dB SNR, 0.45%瞬时周期抖动
JSSC 2014第1期Image SensorsCMOS Image Sensor
A3 . 4 - W Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging Jaehyuk Choi, Seokjun Park, Jihyun Cho, and Euisik Y oon
一种低功耗对象自适应CMOS图像传感器，通过嵌入式特征提取算法显著降低功耗。
0.22 W/frame（运动传感模式）, 3.4 W/frame（特征提取模式）, 94.5%检测率
JSSC 2014第1期Digital Circuits
A 0.15-mm-Thick Noncontact Connector for MIPI Using a V ertical Directional Coupler Atsutake Kosuge, Student Member , IEEE, Wataru Mizuhara , Student Member , IEEE, Tsunaaki Shidei, Tsutomu Takeya, Student Member , IEEE
开发了一种用于MIPI应用的0.15毫米厚非接触连接器，采用垂直定向耦合器实现双链路通信。
2.3 Gb/s/link, 1.47 pJ/b, 320 ps (64% U.I.)单链路, 305 ps (61% U.I.)双链路
JSSC 2014第1期Image Sensors
A 0.18- m CMOS SoC for a 100-m-Range 10-Frame/s 200 96-Pixel Time-of-Flight
一款用于100米范围、10帧/秒、200×96像素飞行时间深度测量的CMOS SoC芯片
100米测距范围，10帧/秒，202×96像素分辨率，70klux光照下14.2cm重复性误差
JSSC 2014第1期Other
A 1024 8, 700-ps Time-Gated SPAD Line Sensor for Planetary Surface Exploration With Laser Raman Spectroscopy and LIBS Y
介绍了一种用于行星表面探索的1024×8时间门控SPAD线传感器，具有高光子检测效率和快速门控能力。
最大光子检测效率19.3%，暗计数率5.7 kHz@3V，时间分辨率250ps，最小门宽0.7ns
JSSC 2014第1期Memory
A 130.7-mm 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology
24纳米工艺下开发的32Gb ReRAM测试芯片，采用交叉点架构和二极管选择器件。
24-nm, 32-Gb, 1307-mm²
JSSC 2014第1期MemorySRAM
A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications Mehul Tikekar, Student Member , IEEE
一款支持4K超高清的HEVC视频解码芯片，优化架构降低存储需求
40nm CMOS, 200MHz, 1.19nJ/pixel, 4K Ultra HD 30-fps
JSSC 2014第1期MemorySRAM
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable
提出双电源SRAM的电路技术，显著降低活动与待机模式功耗
28nm CMOS, 活动模式功耗降低27%, 待机模式功耗降低85%
JSSC 2014第1期Memory
A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13- m CMOS for Nonvolatile Processing in
一种基于FeRAM的非易失性D触发器设计，用于断电不丢失数据的数字系统。
3.4 pJ每NVDFF的往返保存-恢复能量
JSSC 2014第1期Memory
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm Jason M. Hart , Member , IEEE, Hoyeol Cho, Y uefei Ge, Gr egory Gruber
Oracle推出28nm工艺的16核SPARC T5处理器，性能提升显著。
28nm CMOS, 3.6GHz, 1.5 billion transistors, 5.65 TB/sec bandwidth
JSSC 2014第1期RF & WirelessDRAM
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory
一款用于双列直插内存模块的6.4Gb/s近地单端收发器，采用低功耗信号传输技术。
6.4Gb/s, 3.5英寸FR4 PCB传输, 9.1pJ/bit能效
JSSC 2014第1期Clocking & PLLsPLLVCO
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration
一种采用双环双VCO架构的低抖动、低功耗、小面积全数字注入锁定PLL。
65nm CMOS, 1.2GHz, 0.7ps RMS jitter, 1.6mW/0.97mW功耗, 0.022mm²面积
JSSC 2014第1期Other
A Fully Differential Charge-Balanced Accelerometer for Electronic Stability Control Vladimir P . Petkov, Member , IEEE, Ganesh K. Balachandran , Member , IEEE, and
一种用于电子稳定控制的全差分电荷平衡加速度计，具有抗电磁干扰和高动态范围特性。
380噪声基底，84-dB动态范围，40至140°C温度范围内偏移变化11 mg
JSSC 2014第1期Clocking & PLLs
A Fully Digital 8 16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output L e oH .C .B r a g a, Student Member , IEEE
一种用于PET应用的全数字8x16 SiPM阵列，具有每像素TDC和实时处理能力。
570x610μm像素尺寸, 35.7%填充因子, 100Msamples/s, 10.9%能量分辨率, 399ps符合时间分辨率
JSSC 2014第1期Data ConvertersSAR ADCBiosignal
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic
一款8通道闭环神经假体SoC，用于实时颅内脑电采集、癫痫检测和电刺激抑制。
8通道, 10位ADC, 实时处理
JSSC 2014第1期Digital CircuitsPower Amplifier
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS Paul N. Whatmough , Member , IEEE
一篇关于1GHz Razor FIR加速器的低功耗设计，采用时间借用跟踪算法和插值纠错技术。
65nm CMOS, 1 GS/s, 37%能效提升
JSSC 2014第1期Clocking & PLLs
A V ersatile Timing Microsystem Based on Wafer-Level Packaged XTAL/BAW Resonators With Sub- W RTC Mode and Programmable HF Clocks David Ruffieux, Nicola Scolari, Frédéric Giroud, Thanh-Chau Le, Silvio Dalla Piazza, Felix Staub, Kai Zoschke, Charles-Alix Manier, Hermann Oppermann, To mmi Suni, James Dekker, and
提出基于晶圆级封装XTALBAW谐振器的微型计时系统，实现高集成度与小尺寸
0.4W功耗/2ppm稳定性（-40℃~85℃）/1.5×1.1×0.7mm³尺寸
JSSC 2014第1期Digital Circuits
An 8-Core MIPS-Compatible Processor in 32/28 nm Bulk CMOS
介绍32/28纳米工艺的8核MIPS兼容处理器Godson-3B1500，具有高性能和低功耗特点。
1.0 GHz至1.5 GHz频率，1.0 V至1.3 V电压，150GFLOPS@1.2 GHz性能，<40 W功耗
JSSC 2014第1期Other
An 87-mA Iontophoresis Controller IC With Dual-Mode Impedance Sensor for Patch-Type Transdermal Drug Delivery System Kiseok Song, Student Member , IEEE, Unsoo Ha , Student Member , IEEE, Jaehyuk Lee , Student Member , IEEE
一款集成双模阻抗传感器的87mA离子电渗控制器IC，用于可穿戴药物递送。
0.11μm CMOS, 2.35mm×2.35mm, 2.2mW峰值功耗, 16-512μA可编程电流, DC-500Hz频率范围
JSSC 2014第1期OtherProcessor/CPU
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at 0VA c h i e v i n gZ e r oL e a k a g eW i t h 400-ns Wakeup Time for ULP Applications
一款基于FRAM的非易失性逻辑MCU SoC，支持100次数字状态保留，睡眠模式下零泄漏。
130nm低泄漏工艺, 1.5V电源, 400ns恢复时间
JSSC 2014第1期Medical & Bio
An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe Carolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuyse n
提出一种包含455个活动电极和52个同步读出通道的CMOS神经探针，用于大规模神经活动记录。
输入参考噪声3.2μV，NEF 3.08，核心电路功耗949.8μW，总功耗1.45mW
JSSC 2014第1期Other
An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing
提出一种时域模拟与数字混合信号处理的LDPC解码器，结合模拟计算的高效性和数字计算的灵活性。
65 nm CMOS, 10.4 pJ/bit, 6.1 Gbps/mm²
JSSC 2014第1期MemorySRAM
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Ampli fiers for Up to 1.9 Lower Energy/Access
针对高相关性数据的应用，提出一种基于预测的SRAM设计以减少位线切换活动。
1.9倍能量/访问降低
JSSC 2014第1期MemoryProcessor/CPU
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module
描述IBM EC12系统中处理器芯片和缓存芯片的电路与物理设计实现
5.5 GHz, 192 MB eDRAM
JSSC 2014第1期Other
Digital Object Identi fier 10.1109/JSSC.2013.2296111
无摘要信息
无
JSSC 2014第1期Other
Digital Object Identi fier 10.1109/JSSC.2013.2296112
无摘要提供，无法生成概要。
无
JSSC 2014第1期Other
Hi g hl i gh t s o f th e I SSC C 2 0 13 P r o c e s s o r s a n d Hi g h Pe r f
2013年ISSCC会议处理器与高性能数字电路专题亮点
3.6 GHz 16核SPARC处理器
JSSC 2014第1期Digital Circuits
Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions I
2013年ISSCC会议精选论文，涵盖处理器与高性能数字电路的最新进展
5.5 GHz, 2.75 B晶体管, 6 CPU核心, 2 MB L2缓存, 48 MB eDRAM L3缓存, 192 MB eDRAM L4缓存
JSSC 2014第1期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路的分析、设计与性能研究，涵盖数字、模拟、微波及光电子集成电路。
无具体性能指标
JSSC 2014第1期Data Converters
The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Kinya Ishizaka, Ryuichi Nishiyama , Sota Sakabayashi, Y oichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Y oshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, and
第10代16核SPARC64处理器，采用28nm CMOS工艺，主频3.0GHz，适用于关键任务UNIX服务器。
28nm CMOS, 3.0GHz, 16核, 24MB共享L2缓存, 588mm²芯片面积
JSSC 2014第2期Data ConvertersDAC
A7 2d BD R ,C T ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW John G. Kauffman , Member , IEEE
提出一种采用数字估计辅助DAC线性化的2D BD RC T ΔΣ调制器
67.5 dB SNDR, 72 dB DR, 79 dB SFDR, 25 MHz带宽, 8.5mW功耗
JSSC 2014第2期Power Management
A 0.791 mm On-Chip Self-Aligned Comparator Controller for Boost DC-DC Converter Using Switching Noise Robust Charge-Pump Tae-Hwang Kong, Student Member , IEEE , Sung-Wan Hong , Student Member , IEEE ,a n d
提出一种新型自对准比较器控制PWM控制器，用于提升DC-DC转换器效率。
0.35μm BCDMOS, 3.7V/8V, 926kHz, 90%效率, 480mW输出功率
JSSC 2014第2期Analog CircuitsOp-Amp
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF
一款12mW低功耗连续时间带通ΔΣ调制器，采用新型高效谐振器，实现58dB SNDR和24MHz带宽。
65nm CMOS, 12mW, 58dB SNDR, 24MHz带宽, 800MS/s
JSSC 2014第2期Data ConvertersPipeline ADCOp-Amp
A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity Y uichi Miyahara, Mitsuhiro Sano, Kazuo Koya ma, Toshikazu Suzuki
通过自适应消除运放增益和非线性误差的14位60MS/s流水线ADC设计
14b INL, 91 dB SFDR, 60 MS/s, 1.6 V
JSSC 2014第2期RF & WirelessOptical I/O
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-V ariation-Tolerant Analog Front End and Data-Format Conversion
一款65nm CMOS工艺的光收发器，支持25-Gb/s数据传输，具有电源噪声抑制功能。
25-Gb/s数据传输速率，2.2W总功耗，-6.1-dBm OMA
JSSC 2014第2期Clocking & PLLs
A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Ef ficient Operation From Sub-Threshold to High Performance Kyle Craig, Y ousef Shakhsheer, Saad Arrabi, Sudhanshu Khanna
32位90纳米处理器实现全动态电压调节，显著提升能效。
32 b, 90 nm, 0.25 V–1.2 V, 80% energy savings
JSSC 2014第2期Clocking & PLLsVCOClock Generation
A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology
提出一种采用同相注入耦合QVCO的60 GHz频率合成器，降低相位噪声和误差。
65nm CMOS, 1.2V, 57.9-68.3GHz, 24.6mW, -89.8~-91.5dBc/Hz@1MHz
JSSC 2014第2期RF & WirelessEnergy HarvestingTransceiver
A 90-nm CMOS 5-Mbps Crystal-Less RF-Powered Transceiver for Wireless Sensor Network Nodes Giuseppe Papotto, F
一款90纳米CMOS无晶振射频供电收发器，支持5 Mbps数据传输
90nm CMOS, -17.1 dBm, 5 Mbps
JSSC 2014第2期Clocking & PLLs
A Low Phase Noise Oscillator Principled on Transformer-Coupled
通过硬限幅和波形恢复技术实现低相位噪声的8 GHz CMOS振荡器，适用于基站应用。
8 GHz, 65 nm CMOS, 32 mA @ 1.5 V, 相位噪声-147.7 dBc/Hz @ 1 MHz偏移
JSSC 2014第2期RF & WirelessNeural Interface
A Low Power Light Weight Wireless Multichannel Microsystem for Reliable
一款低功耗轻量级无线多通道微系统，用于可靠神经信号记录。
2.85×3.84mm², 5mW功耗, 4.58-7.81μV噪声, 3m-20m传输距离
JSSC 2014第2期Data Converters
Compressed Sensing Analog Front-End for Bio-Sensor Applications
一种用于生物传感器应用的压缩感知模拟前端，实现低功耗和高精度
0.13 µm CMOS, 2×3 mm², 28 nW/1.8 µW (1/64 channels), 2 kHz时钟
JSSC 2014第2期Wireline I/OEqualizer
Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer Ahmed Awny, Lothar Moeller, Joseph Junio, J.
设计并测量了用于80 Gb/s短距离光通信系统的1-tap决策反馈均衡器
80 Gb/s和110 Gb/s版本分别消耗4W和5.75W，面积分别为2 mm²和2.56 mm²
JSSC 2014第2期Power ManagementLDO
External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range
提出一种无外置电容的高电源抑制比LDO稳压器设计
0.18µm CMOS, 1.8V, 80µA静态电流, 56dB PSR@4MHz
JSSC 2014第2期Clocking & PLLsClock Generation
FEBRUARY 2014 VOLUME 49 NUMBER 2 IJSCBC ISSN 0018-9200 REGULAR PAPERS A 90 - n m
该期刊包含多篇关于高频合成器、低相位噪声振荡器和ΔΣ调制器的论文。
90-nm CMOS, 24.6 mW, 58 dB SNDR, 24 MHz带宽
JSSC 2014第2期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路的分析、设计与性能研究，涵盖数字、模拟、微波和光电子电路。
无
JSSC 2014第2期Clocking & PLLs
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold
提出间歇谐振时钟技术，可在任意时钟频率下降低功耗。
0.37V 32位加法器阵列，时钟功耗降低36%，泄漏功耗降低81%
JSSC 2014第2期Other
Large-Scale Sensing System Combining Large-Area Electronics and CMOS ICs for Structural-Health Monitoring Yingzhe Hu, Student Member , IEEE , Warren S. A. Rieutort-Louis ,S t u d e n tM e m b e r ,I E E E
结合大面积电子和CMOS IC的大规模传感系统，用于桥梁早期损伤检测。
灵敏度18 µStrain，读取能量270 nJ/测量，通信能量12.8 pJ/3.3 pJ每比特（Tx/Rx），距离7.5米
JSSC 2014第2期Clocking & PLLs
Mutual Pulling Between
研究两个相互耦合的振荡器在相位锁定或自由运行时的行为及其频率相互牵引现象。
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JSSC 2014第2期Power ManagementCharge Pump
Patent Abstracts The Patent Abstracts cited are intended to provide the minimum in- formation necessary for determining interest. The full text and images can be obtained from the U.S. Patent Of fice at http://www.uspto.gov 8,476,963 July 2, 2013 Exponential charge pump Inventors: Thomas D. Cook (Austin, TX), Jeffrey C. Cunningham (Austin, TX), and Karthik Ramanan (Austin, TX) Assignee: Freescale Semiconductor, Inc. (Austin, TX) Filed: January 4, 2011.
专利摘要提供了指数多级电荷泵和高速接收器架构的创新设计。
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JSSC 2014第2期Digital CircuitsNeural Network Accelerator
Positive-Feedback Level Shifter Logic for Large-Area Electronics Daniele Raiteri, Student Member , IEEE, Pieter van Lieshout, Arthur
提出正反馈电平转换器逻辑，用于有机或金属氧化物半导体的大面积电子器件设计，显著提高增益和噪声容限。
增益从13 dB（传统Zero-Vgs逆变器）提升至76 dB（PLS逆变器），噪声容限从2.58 V提升至6.82 V（20 V电源）
JSSC 2014第2期Clocking & PLLsVCO
Relation Between Delay Line Phase Noise and Ring Oscillator
通过开环相位噪声与整形函数相乘，推导出环形振荡器相位噪声的紧凑表达式。
65nm CMOS工艺验证
JSSC 2014第3期Data Converters
A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs Hyun-Sik Kim, Student Member , IEEE, Jun-Hyeok Y ang, Sang-Hui Park , Student Member , IEEE
提出一种用于主动矩阵LCD的10位列驱动IC，采用迭代电荷共享技术提高线性度和面积效率。
0.11µm CMOS, 188×15µm²/channel, 0.9µA/channel, DNL 0.25LSB, INL 0.43LSB
JSSC 2014第3期RF & Wireless
A 100–800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving 40 dBc for ALL Harmonics Saqib Subhan, Student Member , IEEE, Eric A. M. Klumperink , Senior Member , IEEE,A m i r G h a f f a r i
一款100-800 MHz 8路径多相发射机，通过混频器占空比控制实现全谐波抑制。
0.16μm CMOS, 100-800 MHz, 10.8 dBm输出功率, 8.7%效率
JSSC 2014第3期Data ConvertersDAC
A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique Wei-Te Lin, Student Member , IEEE, Hung-Yi Huang , Student Member , IEEE,a n d T a i - H a u rK u o, Member , IEEE
提出DEMDRZ技术，在40nm工艺下实现12位高速高分辨率DAC，性能优异。
40nm CMOS, 1.2V, 1.6/2.8GS/s, 70dB SFDR, -61dB IMD, 40mW, 0.016mm²
JSSC 2014第3期Data Converters
A 15-MHz Bandwidth 1-0 MASH ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR
首次采用数字线性化技术校准带记忆的积分器失真和电容失配误差的1-0MASH ΣΔ ADC。
1.25V, 240MHz采样时钟, 85-dBc SFDR, 67-dB SNDR, 37mW功耗
JSSC 2014第3期RF & Wireless
A 2.4-GHz CMOS Power Ampli fier With an Integrated Antenna Impedance Mismatch Correction System Y oungchang Y oon, Member , IEEE
提出一种集成天线阻抗失配校正的24GHz CMOS功率放大器，自动补偿阻抗失配。
0.18μm CMOS, 1-dB增益变化点, 功率附加效率接近匹配条件
JSSC 2014第3期Data Converters
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS Takumi Danjo, Masato Y oshioka, Masa yuki Isogai
65nm CMOS工艺下实现的6位1GS/s插值亚稳态ADC，功耗99mW
65nm CMOS, 1.1V, 1GS/s, 32.8dB SNDR, 9.9mW
JSSC 2014第3期RF & Wireless
A CMOS 210-GHz Fundamental Transceiver With OOK Modulation Zheng Wang, Student Member , IEEE , Pei-Y uan Chiang , Student Member , IEEE , Peyman Nazari, Student Member , IEEE
32nm SOI CMOS工艺下实现的210GHz OOK调制收发器
VCO输出功率13.5dBm, PA增益15dB, LNA增益18dB, EIRP 15.2dBm
JSSC 2014第3期Clocking & PLLsPLL
A CMOS Class-D Line Driver Employing a Phase-Locked Loop Based PWM Generator Jingxue Lu
一种采用PLL生成PWM的CMOS D类线路驱动器，实现高效低失真输出。
130nm CMOS, 4.8V, 1.2W@6.8Ω, THD -65dB@60kHz, 峰值效率83%@1W
JSSC 2014第3期Medical & Bio
A Complete 256-Electrode Retinal
一款完整的256电极视网膜假体芯片，具有高集成度和多种安全特性。
65nm CMOS, 150µm电极间距, 8mm²芯片面积, 70%能效
JSSC 2014第3期Other
A Feed-Forward Power-Supply Noise Cancellation Technique for Single-Ended Class-D Audio Amplifiers Adrian I. Colli-Menchi , Student Member , IEEE , Joselyn Torres , Student Member , IEEE ,a n d
提出一种前馈电源噪声消除技术，显著提升单端D类音频放大器的电源抑制比。
83 dB PSRR at 217 Hz, 0.0149% THD+N, 94.6% efficiency, 356 μW quiescent power
JSSC 2014第3期Clocking & PLLs
A Power-Scalable DCO for Multi-Standard GSM/WCDMA
一种功耗可调的DCO设计，通过互补开关对结构实现75%功耗降低且保持相位噪声性能不变
55nm CMOS, 4GHz, 129.3dBc/Hz@2MHz(P-N), 134.7dBc/Hz@2MHz(N-only), FoM 185dBc/Hz
JSSC 2014第3期RF & Wireless
A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery
一款自同步、自循环的超宽带脉冲无线电接收器SoC，用于低数据率通信，具有高能效。
65 nm LP CMOS, 375 pJ/bit, 79.5 dBm sensitivity
JSSC 2014第3期Power ManagementLDO
A Switchable Digital–Analog Low-Dropout Regulator for Analog Dynamic V oltage Scaling Technique Wei-Chung Chen, Student Member , IEEE, Su-Yi Ping, Tzu-Chi Huang, Y u-Huei Lee , Student Member , IEEE
一种可切换数字模拟低压差稳压器，用于模拟动态电压调节，提升系统效率。
40nm CMOS, 峰值效率96.7%, 输出纹波5mV@120mA, 轻载效率>92.57%@1μA
JSSC 2014第3期Clocking & PLLsVCO
An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators Marco Garampazzi, Student Member , IEEE, Stefano Dal Toso
提出一种直观且准确的相位噪声分析方法，用于比较各类振荡器的基本限制。
无具体指标
JSSC 2014第3期RF & WirelessEnergy Harvesting
Co-Design of a CMOS Recti fier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters Mark Stoopman, Student Member , IEEE , Shady Keyrouz , Student Member , IEEE
本文提出了一种CMOS整流器与小环天线的协同设计方法，以提高射频能量收集的灵敏度。
–27 dBm灵敏度，1 V输出，40%转换效率，27米范围
JSSC 2014第3期Other
Digital Object Identi fier 10.1109/JSSC.2014.2309275
无摘要提供，无法生成概要。
无
JSSC 2014第3期Other
Digital Object Identi fier 10.1109/JSSC.2014.2309513
无摘要，无法提供概要
无
JSSC 2014第3期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路的分析、设计与性能研究，涵盖数字、模拟、微波及光电子集成电路。
无具体指标
JSSC 2014第3期Clocking & PLLsVCOClock Generation
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator WooSeok Kim, Student Member , IEEE, Jaejin Park
本文提出了一种适用于视频像素时钟生成的双环ADPLL，通过双环架构有效抑制振荡器相位噪声。
28nm CMOS, 1.0V, 250MHz, 15ps rms抖动, 3.1mW功耗
JSSC 2014第3期MemoryDRAM
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM
采用非刷新嵌入式DRAM的低功耗高吞吐量LDPC解码器设计
9 Gb/s峰值吞吐量，89.5 pJ/b能效，37.7 mW功耗
JSSC 2014第3期RF & Wireless
MARCH 2014 VOLUME 49 NUMBER 3 IJSCBC ISSN 0018-9200 EDITORIAL Ne w A s s o c i a
IEEE JSSC 2014年3月刊收录了多篇关于高频CMOS电路设计的论文，涵盖收发器、UWB接收机、多相发射机等主题。
210 GHz, 2.4 GHz, 100–800 MHz
JSSC 2014第4期Clocking & PLLsSRAM
1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing
首款1 Mb非易失性TCAM，采用2T-2R单元，面积比SRAM TCAM小10倍以上。
1 Mb容量, 0.75V最低工作电压, 1.9ns匹配延迟
JSSC 2014第4期Digital Circuits
APRIL 2014 VOLUME 49 NUMBER 4 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE 2013 SYMPOSIUM ON VLSI CIRCUITS
2014年IEEE JSSC特刊聚焦低功耗医疗SoC、高性能处理器及自供电传感系统等前沿技术。
48.6-to-105.2 µW, 3 GHz, 1.59 Gpixel/s
JSSC 2014第4期Power ManagementNeural Network Accelerator
A 0.45–1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density M I MC a p a c i t o ri n2 2n mT r i - G a t eC M O S
22nm三栅CMOS工艺中实现的全集成分布式开关电容DC-DC转换器，具有高密度MIM电容和高效电源管理。
22nm CMOS, 1.225V输入, 0.45–1V输出, 63–84%转换效率, 0.88 A/mm²电流密度
JSSC 2014第4期Data Converters
A 10-Bit 800-MHz 19-mW CMOS ADC
一款采用电荷导向运放的10位800MHz 19mW CMOS ADC，通过非线性校准提升性能。
10-bit, 800MHz, 19mW, Nyquist SNDR 52.2dB
JSSC 2014第4期Clocking & PLLs
A 100 fps, Time-Correlated Single-Photon- Counting-Based Fluorescence-Lifetime Imager in 130 nm CMOS
一款基于130nm CMOS工艺的64x64 SPAD-TDC阵列，实现100 fps荧光寿命成像。
62.5 ps分辨率/64 ns量程/42 Gbps/100 fps
JSSC 2014第4期Memory
A 1.59 Gpixel/s Motion Estimation Processor With 211 to +211 Search Range for UHDTV
一款针对UHDTV的159 Gpixels/s运动估计处理器，支持211×211搜索范围，显著提升编码效率。
40nm CMOS, 210MHz, 622mW, 1.59 Gpixel/s
JSSC 2014第4期RF & WirelessPhased ArrayRadar
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS Brian P . Ginsburg, Member , IEEE, Srinath M. Ramaswamy , Member , IEEE, Vijay R entala, Member , IEEE
65nm CMOS工艺实现的160GHz脉冲雷达收发器，用于短程雷达应用。
65nm CMOS, 1.2/1.4V, 18.8dBm EIRP, 7GHz带宽
JSSC 2014第4期Clocking & PLLsDRAM
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Y u Hsu, Shu-Chun Y ang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang
通过CoWoS平台展示1Tbit/s带宽PHY，采用TSMC 40nm CMOS技术，实现低功耗和小面积eDRAM PHY。
1Tbit/s带宽, 0.3V, 1.1Gbit/s
JSSC 2014第4期Clocking & PLLsPLLVCO
A 28 GHz Hybrid PLL in 32 nm SOI CMOS Mark Ferriss, Alexander Rylyakov, José A. Tierno , Member , IEEE, Herschel Ainspan, and Daniel J. Friedman ,M e m b e r ,I E E E
介绍了一种28 GHz混合PLL，采用32 nm SOI CMOS工艺，结合模拟比例路径和数字积分路径设计。
28 GHz, 32 nm SOI CMOS, 31 mA @ 1 V, 199 fs RMS jitter (1 MHz to 1 GHz), -110 dBc/Hz @ 10 MHz offset
JSSC 2014第4期RF & Wireless
A 2 dB NF Receiver With 10 mA Battery Current Suitable for
一种适用于共存应用的2 dB NF接收器，电池电流仅为10 mA。
40 nm CMOS, 10 mA电池电流, 亚2 dB噪声系数
JSSC 2014第4期Digital Circuits
A 3 GHz Dual Core Processor ARM Cortex TM-A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide V oltage Range and Energy Efficiency Optimization David Jacquet, Frédéric Hasbani, Philippe Flatresse
28nm FD-SOI工艺下实现3GHz双核ARM Cortex-A9处理器，支持动态电压频率调节和体偏置技术。
3GHz@1.37V, 300MHz@0.52V, +237%性能提升@0.6V
JSSC 2014第4期Digital Circuits
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications Shu-Y u Hsu, Student Member , IEEE
一款用于移动医疗的机器学习辅助心脏传感器SoC，具备低功耗和高精度检测能力。
90nm CMOS, 0.5V–1.0V, 486-to-1052 µW
JSSC 2014第4期RF & WirelessPLLTransceiver
A –90 dBm Sensitivity Wireless Transceiver Using VCO-PA-LNA-Switch-Modulator Co-Design for Low Power Insect-Based Wireless Sensor Networks Serkan Sayilir, Student Member , IEEE ,W i n g - F a i L o k e, Student Member , IEEE , Jangjoon Lee, Student Member , IEEE, Harry Diamond ,M e m b e r ,I E EE
一种用于昆虫无线传感器网络的低功耗、小尺寸无线收发器，集成VCO、PA、LNA、开关和调制器。
0.13µm CMOS, -90dBm灵敏度@1Mbps, 1.2mW-4.5mW功耗
JSSC 2014第4期Power ManagementTDC
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register KwangSeok Kim, Student Member , IEEE ,W o n S i k Y u, Student Member , IEEE ,a n d
提出一种65纳米工艺下的9位112皮秒分辨率流水线时间数字转换器
112 ps分辨率, 250 MS/s, 15.4 mW功耗
JSSC 2014第4期Data Converters
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs
提出一种数字后台校准技术，用于消除VCO型ADC的非线性失真，显著提升信噪比。
90nm CMOS, 5MHz带宽, SNDR从46dB提升至73dB, 功耗4.1mW, 91-112fJ/conv-step
JSSC 2014第4期Clocking & PLLsDLL
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface Masum Hossain, Farrukh Aquil, Pak
一款基于快速锁定抖动滤波全数字DLL的突发模式内存接口，提升能效30%并实现零空闲功耗。
800 Mb/s至3.2 Gb/s, 24 mW锁定功耗, 6 mW@1.6 GHz工作功耗, <33 mUI残余时序误差
JSSC 2014第4期MemoryDRAM
A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 µW, 78 pArms, 400 V/s FSCV Sensing Bardia Bozorgzadeh, Student Member , IEEE, Daniel P . Covey, Christopher D. Howard, Paul A. Garris
一款用于体内神经化学模式生成的SoC，集成电刺激与快速扫描循环伏安法传感技术。
输入噪声电流78 pA rms (dc – 5 kHz), 输入电流范围±950 nA, 功耗9.3 µW
JSSC 2014第4期Clocking & PLLsPLLCDR
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop Guanghua Shu, Student Member , IEEE, Saurabh Saxena, Woo-Seok Choi, Mrunma y Talegaonkar, Rajesh Inti
提出一种无参考半速率数字时钟数据恢复电路，采用相位旋转锁相环作为相位插值器。
90nm CMOS, 5Gb/s, 13.1mW, 5.0ps/44.0ps长期抖动, 2MHz JTRAN带宽, 16MHz JTOL角频率
JSSC 2014第4期RF & Wireless
A Self-Powered CMOS Recon figurable Multi-Sensor SoC for Biomedical Applications Y u-Jie Huang, Te-Hsuen Tzeng, Tzu-Wei Lin, Che-Wei Huang, Pei-Wen Y en, Po-Hung Kuo, Chih-Ting Lin
一种自供电CMOS可重构多传感器SoC，用于生物医学应用。
11.25 mm²芯片面积，功耗942.9 µW
JSSC 2014第4期Other
A Self-Powered System for Large-Scale Strain Sensing by Combining CMOS ICs With Large-Area Electronics Yingzhe Hu, Student Member , IEEE , Liechao Huang , Student Member , IEEE
结合CMOS IC与大面积电子技术的自供电大规模应变传感系统
DC-AC功率转换效率30%，DC-DC转换器总效率80.5%，应变传感噪声23μStrain，通信距离7.5m时能效14.6pJ/4.3pJ(Tx/Rx)
JSSC 2014第4期Data Converters
A Stackable, 6-Cell, Li-Ion, Battery Management IC for Electric V ehicles With 13, 12-bit ADCs, Cell Balancing, and Direct-Connect Current-Mode Communications
一种可堆叠的6单元锂离子电池管理芯片，适用于电动汽车，支持192单元监控。
12 bit ADC, 5 mV精度, <1.5 mV匹配, <15 µA静态电流
JSSC 2014第4期Clocking & PLLsPLL
A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based
32nm SOI工艺中采用深沟槽电容的自适应PLL设计，优化时钟数据补偿效果
处理器Fmax提升15.6%，动态功耗降低9.8%，PLL面积减少92.1%
JSSC 2014第4期Data ConvertersPipeline ADCDAC
A Time-Based Pipelined ADC Using Both V oltage and Time
提出一种结合电压和时间域信息的基于时间的流水线ADC，提高分辨率和能效。
69.3 dB SNDR, 6.38 mW, 70 MHz
JSSC 2014第4期Other
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process V ertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme Meng-Fan Chang, Chia-Chen Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Y a-Chin King, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Jui-Jen Wu, and Y ue-Der Chih
提出基于逻辑工艺垂直寄生BJT开关的ReRAM宏，实现高密度和快速读取。
0.18µm 1Mb和65nm 2Mb ReRAM宏，读取时间小于5ns
JSSC 2014第4期Other
Digital Object Identi fier 10.1109/JSSC.2014.2313391
无摘要
JSSC 2014第4期Other
Digital Object Identi fier 10.1109/JSSC.2014.2313432
无摘要提供，无法生成概要
无
JSSC 2014第4期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路的分析、设计与性能研究，涵盖数字、模拟、微波和光电子电路。
无
JSSC 2014第4期Other
Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits T HIS i
2013年VLSI电路研讨会精选论文介绍，涵盖电路设计与半导体技术的最新进展。
无
JSSC 2014第5期RF & WirelessNeural Network Accelerator
A 0.5-to-3 GHz Software-De fined Radio Receiver Using Discrete-Time RF Signal Processing Run Chen, Student Member , IEEE
一款采用离散时间射频信号处理的软件定义无线电接收器，具有高谐波抑制和频率选择性。
0.5-to-3 GHz, IIP3 > 11 dBm, IIP2 > 46 dBm, 谐波抑制 >46 dB/51 dB
JSSC 2014第5期Power Management
A 12 pJ/Pixel Analog-to-Information Converter Based 816 × 640 Pixel CMOS Image
提出一种基于816×640像素CMOS图像传感器的12皮焦耳每像素模拟信息转换器，实现高效能图像压缩。
12皮焦耳每像素（压缩模式），48皮焦耳每像素（原始数据模式），28.7帧每秒
JSSC 2014第5期RF & WirelessPLLRadar
A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS
一款用于FMCW雷达的多速率全数字分数N锁相环，具有高频宽调制能力
65 nm CMOS, 1.2 V, 590.2 fs rms抖动, -74 dBc参考杂散
JSSC 2014第5期Data ConvertersSAR ADC
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range Badr Malki, Student Member , IEEE , Takaya Yamamoto, Bob V erbruggen , Member , IEEE
一种采用自适应动态范围的70dB DR 10位0至80MS/s电流积分SAR ADC
40nm CMOS, 1.1V, 0-80MS/s, 70dB DR, 56.85dB SNDR@40MS/s
JSSC 2014第5期RF & Wireless
A 780–950 MHz, 64–146 µW Power-Scalable Synchronized-Switching OOK Receiver for Wireless Event-Driven Applications
一款低功耗事件驱动的OOK接收器，采用同步切换技术，功耗可调，覆盖780-950MHz频段。
10 kbps时灵敏度-86 dBm，功耗123 µW，1 V供电
JSSC 2014第5期RF & WirelessRadar
A Centimeter Resolution, 10 m Range CMOS Impulse Radio Radar for Human
一款厘米级分辨率、10米范围的CMOS脉冲雷达，用于人体运动监测。
130nm CMOS, 1.2V, 80mA
JSSC 2014第5期Power Management
A Fast-Response Hybrid SIMO Power Converter with Adaptive Current Compensation and Minimized Cross-Regulation
提出一种采用自适应电流补偿技术的混合SIMO电源转换器，显著提升瞬态响应并减少交叉调节效应。
输入电压3V，输出电压1.8V/1.2V，开关频率500kHz，峰值效率82.8%，瞬态响应时间50.3ns
JSSC 2014第5期Data ConvertersVCOTDC
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and
提出一种基于开关环形振荡器的高分辨率时间数字转换器，无需校准即可实现噪声整形。
90nm CMOS, 1V, 500MS/s, 315fs噪声, 1.5mW功耗
JSSC 2014第5期Power Management
Absolute V alue, 1% Linear and Lossless Current-Sensing Circuit for the Step-Down DC-DC Converters With Integrated Power Stage
提出了一种用于PWM模式降压DC-DC转换器的线性无损电流检测电路，通过测量功率级平均压降实现高精度电流检测。
10mA至2.1A范围内线性误差<1%，转换增益精度±4%
JSSC 2014第5期Digital Circuits
An Energy Ef ficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS Dongsuk Jeon, Student Member , IEEE, Michael B. Henry, Y ejoong Kim, Inhee Lee , Student Member , IEEE
提出一种能效优化的全帧特征提取加速器，采用移位锁存技术和算法-架构协同优化，显著降低能耗。
28nm LP CMOS, 470mV, 27MHz, 2.7mW, 30fps VGA
JSSC 2014第5期Clocking & PLLsPhased Array
Analysis and Design of a 54 GHz Distributed “Hybrid” Wave Oscillator Array With Quadrature Outputs Anna Moroni
54 GHz分布式混合波振荡器阵列的分析与设计
125 dBc/Hz（单振荡器）, 131 dBc/Hz（4元素阵列）, 36 mW功耗, FoM 183.7 dBc/Hz
JSSC 2014第5期Data ConvertersPipeline ADC
Analysis of Metastability in Pipelined ADCs
分析流水线ADC中比较器亚稳态引起的误差机制及其预测方法。
8-bit, 600 MS/s
JSSC 2014第5期RF & WirelessOp-Amp
Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity Dlovan H. Mahrof , Student Member , IEEE , Eric A. M. Klumperink , Senior Member , IEEE
提出负导抗技术消除运放虚地非线性失真，提升接收机线性度。
65nm CMOS, 1.2V, 27mA, 2GHz, IIP3提升11dB至20dBm
JSSC 2014第5期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路的分析、设计与性能研究，涵盖数字、模拟、微波及光电子集成电路。
无具体指标
JSSC 2014第5期RF & Wireless
Introduction to the Special Section on the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
介绍2013年IEEE射频集成电路研讨会精选论文，涵盖射频与微波电路技术的多个方面。
75 dBc/Hz相位噪声, 590.2 fs均方根抖动
JSSC 2014第5期RF & WirelessPLL
MAY 2014 VOLUME 49 NUMBER 5 IJSCBC (ISSN 0018-9200) SPECIAL SECTION ON THE IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM Introduction to the Spec i a lS e c t i o no nt h eI E E ER a d i oF r e q u e n c yI ntegrated Circuits (RFIC) Symposium . . .. . . W. Khalil 1079
IEEE JSSC 2014年5月刊包含多篇关于射频集成电路和无线通信技术的论文。
56.4-to-63.4 GHz, 0.5-to-3 GHz, 10米范围
JSSC 2014第5期RF & Wireless
Multi-Drive Stacked-FET Power Ampli fiers at 90 GHz in 45 nm SOI CMOS
提出多驱动堆叠FET功率放大器，提升90 GHz下输出功率和效率。
45 nm SOI CMOS, 3.4 V, 19 dBm输出功率, 14% PAE, 12 dB增益
JSSC 2014第5期RF & Wireless
Nanostructured CMOS Wireless Ultra-Wideband Label-Free PCR-Free DNA Analysis SoC Hamed Mazhab Jafari , Student Member , IEEE, Karim Abdelhalim , Student Member , IEEE, Leyla Soleymani, Edward H. Sargent, Shana O. Kelley
一款全集成无线超宽带免标记免PCR的DNA分析SoC芯片，采用纳米结构CMOS技术实现高灵敏度检测。
0.13µm CMOS, 1.2V, 50Mb/s无线传输, 10aM检测限
JSSC 2014第6期RF & Wireless
0.56 V , –20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop Lingli Xia, Jiao Cheng, Neil E. Glover, and
一种无电池、多节点的无线体域网系统芯片，通过效率跟踪环和注入锁定频率分频器实现高效能量收集和时钟同步。
904.5 MHz下最小RF灵敏度优于-20 dBm，支持20 dBm（30 dBm）基站功率，距离3 m（9 m）
JSSC 2014第6期Data ConvertersDAC
A 10 bit, 300 MS/s Nyquist Current-Steering Power DAC With 6 V Output Swing Mohammad S. Mehrjoo , Student Member , IEEE, and James F. Buckwalter , Senior Member , IEEE
一款10位300MS/s电流导向DAC，采用堆叠FET缓冲实现6V输出摆幅。
10位, 300MS/s, 6V输出摆幅, 476mW功耗, SFDR 73dB, IM3 -69dBc
JSSC 2014第6期Data ConvertersPipeline ADCOp-Amp
A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue
一种12位200MS/s的基于零交叉技术的流水线ADC，采用背景校准技术消除系统性和随机性偏移。
12位, 200MS/s, 64.6dB SNDR, 82.9dBc SFDR, 30.7mW
JSSC 2014第6期RF & WirelessNeural Network Accelerator
A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS
65nm CMOS工艺下集成了Blixer和基带混合滤波器的24 GHz ZigBee接收器
65nm CMOS, 8.5 dB NF, 57 dB增益, 6-dBm IIP3, 1.7 mW功耗, 0.24 mm²芯片面积
JSSC 2014第6期RF & WirelessNeural Network Accelerator
A 4-Element Phased-Array System With Simultaneous Spatial- and Frequency-Domain Filtering at the
一种采用8相位被动混频器的4元件LO相位偏移相控阵接收机，用于抑制超过0 dBm的强干扰。
28 nm CMOS, 0.6–4.5 GHz, 34–119 mW, 1 dB压缩点+12/+10 dBm, 噪声系数4–6.3 dB, IIP3 0–+2.6 dBm
JSSC 2014第6期RF & WirelessLNANeural Network Accelerator
A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Ampli fier With Complementary Transconductance Linearization Bum-Kyum Kim, Student Member , IEEE
采用0.18µm SOI CMOS工艺实现的高线性度1 GHz低噪声放大器，具有13 dB的噪声系数。
1 GHz频率下增益10.7 dB，噪声系数1.3 dB，输入参考1 dB压缩点3 dBm，带内IIP3 22 dBm
JSSC 2014第6期Wireline I/OEqualizer
A Low-Noise Design Technique for High-Speed CMOS
提出一种用于高速CMOS光接收器的低噪声设计技术，通过两阶段前端实现噪声与带宽的优化。
灵敏度-11.9 dBm @ BER, 跨阻增益83 dB, 25 Gb/s
JSSC 2014第6期Data ConvertersSAR ADCDAC
An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure
一种高效节能的异步2b步进SAR ADC，采用混合R-2RC DAC设计
180nm CMOS, 0.6V, 100-kS/s
JSSC 2014第6期Data Converters
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without
提出两种全数字自适应算法，消除ADC输出中的开关噪声影响。
12-bit, 40-MS/s, SNDR 64.9 dB（无噪声）/63.7 dB（噪声消除后）
JSSC 2014第6期RF & WirelessPower Amplifier
CMOS Doherty Ampli fier With V ariable Balun Transformer and Adaptive Bias Control for Wireless LAN Application Namsik Ryu, Seunghyun Jang, Kwang Chun Lee, and Y
提出一种采用可变巴伦变压器和自适应偏置控制的CMOS Doherty功率放大器，提高了效率和输出功率。
31.9 dBm P1dB, 51% PAE at P1dB, 22.8 dBm OFDM输出功率, 30.1% PAE
JSSC 2014第6期RF & Wireless
Design and Analysis of a W-band 9-Element Imaging Array Receiver Using Spatial-Overlapping Super-Pixels in
W波段9元素成像阵列接收器设计，采用空间重叠超像素技术提升毫米波成像性能。
峰值相干响应度1150 MV/W，非相干响应度1000 MV/W，最小NEP 0.28 fW/Hz，带宽87-108 GHz，每元素功耗225 mW
JSSC 2014第6期Other
Digital Object Identi fier 10.1109/JSSC.2014.2326919
该论文探讨了数字对象标识符在IEEE JSSC期刊中的应用。
无
JSSC 2014第6期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路的分析、设计与性能研究，涵盖数字、模拟、微波及光电子电路，特别关注集成电路与VLSI设计。
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JSSC 2014第6期Digital CircuitsNeural Network Accelerator
JUNE 2014 VOLUME 49 NUMBER 6 IJSCBC (ISSN 0018-9200) REGULAR PAPERS A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization . . .
IEEE JSSC 2014年6月刊收录了多篇关于高频电路设计和无线通信技术的论文。
如：65nm CMOS, 2.4 GHz, 0.56V
JSSC 2014第6期Digital CircuitsNeural Network Accelerator
Patent Abstracts The Patent Abstracts cited are intended to provide the minimum in- formation necessary for determining interest. The full text and images can be obtained from the U.S. Patent Of fice at http://www.uspto.gov 8,587,381 November 19, 2013 Even-Order Distortion Cancellation in Single-Ended Input, Differential Output Ampli fiers Using Feed-Back Inventors: Danilo Manstretta (Stradella, IT) and Fernando DeBernardinis (Pavia, IT)
专利涉及一种单端输入差分输出放大器的偶数阶失真消除技术
未明确提及
JSSC 2014第6期RF & WirelessOptical I/O
Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS Cheng Li, Student Member , IEEE,R u i B a i, Student Member , IEEE,A y m a n S h afik, Student Member , IEEE, Ehsan Zhian Tabasy , Student Member , IEEE, Binhao Wang, Geng Tan g, Student Member , IEEE, Chao Ma
硅光子收发器电路采用微环谐振器偏置波长稳定技术，实现高效光互连。
5 Gb/s下12.7 dB消光比，4.04 mW功耗；8 Gb/s下9 dBm灵敏度，2.2 mW功耗
JSSC 2014第7期Data ConvertersDelta-Sigma ADCVCO
0.3–4.3 GHz Frequency-Accurate Fractional- Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital - Modulator-Based
提出基于混合基数代数的新型分数频率合成器，解决传统方法精度与杂散问题。
0.18 µm SiGe BiCMOS, 0343 GHz
JSSC 2014第7期Memory
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for V ariation
提出一种采用自动背景检查方案的低功耗内容可寻址存储器，优化匹配线摆动和感应速度。
65nm CMOS, 1.2V, 500MHz, 0.77fJ/bit/search
JSSC 2014第7期Data ConvertersDACOp-Amp
A 0.039 mm Inverter-Based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT- -ADC in 65 nm CMOS Using Power- and Area-Ef ficient
提出了一种基于逆变器的低功耗连续时间ΔΣ ADC设计，采用65纳米CMOS工艺实现高性能
65nm CMOS, 1.1V, 686dB-SNDR, 10MHz带宽, 182mW功耗
JSSC 2014第7期Clocking & PLLs
A 0.54 THz Signal Generator in 40 nm Bulk CMOS With 22 GHz Tuning Range and Integrated Planar Antenna Wouter Steyaert, Student Member , IEEE
本文介绍了一种在40nm CMOS工艺中实现的0.54 THz信号发生器，具有22 GHz调谐范围。
40nm CMOS, 543 GHz, 31 dBm, 16.8 mW, 21.9 GHz tuning range
JSSC 2014第7期RF & WirelessVCO
A 120 GHz Fully Integrated 10 Gb/s Short-Range Star-QAM Wireless Transmitter With On-Chip Bondwire Antenna in 45 nm Low Power CMOS Noël Deferm, Student Member , IEEE
一款45纳米CMOS工艺集成120GHz短距离10Gbps无线发射器
45nm CMOS, 120GHz, 10Gb/s, 1m传输距离
JSSC 2014第7期RF & Wireless
A 19 dBm, 15 Gbaud, 9 bit SOI CMOS Power-DAC Cell for High-Order QAM W-Band Transmitters Stefan Shopov, Student Member , IEEE , Andreea Balteanu , Student Member , IEEE ,a n d Sorin P . V oinigescu, Senior Member , IEEE
一款45nm SOI CMOS工艺的19 dBm 15 Gbaud 9位功率DAC单元，用于W波段高阶QAM传输。
19 dBm输出功率, 8.9% PAE, 15 Gbaud, 9位分辨率
JSSC 2014第7期Other
A Continuous-Time Ripple Reduction Technique for Spinning-Current
提出一种新型霍尔传感器纹波消除技术，无需低通滤波即可抑制偏移纹波。
1 kHz旋转频率下纹波降低40 dB至10 μT，偏移25 μT，带宽超过100 kHz
JSSC 2014第7期RF & WirelessDAC
A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B
提出一种满足LTE要求的低带外噪声电流模式发射机，采用AB类功率混频器实现高效率与低噪声。
55nm CMOS, 1.8V, 96mW/34mW功耗, 158dBc/Hz RX-band噪声
JSSC 2014第7期RF & Wireless
A Filtering ΔΣ ADC for LTE and Beyond
提出一种用于LTE通信的滤波ADC，结合二阶ΔΣ调制器和三阶切比雪夫滤波器，优化噪声抑制性能。
65nm CMOS, 576/288 MHz时钟, 18.5/9.0 MHz带宽, 56.4/58.1 dB SNDR, 7.9/5.4 mW功耗
JSSC 2014第7期Digital Circuits
A Fine-Grain V ariation-Aware Dynamic -Hopping A VFS Architecture on a 32 nm GALS MPSoC Ivan Miro-Panades, Edith Beigné, Y vain Thonnart , Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Far hat Thabet, Benoit Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, and
提出一种32纳米工艺下的细粒度自适应电压频率调节架构，优化多处理器系统芯片的全局能效。
32 nm CMOS, 18.2% energy gains, 10% area overhead
JSSC 2014第7期Other
A Four-Channel, 36 V , 780 kHz Piezo Driver Chip for Structural Health Monitoring Ya n g G u o, Student Member , IEEE, Christopher Aquino
一款用于结构健康监测的四通道36V 780kHz压电驱动芯片。
36V, 780kHz, 40.5dB信号失真
JSSC 2014第7期RF & Wireless
A Sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications Patrick P . Mercier, Member , IEEE
设计了一种超低功耗2.4 GHz发射器，平均功耗78 pW，适用于低数据率传感应用。
0.18 µm CMOS, 0.8 V, 38 pJ/bit, 5 Mbps
JSSC 2014第7期RF & WirelessDelta-Sigma ADCDAC
A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode Receiver Charles Wu, Student Member , IEEE
一款基于65nm CMOS工艺的宽频带直接射频到数字多模接收器，支持400 MHz至4 GHz频率范围。
65nm CMOS, 1.1 V/1.5 V, 40 mW, 68 dB SNDR, 10 dBm IIP3
JSSC 2014第7期Power ManagementEnergy Harvesting
An Autonomous Piezoelectric Energy Harvesting IC Based on a Synchronous Multi-Shot Technique Pierre Gasnier, Jérôme Willemin, Sebastien Boi sseau, Ghislain Despess e, Cyril Condemine, Guillaume Gouvernet, and Jean-Jacques Chaillout
提出一种基于同步多电荷提取技术的自主压电能量收集集成电路。
AMS 0.35 µm 3.3 V, 1 µW @ 5 Hz, 61% efficiency
JSSC 2014第7期Other
Design and Analysis of a High-Ef ficiency High-V oltage Class-D Power
设计并分析了一种高效高压D类功率输出级，采用0.14µm SOI BCD工艺，峰值效率达94%。
80V, 94% peak efficiency
JSSC 2014第7期Digital CircuitsNeural Network Accelerator
Fast Charging and High Ef ficiency Switching-Based Charger With Continuous Built-In Resistance Detection and Automatic Energy Deliver Control for Portable Electronics Tzu-Chi Huang, Ruei-Hong Peng, Tsu-Wei Tsai , Student Member , IEEE,K e - H o r n g C h e n, Senior Member , IEEE
提出一种基于开关的快速充电器，采用连续内置电阻检测和自动能量传输控制技术，显著缩短充电时间并提高效率。
0.25 µm CMOS, 3 mm², 1 A充电电流, 87%峰值效率
JSSC 2014第7期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路的分析、设计与性能，涵盖集成电路与VLSI设计。
无
JSSC 2014第7期Other
Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC)
IEEE JSSC特刊介绍第39届欧洲固态电路会议的精选论文，涵盖模拟和数字电路领域。
78 pW平均功耗，1 bps占空比数据率
JSSC 2014第7期Other
JULY 2014 VOLUME 49 NUMBER 7 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE 39TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)
IEEE JSSC期刊特刊介绍及多篇固态电路技术论文摘要。
如：0.77 fJ/bit/search, 0.35V至1.2V SRAM
JSSC 2014第7期MemorySRAM
Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel ,S t u d e n tM e m b e r ,I E E E,A n i s Feki
提出一种可扩展的超宽电压范围SRAM设计方法，采用10晶体管位单元，实现低电压、高良率和硅-CAD相关性。
65nm BULK CMOS 485MHz, 28nm FDSOI 1GHz
JSSC 2014第7期Power ManagementBuck Converter
V ariable Off-Time Control Loop for Current-Mode Floating Buck Converters in LED Driving Applications Vlad Anghel, Christopher Bartholomeusz, An ca Gabriela V asilica
提出一种基于固定峰值电流和可变关断时间的LED驱动浮动降压转换器控制架构。
11-20V输入电压, 100-1000μH电感范围, 91%最大转换效率
JSSC 2014第8期Other
AUGUST 2014 VOLUME 49 NUMBE R 8 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE
IEEE JSSC 2014年8月特刊聚焦2013年集成电路会议，涵盖宽带传感器接口、低功耗温度传感器等创新研究。
40nm CMOS, 82mW
JSSC 2014第8期RF & Wireless
A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2
一款0.9V供电、28nm CMOS工艺的0.4-6GHz软件定义无线电接收器，支持谐波重组和宽频带操作。
28nm CMOS, 0.9V, 1.8dB NF, +3dBm IIP3, 70dB HR3/5, +80dBm IIP2, 20-40mW功耗
JSSC 2014第8期Data ConvertersSAR ADCTime-Interleaved ADC
A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB Yida Duan, Student Member , IEEE,a n dE l a dA l o n, Senior Member , IEEE
本文介绍了一种12.8 GS/s 32路分层时间交织SAR ADC，采用65 nm CMOS工艺，实现4.6 ENOB和25 GHz有效分辨率带宽。
12.8 GS/s, 4.6 ENOB, 25 GHz ERBW, 0.23 mm², 162 mW
JSSC 2014第8期RF & WirelessPLLClock Generation
A 21–48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point
一款用于毫米波无线多频段点对点回传通信的2148 GHz次谐波注入锁定分数N频率合成器。
20.6-48.2 GHz连续输出，220 kHz分辨率，1MHz偏移相位噪声-107.0至-113.9 dBc/Hz，功耗148mW
JSSC 2014第8期Power ManagementNeural Network Accelerator
A 40 V 10 W 93%-Ef ficiency Current-Accuracy- Enhanced Dimmable LED Driver With Adaptive Timing Difference Compensation for Solid-State Lighting Applications Dongkyung Park, Zhidong Liu , Student Member , IEEE,a n d H o iL e e, Senior Member , IEEE
一款高效率、高精度的40V 10W可调光LED驱动器，采用自适应时序差补偿技术
93%峰值效率, 345mA平均电流, 2.8%电流误差, 8.5μs稳定时间
JSSC 2014第8期Other
A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications Khaled Abdelfattah, Sherif Galal, Iu ri Mehr, Alex Jianzhong Chen, Chengyu e Y u, Maurice Tjie, Ahmet Tekin
40nm CMOS工艺下设计的82mW全集成立体声耳机模块，支持直接电池连接。
40nm CMOS, 3.1-4.5V, 100dB动态范围, 84dB THD+N, 0.675mm²面积
JSSC 2014第8期RF & WirelessEqualizer
A 5 Gb/s Energy-Ef ficient V oltage-Mode Transmitter Using Time-Based De-Emphasis Saurabh Saxena, Student Member , IEEE, Romesh Kumar Nandwana , Student Member , IEEE,a n d Pavan
提出一种基于时间均衡的电压模式驱动器，实现5 Gb/s高效能传输
5 Gb/s, 15.6 mW, 3.1 mW/Gb/s
JSSC 2014第8期Data ConvertersPipeline ADC
A 7.1 mW 1 GS/s ADC With 48 dB SNDR at
一种采用双级流水线ADC设计的1 GHz采样率转换器，在奈奎斯特频率下实现48 dB SNDR和25 fJ/转换步的能效。
65nm CMOS, 1V, 1GS/s, 48dB SNDR, 25fJ/conversion-step
JSSC 2014第8期Clocking & PLLsPLL
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function Sigang Ryu, Student Member , IEEE, Hwanseok Y eo, Student Member , IEEE, Y oontaek Lee
提出一种9.2 GHz无峰值抖动传递函数的数字锁相环，采用新型数字环路滤波器实现快速稳定。
65nm CMOS, 1.2V, 1.2 ps集成抖动, 1.58 s稳定时间, 700 kHz带宽, 63.9 mW功耗
JSSC 2014第8期MemoryEmerging Memory
A Bit-by-Bit Re-Writable E fla s hi naG e n e r i c6 5n m Logic Process for Moderate-Density Nonvolatile Memory Applications Seung-Hwan Song, Ki Chul Chun, and Chris H. Kim , Senior Member , IEEE
提出一种在65nm逻辑工艺中实现的可逐位重写的嵌入式闪存技术，解决未选字线干扰问题。
65nm CMOS, 未提及电压及速度
JSSC 2014第8期RF & Wireless
A Broadband Sensor Interface IC for Miniaturized Dielectric Spectroscopy From MHz to GHz Mehran Bakhshiani, Student Member , IEEE , Michael A. Suster , Member , IEEE,a n d
一款用于微型化介电光谱测量的宽带传感器接口IC
0.35 µm 2P/4M RF CMOS, 50 MHz至3 GHz
JSSC 2014第8期RF & Wireless
A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes Seokhyeon Jeong, Student Member , IEEE , Zhiyoong Foo, Y oonmyung Lee ,M e m b e r, IEEE
提出一种全集成71nW CMOS温度传感器，适用于低功耗无线传感系统。
71nW功耗/0.3°C精度/2.2nJ每转换
JSSC 2014第8期Data Converters
A Monolithic Digital Ripple-Based Adaptive-Off- Time DC-DC Converter With a Digital Inductor
本文提出了一种基于数字纹波的自适应关断时间DC-DC转换器，采用数字电感电流传感器获取纹波信号，无需额外ADC或电感DCR知识。
2MHz开关频率，91%峰值效率，100mA负载电流
JSSC 2014第8期Data ConvertersTime-Interleaved ADC
A n8B i t4G S / s1 2 0m WC M O SA D C
采用四通道时间交织ADC及新型时序失配检测算法，实现44.4 dB SNDR和219 fJ/转换步的能效。
44.4 dB SNDR, 219 fJ/conversion-step
JSSC 2014第8期RF & WirelessPLLTDC
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs Salvatore Levantino,M e m b e r ,I E E E
提出一种自适应预失真技术，有效降低数字锁相环中的DTC非线性问题。
3.6-GHz, 4.2 mW, 103 dBc/Hz
JSSC 2014第8期Data Converters
Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling Manideep Gande, Student Member , IEEE, Hariprasath V enkatram, Member , IEEE, Ho-Y oung Lee
提出一种无需外部校准信号的首创盲校准算法，用于抑制ADC中的非线性失真。
0.13μm CMOS, SNDR提升39dB, SFDR提升45dB
JSSC 2014第8期RF & WirelessPhased Array
Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming
提出一种基于梯形滤波器的可编程时延元件，用于超宽带波束成形系统。
3.1–10.6 GHz, 140 ps延迟范围, 30 dB至10 dB增益范围, 53 mW功耗, 2.5 V供电
JSSC 2014第8期Other
Digital Object Identi fier 10.1109/JSSC.2014.2338692
该论文未提供摘要，无法进行概要总结。
无
JSSC 2014第8期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路设计、分析与性能的广泛研究。
无
JSSC 2014第8期RF & Wireless
Introduction to the Special Issue on the 2013 IEEE Custom Integrated
2013 IEEE CICC精选论文集，涵盖模拟/混合信号技术、数据转换等领域。
110 dB PSRR, 100 dB动态范围, 84 dB THD+噪声
JSSC 2014第8期Other
Sampling Circuits That Break the kT/C Thermal
提出两种电路技术突破kT/C热噪声限制，分别通过改变采样带宽与噪声源关系及主动噪声消除实现。
热噪声功率降低48%和67%
JSSC 2014第9期Clocking & PLLs
A1 0G b / s ,6Vp-p, Digitally Controlled, Differential Distributed Amplifier MZM Driver
采用0.18µm SiGe-BiCMOS工艺实现的10Gb/s数字控制差分分布式放大器MZM驱动器，输出6Vp-p差分摆幅。
0.18µm SiGe-BiCMOS, 6Vp-p, 10Gb/s, 2.13W
JSSC 2014第9期Other
A - B a n dF o u r - E l e m e n tB u t l e rM a t r i xi n0 . 1 3µ m SiGe BiCMOS Technology Mohamed Elkhouly, Student Member , IEEE,Y a n f e i M a o, Student Member , IEEE,C h afik Meliani, Member , IEEE, J.
本文介绍了一种基于0.13µm SiGe BiCMOS工艺的220-240 GHz四元件巴特勒矩阵波束切换芯片设计。
2 dB插入损耗, 15°最大相位误差, 4 dB rms幅度变化, 104 mA@3.3V
JSSC 2014第9期Digital CircuitsCMOS Image Sensor
A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network Cong Shi, Student Member , IEEE, Jie Y ang, Y e Han, Zhongxiang Cao, Qi Qin
提出一种基于动态可重构混合架构的1000 fps视觉芯片，集成高速CMOS图像传感器与多处理器架构。
256×256图像传感器, 64×64 PE阵列/16×16 SOM, 0.18μm CMOS工艺, 1000fps
JSSC 2014第9期Data ConvertersPipeline ADC
A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC
本文介绍了一种采用0.18µm BiCMOS工艺的12位1.6 GS/s流水线ADC，具有四路时间交织分层结构和主从T&H，以提高动态性能并降低误差率。
12位, 1.6 GS/s, SFDR 79 dBc/66 dBc, 误差率<10, 功耗1.15 W
JSSC 2014第9期RF & WirelessNeural Network Accelerator
A 2 GS/s Frequency-Folded ADC-Based Broadband
一种基于频率折叠ADC的宽带采样接收器，实现高采样率和动态范围。
2 GS/s, 125MHz-1000MHz带宽, 49dB SNDR, 104mW功耗
JSSC 2014第9期RF & WirelessPLLClock Generation
A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios
一种用于软件定义无线电的紧凑型低功耗分数注入锁定正交频率合成器
65nm CMOS, 10MHz-6.6GHz, 16-26mW, 0.38mm²
JSSC 2014第9期RF & WirelessTransceiver
A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory Hadar Dagan, Aviv S hapira
首款低成本、超低功耗、被动式24 GHz RFID标签，采用标准CMOS工艺单芯片集成。
0.18 µm CMOS, 3.6 mm × 1.6 mm, 13.2 µW
JSSC 2014第9期RF & WirelessEnergy Harvesting
A Micro Inertial Energy Harvesting Platform With Self-Supplied Power Management Circuit for Autonomous Wireless
实现了一种微型自供能能量采集平台，高效采集环境振动能量，无需电池启动，睡眠模式零功耗。
0.5 µW（工作模式）, 10 pW（睡眠模式）, 58–86%整流效率
JSSC 2014第9期RF & Wireless
A Scalable, 2.9 mW, 1 Mb/s e-Textiles Body Area Network Transceiver With Remotely-Powered Nodes and Bi-Directional
本文提出了一种用于体域网的可扩展、低功耗收发器及无线供电系统，支持1 Mb/s数据传输。
0.18 µm CMOS, 1 Mb/s, 29 mW, 34 µW能量回收
JSSC 2014第9期Power ManagementBiosignal
A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks Jiawei Xu, Srinjoy Mitra, Akinori Matsumoto, Shrishail Patki, Chris V an
一种可穿戴的8通道无凝胶EEG/电极-组织阻抗采集系统，具有高输入阻抗和低噪声特性。
1.2 GΩ输入阻抗（20 Hz时），1.75 µVrms输入参考噪声（0.5–100 Hz），84 dB CMRR，±250 mV电极偏移抑制能力
JSSC 2014第9期RF & WirelessPLLRadar
An X-Band Radar Transceiver MMIC with Bandwidth Reduction in 0.13 µm SiGe Technology
本文提出了一种采用0.13µm SiGe工艺的X波段雷达收发器，通过带宽降低技术实现高效距离检测。
0.13µm SiGe, 2.2V/1.5V供电, 326mW(接收)/333mW(发射), 3.5×2.5mm²芯片面积
JSSC 2014第9期RF & WirelessOp-Amp
Comments and Corrections Comments on “Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity” P . V . Ananda Mohan, Eric A. M. Klumperink, Dlovan H. Mahrof, and Bram Nauta In the above paper [1], not only [2] but also older papers [3]–[5] ex- ploiting a negative impedance connected to the virtua l ground node should have been included as references. As discussed more exten- sively in a recent book [6], all these papers aim at mitigating the vir-
评论并补充关于消除运放虚拟地缺陷的参考文献。
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JSSC 2014第9期mm-WaveESD
Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection X. Shawn Wang , Student Member , IEEE, Xin Wang, Fei Lu, Chen Zhang, Zongyu Dong ,L i W a n g
本文提出了一种8.5 kV ESD保护的SP10T开关设计，适用于多频段智能手机。
0.18μm CMOS, 36.4/34.2 dBm, 0.48/0.81 dB, 43/40 dB
JSSC 2014第9期RF & Wireless
Current-Mode Transceiver for Silicon Interposer Channel Seung-Hun Lee, Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, and Jae-Y
提出一种用于硅中介层通道的3Gb/s电流模式收发器，能效达9.5fJ/b/mm
3Gb/s, 9.5fJ/b/mm (10mm点对点), 29.4fJ/b/mm (20mm四路源同步)
JSSC 2014第9期Data ConvertersFlash ADCNeural Network Accelerator
Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold Philipp Ritter, Stéphane Le Tual
提出新型比较器布局和参考电压阶梯设计，实现无跟踪保持的6位20GS/s SiGe BiCMOS闪存ADC。
6位分辨率，20GS/s采样率，1.0W功耗，3.9pJ/转换步
JSSC 2014第9期Other
Digital Object Identi fier 10.1109/JSSC.2014.2348863
该论文探讨了数字对象标识符在IEEE JSSC期刊中的应用。
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JSSC 2014第9期Other
Introduction to the Special Section on the 2013 IEEE Bipolar/BiCMOS Circuits and
2013 IEEE Bipolar/BiCMOS会议精选论文，涵盖SiGe BiCMOS技术中的ADC和CDR设计创新。
SFDR 79 dBc/66 dBc, 3.7位有效分辨率@10 GHz, 100 GHz时钟提取
JSSC 2014第9期RF & WirelessVCO
Pulling Mitigation in
提出一种新型架构，有效抑制无线发射器中VCO因自身信号或其他振荡器引起的频率牵引效应。
16QAM信号下EVM从11%降至2.4%，抑制互扰边带20dB以上
JSSC 2014第9期Data Converters
Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails Inyong Kwon, Student Member , IEEE, Seongjong Kim
Razor-Lite是一种低开销寄存器，用于错误检测和校正系统，通过电荷共享技术实现低开销。
45nm SOI CMOS, 83% energy improvement, 4.4% core area overhead
JSSC 2014第9期Other
SEPTEMBER 2014 VOLUME 49 NUM BER 9 IJSCBC (ISSN 0018-9200) SPECIAL SECTION ON THE 2013 IEEE BIPOLAR/ BICMOS CIRCUITS AND TECHNOLOGY MEETING
2014年IEEE JSSC期刊特辑聚焦BiCMOS电路与技术，涵盖高速ADC、雷达收发器等前沿研究。
12位1.6GS/s, 6位20GS/s, X波段
JSSC 2014第9期RF & WirelessCDR
SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link Quentin Béraud-Sudreau
130nm BiCMOS SiGe工艺下设计的100Gbit/s时钟数据恢复系统，采用注入锁定振荡器。
100GHz时钟，50Gb/s输入数据，1.2ps rms抖动，1.4W功耗，2.3V电源
JSSC 2014第10期Other
AR e c o nfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels Jun-Eun Park, Student Member , IEEE, Dong-Hyuk Lim
一款可配置SNR和帧率的电容式触摸屏读IC，具有高抗噪性和触摸灵敏度。
40-to-67 dB SNR, 50-to-6400 Hz frame rate, 6.26 mW power consumption
JSSC 2014第10期Image SensorsCMOS Image Sensor
A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for
一款用于机器视觉的高灵敏度400帧/秒CMOS图像传感器
640×480分辨率，8.7×8.22μm²像素尺寸，36.5V/lux·s灵敏度，15.6e-噪声，0.55%FPN
JSSC 2014第10期Image Sensors
A 240 × 180 130 dB 3 µs Latency Global Shutter Spatiotemporal Vision Sensor Christian Brandli,S t u d e n tM e m b e r ,I E E E
提出一种动态和主动像素视觉传感器，同时输出异步DVS事件和同步全局快门帧。
240×180传感器阵列，130 dB动态范围，3 µs延迟，51 dB动态范围
JSSC 2014第10期RF & Wireless
A 25-to-28 Gb/s High-Sensitivity ( 9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects
65nm CMOS工艺下25至28 Gb/s高灵敏度光接收器设计
28 Gb/s, 137.5 mW, 4.9 mW/Gb/s
JSSC 2014第10期Image Sensors
A 3-D Camera With Adaptable Background Light Suppression Using Pixel-Binning and Super-Resolution Jihyun Cho, Jaehyuk Choi, Seong-Jin Kim, Seokjun Park, Jungsoon Shin, James D. K. Kim, and Euisik Y oon
提出一种采用列级背景光抑制方案的CMOS TOF 3D相机，适用于高分辨率户外成像。
5.9μm像素间距，24%填充因子，1.47cm-rms时间噪声，1%非线性，100klx背景光抑制
JSSC 2014第10期RF & Wireless
A 5 Gb/s, 10 ns Power-On-Time, 36 W Off-State Power, Fast Power-On Transmitter for Energy Proportional Links Tejasvi Anand, Student Member , IEEE
提出一种快速启动的发射器架构，实现服务器和移动平台的能效比例通信。
90nm CMOS, 1.1V, 5Gb/s, 10ns启动时间, 4.8mW/36W开关态功耗
JSSC 2014第10期Data Converters
A Column Driver Architecture With Double Time-Division Multiplexing RDACs for TFT-LCD Applications
提出一种双时分复用RDAC的TFT LCD列驱动架构，提升线性度和均匀性。
0.35μm/0.5μm CMOS, 18.2 MSPS, 0.017 mm²/channel
JSSC 2014第10期Clocking & PLLsNeural Network Accelerator
A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input
提出一种灵活的无时钟数字滤波器，频率响应独立于输入速率和格式。
16-tap, 8-bit FIR滤波器
JSSC 2014第10期RF & Wireless
A Frequency-Agile RF Frontend Architecture for Multi-Band TDD Applications
提出一种频率敏捷的射频前端架构，支持多频段TDD应用，实现高效集成。
45 nm SOI CMOS, 1.3-3.3 GHz, 27.7 dBm, 30%效率
JSSC 2014第10期RF & Wireless
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg ,S t u d e n tM e m b e r ,I E E E, Sunjay Dodani, Parag G. Patil, and Michael P . Flynn , Senior Member , IEEE
一种全自包含的对数闭环深脑刺激SoC，用于神经疾病治疗。
180 nm CMOS, 468 W
JSSC 2014第10期RF & WirelessDAC
A High Modulation Bandwidth, 110 GHz Power-DAC Cell for IQ Transmitter Arrays With Direct Amplitude and Phase Modulation Andreea Balteanu, Student Member , IEEE , Stefan Shopov , Student Member , IEEE ,a n d Sorin P . V oinigescu, Senior Member , IEEE
研究毫米波功率DAC发射机架构的最大波特率及W波段可扩展性。
29 GHz OOK和BPSK调制带宽，2×44 Gb/s BPSK+OOK数据速率，7.5 pJ/bit能效，12 dBm输出功率
JSSC 2014第10期Medical & Bio
A High Resolution Interface for Kelvin
提出一种高精度阻抗传感接口芯片，用于电化学和生物传感应用。
15位分辨率，150 ppm温度精度，86-95 dB动态范围
JSSC 2014第10期Clocking & PLLs
A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation Ni Xu
提出一种无需DCO非线性校准的混合环路两点调制器架构。
1.8GHz, 6.9mW@1V, EVM 1.63%-1.96%
JSSC 2014第10期Other
A Single-Inductor 0.35 µm CMOS Energy-Investing
提出一种单电感0.35µm CMOS压电能量收集器，通过电池能量注入提升输出功率
0.35µm CMOS, 79µW输出功率, 69%峰值转换效率
JSSC 2014第10期RF & WirelessVCODLL
An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS Mrunmay Talegaonkar, Student Member , IEEE ,A m r E l s h a z l y, Member , IEEE, Karthikeyan Reddy, Student Member , IEEE , Praveen Prabha , Student Member , IEEE , Tejasvi Anand, Student Member , IEEE, and Pavan
90纳米CMOS工艺下实现6ns快速启动的突发模式发射器，能效达2.29mW/Gb/s。
90nm CMOS, 8Gb/s峰值数据率, 2.29mW/Gb/s能效
JSSC 2014第10期RF & Wireless
An EDGE/GSM Quad-Band CMOS Power Ampli fier
提出一种用于EDGE应用的线性功率放大器，采用0.18µm CMOS工艺，自适应偏置改善AM-AM特性。
22%和23%功率附加效率，28.5 dBm和27.5 dBm输出功率
JSSC 2014第10期RF & Wireless
Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering Radha S. Rajan
通过嵌入式滤波器优化连续时间ΔΣ调制器的动态范围和功耗
信号带宽=2 MHz, VGA增益=0至18 dB, 二阶巴特沃斯滤波器截止频率=4 MHz
JSSC 2014第10期Other
INFORMATION FOR AUTHORS Content The IEEE J OURNAL OF SOLID STATE CIRCUITS is published monthly. Contrib uted papers may be of a tutorial or research nature, but the latter must be original and must
IEEE JSSC期刊专注于固态电路的分析、设计与性能研究，涵盖数字、模拟、微波及光电子集成电路。
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JSSC 2014第10期Other
Introduction to the Special Section on the 2013 Compound Integrated
2013年化合物集成电路研讨会精选论文，展示化合物半导体技术的最新进展。
80 GHz, 100 mW/200 mW, PAE >30%
JSSC 2014第10期Other
Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers
采用250nm InP DHBT工艺设计的50 GSamples/s跟踪保持和采样保持放大器。
250nm InP DHBT, 5V/2.5V供电, 16-17dBm IIP3, 2-22GHz
JSSC 2014第10期mm-Wave
Millimeter-Wave Series Power Combining Using Sub-Quarter-Wavelength Baluns Hyun-chul Park, Student Member , IEEE, Saeid Daneshgar, Zach Grif fith, Senior Member , IEEE,M i g u e l U r t e a g a
提出一种毫米波功率合成技术，使用短于四分之一波长的巴伦实现晶体管输出串联和电感调谐。
86 GHz, 30.4% PAE, 20.37 dBm, 23 GHz 3-dB带宽
JSSC 2014第10期Other
New Associate Editor I T IS with pleasure that I welcome Dr Ken Suyama to the Jo
欢迎Ken Suyama博士加入IEEE JSSC期刊，担任副编辑，他在模拟电路和混合信号电路领域具有丰富经验。
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JSSC 2014第10期Other
OCTOBER 2014 VOLUME 49 NUMBE R 10 IJSCBC (ISSN 0018-9200) SPECIAL SECTION ON THE 2013 COMPOUND INTEGRATED CIRCUITS SYMPOSIUM
该期刊包含多篇关于高频电路设计和功率放大器的研究论文。
110 GHz功率-DAC单元，50 GSamples/s采样率
JSSC 2014第10期Clocking & PLLs
Patent Abstracts The Patent Abstracts cited are intended to provide the minimum in- formation necessary for determining interest. The full text and images can be obtained from the U.S. Patent Of fice at http://www.uspto.gov 8,665,033 March 4, 2014 Varactorless tunable oscillator Inventors: Yiwu Tang (San Diego, CA), Jaehyouk Choi (Ulsan, KR), Jongmin Park (San Diego, CA), and Chiewcharn Narathong (San Diego, CA) Assignee: QUALCOMM Incorporated (San Diego, CA)
无变容二极管可调振荡器电路及数字锁相环电路
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JSSC 2014第10期mm-Wave
Performance Limits, Design and Implementation of m m - W a v eS i G eH B TC l a s s - Ea n dS t a c k e d Class-E Power Ampli fiers Kunal Datta, Student Member , IEEE
提出毫米波SiGe HBT超额定击穿电压Class-E功率放大器设计方法，实现高输出功率与高效率。
45 GHz输出20 dBm/31.5% PAE，41 GHz输出23.4 dBm/34.9% PAE
JSSC 2014第11期Other
1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis Erik Ryman, Student Member , IEEE, Anders Emrich, Stefan Back Andersson
提出一种用于地球同步轨道合成孔径成像的低功耗64通道相关器系统，采用两种ASIC实现高速信号处理。
数字ASIC处理2016个互相关，速度达3.6 GS/s，功耗仅0.13 mW/相关/GHz（1V供电）
JSSC 2014第11期Power ManagementBuck ConverterNeural Network Accelerator
A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS
提出一种40nm CMOS工艺的0.6V输入降压转换器，采用CCM/DCM自适应控制提高效率。
40nm CMOS, 0.6V输入, 0.3-0.55V输出, 峰值效率94%
JSSC 2014第11期Power Management
A 0.79 pJ/K-Gate, 83% Ef ficient Uni fied Core and V oltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS
提出一种嵌入计算子系统的电压调节架构，显著提升超低功耗平台能效。
83%效率（0.52-0.6V输出范围），系统级能耗降低44.8%
JSSC 2014第11期Analog Circuits
A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Ampli fier Linfei Guo
提出一种新型无滤波器D类放大器，具有高PSRR和低THD+N，适用于智能手机和SoC集成。
65nm CMOS, 3.6V, 500mW@8Ω, THD+N 0.0027%, 效率94%, PSRR -101dB@217Hz
JSSC 2014第11期Other
A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells
一款集成26400个电极的1024通道CMOS微电极阵列，用于高时空分辨率神经信号记录与刺激
2.4µV@AP频段(300Hz-10kHz), 5.4µV@LFP频段(1Hz-300Hz), 78dB可编程增益, 20kSamples/s采样率
JSSC 2014第11期MemorySRAM
A 128 Kbit SRAM With an Embedded Energy Monitoring Circuit and Sense-Ampli fier Offset Compensation Using
本文介绍了一种嵌入能量监测电路的128 Kbit SRAM，采用65纳米低功耗CMOS工艺，实现了高能效和高性能操作。
65nm CMOS, 370mV至1.2V供电范围, 能量监测精度10%以内
JSSC 2014第11期Power Management
A 13.56 MHz 40 mW CMOS High-Ef ficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated V oltage Doubler Rectifier and Multiple LDOs for Implantable
提出一种13.56MHz CMOS高效电感链路电源，用于植入式医疗设备，传输效率达76.3%，功率转换效率85%。
13.56MHz, 20mA输出电流, 76.3%传输效率, 85%功率转换效率, 384mV压降
JSSC 2014第11期RF & WirelessPLLVCO
A 13 pJ/bit 900 MHz QPSK/16-QAM Band Shaped Transmitter Based on Injection Locking and Digital PA for Biomedical Applications Xiayun Liu, Student Member , IEEE,M e h r a n M . I z a d, Member , IEEE, Libin Y ao, Senior Member , IEEE,a n d
一款基于注入锁定的高效能900 MHz QPSK/16-QAM带形变发射器
65nm CMOS, 0.77V, 50/100 Mbps, 38dB边带抑制, 6%EVM, 15dBm输出
JSSC 2014第11期RF & WirelessCDR
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking
介绍了一种基于22nm CMOS SOI技术的16Gb/s I/O链路接收器，采用8抽头DFE和波特率CDR实现高速数据传输。
16Gb/s, 3.7mW/Gb/s, 31kppm跟踪带宽
JSSC 2014第11期RF & WirelessCDR
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology Gautam R. Gangasani
32nm SOI CMOS工艺下32 Gb/s背板收发器，采用AC耦合和低延迟CDR技术
32 Gb/s, 30 dB损耗通道, 21 mW/Gbps, 1 V电源, 0.7 mm²面积
JSSC 2014第11期Power Management
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits Samantak Gangopadhyay, Dinesh Somasekhar ,M e m b e r ,I E E E, James W . Tschanz , Member , IEEE,a n d
32nm CMOS工艺下全数字锁相低压差稳压器，用于数字IC细粒度电源管理。
32nm CMOS, 峰值电流效率98%
JSSC 2014第11期Data ConvertersVCO
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS Laura Fick,S t u d e n tM e m b e r ,I E E E,D a v i d F i c k, Member , IEEE
一种基于VCO的无参考时钟传感器接口电路，面积仅346µm²，适用于低功耗传感器节点
28nm CMOS, 500mV-1.0V, 11.7µW@0.6V, 41.2fJ/b
JSSC 2014第11期Data ConvertersBiosignal
A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term
一款超低功耗多功能心电图处理器，采用近阈值电压设计，功耗仅457nW。
0.18 µm CMOS, 0.5 V, 457 nW
JSSC 2014第11期RF & WirelessSAR ADCEqualizer
A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver
一款6位10GS/s时间交织SAR ADC，集成低开销FFE/DFE均衡，适用于高速有线通信
6bit 10GS/s, 79.1mW, 0.33mm²核心面积
JSSC 2014第11期RF & WirelessSAR ADCDAC
A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode
提出一种采用数字校正技术的全集成SAR ADC，适用于三模收发器。
52 MS/s时SNDR 67.0 dB (GSM), 80 MS/s时58.2 dB (WCDMA/LTE)
JSSC 2014第11期Other
A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Y asuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, and Y asunori Tanaka
提出一种拓扑压缩的21晶体管静态触发器，功耗降低75%
40nm CMOS, 75%功耗降低, 0%数据活动时
JSSC 2014第11期Power ManagementLDO
A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load Xiao Liang Tan, Student Member , IEEE, Sau
提出一种加权电流反馈技术，用于无输出电容LDO稳压器，实现宽负载电容范围驱动和快速瞬态响应。
0.75V电源电压，15.9µA静态电流，50mA最大负载电流，470pF-10nF负载电容范围，400ns稳定时间
JSSC 2014第11期Other
A Monolithically Integrated Pressure/Oxygen/ Temperature Sensing SoC for Multimodality Intracranial Neuromonitoring Wai Pan Chan, Margarita Narducci, Y
本文介绍了一种用于多模态颅内神经监测的全集成SoC，集成了压力、氧气和温度传感器及其接口电路。
压力灵敏度18.6 aF/mmHg，氧气灵敏度194 pA/mmHg，温度灵敏度2 mV/°C，功耗166 μW
JSSC 2014第11期Power ManagementBuck Converter
A Multiphase Buck Converter With a Rotating Phase-Shedding Scheme For Ef ficient Light-Load Control Y oungkook Ahn
提出一种采用旋转相位脱落方案的多相降压转换器，以提高轻载效率。
2.7V-5V, 4.5A
JSSC 2014第11期RF & WirelessDRAM
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Y ong-Ju Kim, Y un-Saing Kim, Byungsub Kim, Jae-Y
提出一种低能耗单端双二进制收发器，用于DRAM接口，能效达0.56 pJ/bit@7Gb/s。
0.56 pJ/bit@7Gb/s, 80 mV信号摆幅
JSSC 2014第11期RF & WirelessHigh-Speed LinkEqualizer
An 8–16 Gb/s, 0.65–1.05 pJ/b, V oltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning Y
一种低功耗电压模式发射器，采用模拟阻抗调制技术，支持快速功率状态切换。
8-16 Gb/s, 0.65-1.05 pJ/b, 100-300 mV输出摆幅, 12 dB均衡
JSSC 2014第11期RF & WirelessBiosignal
An ECG-on-Chip With 535 nW/Channel Integrated Lossless Data Compressor for Wireless
提出一种低功耗ECG片上系统，集成无损数据压缩技术，适用于无线/移动ECG传感器。
0.35 µm, 2.4 V, 512 Hz, 535 nW/channel
JSSC 2014第11期RF & Wireless
An RF-to-BB-Current-Reuse Wideband Receiver With Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF
该论文提出了一种利用并行N路径有源/无源混频器的宽带接收器，实现了低噪声、高线性度和高功率效率。
NF 4.6-0.9 dB, IIP2/IIP3 +61/+17.4 dBm, 功耗10.6-16.2 mW, 面积0.55 mm²
JSSC 2014第11期Analog Circuits
Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter Massoud Tohidian, Student Member , IEEE , Iman Madadi , Student Member , IEEE
提出一种基于电荷共享旋转的高阶离散时间无源IIR低通滤波器，支持电压采样和电荷采样模式。
65nm CMOS, 1.2V, 800MS/s, 400kHz-30MHz带宽, 100dB阻带抑制, +21dBm IIP3, 4.57nV/√Hz噪声, 2mW功耗, 0.42mm²面积
JSSC 2014第11期MemorySRAM
Comments and Corrections Correction to “Recon figurable Processor for Energy-Efficient Computational Photography” Rahul Rithe, Priyanka Raina, Nathan Ickes, Srikanth Tenneti, and Anantha P . Chandrakasan In the above paper [1], an error was made in reporting the operating voltage for the SRAMs. Section V I of the paper states: “The test chip, shown in Fig. 19, is implemented in 40 nm CMOS technology and Manuscript received August 17, 2 014; accepted August 23, 2014. Date of publication September 16, 2014; date of current version October 24, 2014.
论文更正了SRAM工作电压的错误报告。
40nm CMOS, 0.5V to 0.9V, 25MHz to 98MHz
JSSC 2014第11期RF & WirelessEqualizer
Design Techniques for a Mixed-Signal I/Q 32-Coefficient Rx-Feedforward Equalizer, 100-Coefficient Decision Feedback Equalizer in an 8 Gb/s 60 GHz 65 nm LP CMOS Receiver
设计用于60 GHz基带的混合信号I/Q 32系数接收端前馈均衡器和100系数决策反馈均衡器
65 nm LP CMOS, 1.2V, 8Gb/s, 66mW
JSSC 2014第11期Power ManagementBoost ConverterEnergy Harvesting
Design of Transformer-Based Boost Converter for High Internal Resistance Energy Harvesting Sources With 21 mV Self-Startup V oltage and 74% Power Ef ficiency
提出一种改进型变压器升压转换器，解决高内阻能源启动问题。
21mV启动电压, 1.3μW启动功率, 2mW最大输出功率, 74%峰值效率
JSSC 2014第11期MemorySRAM
Design of a Temperature-Aware Low-V oltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C Tony
设计了一种适用于高温环境的低电压SRAM，采用温度感知的位线感应增强技术。
2V, 300°C, 0.94pJ
JSSC 2014第11期Other
INFORMATION FOR AUTHORS Content The IEEE Journal of Solid-State Circuits publishe s papers each month in the broad area of solid-state circuits with particular emphasis on transisto r-level design of inte-
IEEE JSSC期刊专注于集成电路设计，包括电路建模、技术、系统设计、布局和测试，鼓励实验验证。
无
JSSC 2014第11期RF & Wireless
Integrated Class-D Audio Ampli fier With 95% Efficiency and 105 dB SNR
集成超低EMI D类音频放大器，具有95%效率和105 dB SNR。
1.75 W, 8 Ohm, 105 dB SNR, 95%效率, 0.004% THD+N, 15.4 dB余量
JSSC 2014第11期Other
Introduction to the Special Section on the 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
2013年IEEE亚洲固态电路会议精选论文，聚焦移动计算新电路与系统。
无
JSSC 2014第11期Data ConvertersDelta-Sigma ADC
Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback
本文提出了一种低功耗单比特音频连续时间ΔΣ ADC设计技术，通过FIR反馈DAC实现高性能。
峰值A加权SNR 102.3 dB，无杂散动态范围106 dB，功耗280 µW，1.8 V电源
JSSC 2014第12期Image Sensors
A0 . 5 3T H zR e c o nfigurable Source Module With Up to 1 mW Radiated Power for Diffuse Illumination in Terahertz Imaging Applications Ullrich R. Pfeiffer , Senior Member , IEEE , Y
本文介绍了一种高功率0.53 THz可重构光源模块，适用于太赫兹成像应用。
总辐射功率1 mW，每像素平均功率62.5 µW，EIRP每像素25 dBm
JSSC 2014第12期RF & WirelessPipeline ADCNeural Network Accelerator
A1 4B i t1G S / sR FS a m p l i n gP i p e l i n e dA D C With Background Calibration Ahmed M. A. Ali , Member , IEEE, Huseyin Dinc
14位1GS/s RF采样流水线ADC，采用背景校准技术提升性能
65nm CMOS, 140MHz 2Vpp输入时SNR 69dB, SFDR 86dB, 功耗1.2W
JSSC 2014第12期Data ConvertersTime-Interleaved ADC
A6 9 . 5m W2 0G S / s6 bT i m e - I n t e r l e a v e dA D C With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI
32nm CMOS SOI工艺下实现的20GS/s 6位时间交织ADC，嵌入时间数字转换器校准时序偏差，功耗69.5mW。
20GS/s, 6bit, 30.7dB SNDR, 69.5mW, 124J/conv-step FoM
JSSC 2014第12期Power ManagementBuck Converter
A 10/30 MHz Fast Reference-Tracking Buck Converter With DDA-Based Type-III Compensator Lin Cheng, Student Member , IEEE, Y onggen Liu
提出一种10/30 MHz宽占空比范围的电压模式降压转换器，采用新型DDA型III补偿器和端点预测方案，实现快速参考跟踪响应。
0.13μm CMOS, 2.4V输出, 3.6W最大输出功率, 91.8%/86.6%峰值效率, 1.67μs/V和0.67μs/V上升跟踪速度
JSSC 2014第12期Data ConvertersSAR ADCNeural Network Accelerator
A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First
提出一种LSB优先的逐次逼近算法，实现10位SAR ADC，显著降低低活动信号采样时的能耗。
0.18μm CMOS, 0.6V, 16kHz, 9.73b ENOB, 3.5-20fJ/conversion-step FoM
JSSC 2014第12期RF & WirelessBoost Converter
A 1.1 nW Energy-Harvesting System with 544 pW Quiescent Power for Next-Generation Implants
一种用于下一代无线传感器的11nW能量收集系统，静态功耗仅544pW。
0.8-1.1V输出, 56%峰值转换效率, 1.1-6.25nW输入功率
JSSC 2014第12期RF & Wireless
A 1.2 nJ/bit 2.4 GHz Receiver With a Sliding-IF Phase-to-Digital Converter for Wireless Personal/Body Area Networks Y
提出一种超低功耗2.4GHz FSK/PSK接收机，采用滑动中频相位数字转换技术。
2.4 mW at 2 Mbps, 1.2 nJ/bit efficiency, -92 dBm sensitivity
JSSC 2014第12期RF & WirelessHigh-Speed Link
A 15–22 Gbps Serial Link in 28 nm CMOS With Direct DFE
28nm CMOS工艺下实现1522 Gbps半双工串行链路设计，支持20 dB损耗PCB信道。
28nm CMOS, 1.35V/0.9V, 20 Gbps, 6.5 mW/Gbps
JSSC 2014第12期Data ConvertersSAR ADC
A 1.5 mW 68 dB SNDR 80 Ms/s 2 Interleaved Pipelined SAR ADC in 28 nm CMOS Frank van der Goes, Christopher M. Ward, Santosh Ast gimath, Han Y an, Jeff Riley, Zeng Zeng, Jan Mulder
本文介绍了一种28nm CMOS工艺下80 MS/s、11位ENOB的低功耗ADC。
28nm CMOS, 80 MS/s, 11 bit ENOB, 1.5 mW
JSSC 2014第12期Data ConvertersDAC
A 160 Channel QAM Modulator With 4.6 Gsps 14 Bit DAC Daniel R. McMahill , Senior Member , IEEE, Dwaine S. Hurta, Brian Brandt ,S e n ior Member , IEEE
一款支持160通道QAM调制的46 Gsps 14位DAC，用于低功耗低成本电缆头端系统。
46 Gsps, 14 bit DAC, 动态范围高
JSSC 2014第12期RF & Wireless
A 16TX/16RX 60 GHz 802.11ad Chipset With Single Coaxial Interface and
一款支持802.11ad标准的60GHz射频芯片组，采用16发射16接收波束成形和极化多样性天线阵列，通过单同轴电缆接口实现低成本集成。
4.6 Gbps (PHY rate) at 10 m
JSSC 2014第12期RF & Wireless
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Ampli fier Using Timing Alignment Technique for WCDMA and LTE Kazuaki Oishi, Eiji Y oshida, Y asufumi Sakai, Hideki Ta kauchi, Y oichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Y amazaki, and
一款用于WCDMA和LTE手机的195 GHz全集成EER CMOS功率放大器
PAE 39%（WCDMA），32%（LTE）；ACLR -41 dBc（WCDMA），-33 dBc（LTE）
JSSC 2014第12期Data ConvertersSAR ADC
A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing
一款1 GS/s 10位189 mW时间交错SAR ADC，带背景时序偏差校准功能。
1 GS/s, 10位, 51.4 dB SNDR, 59.1 dB SFDR, 1.0 LSB INL/DNL, 18.9 mW, 62.3 fJ/step FoM
JSSC 2014第12期Power ManagementEqualizer
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS
28nm CMOS工艺下实现28 Gb/s多标准SerDes，功耗560 mW/通道。
28 Gbps, 560 mW/lane, 34 dB channel loss
JSSC 2014第12期Data ConvertersDACClock Generation
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS Taegeun Y oo, Student Member , IEEE , Hong Chang Y eoh , Member , IEEE, Y un-Hwan Jung
一款基于非线性DAC的2 GHz直接数字频率合成器，功耗130 mW，采用55 nm CMOS工艺。
2 GHz时钟频率，55.1 dBc SFDR，130 mW功耗，0.1 mm²面积
JSSC 2014第12期Clocking & PLLsEqualizer
A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS TawfiqM u s a h, Member , IEEE, James E. Jaussi , Member , IEEE
22nm CMOS技术下设计的8通道双向链路，支持32Gb/s每通道速率，功耗优化显著。
32Gb/s时功耗205mW@1.07V，8Gb/s时26mW@0.72V
JSSC 2014第12期RF & WirelessHigh-Speed Link
A 780 mW 4 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS Ullas Singh, Adesh Garg, Bharath Ragha van, Nick Huang, Heng Zhang, Zhi Huang
40纳米CMOS工艺下实现780mW功耗的4通道28Gb/s收发器，支持100GbE/40GbE标准。
28Gb/s, 0.9V, 780mW, 1.87ps抖动, 202fs抖动, 80MHz下0.46UI抖动容忍度, 27mV输入灵敏度
JSSC 2014第12期RF & Wireless
A 79 GHz Phase-Modulated 4 GHz-BW CW Radar Transmitter in 28 nm CMOS
28nm CMOS工艺下79GHz相位调制雷达发射器，带宽4GHz，输出功率11dBm。
28nm CMOS, 0.9V, 121mW, 10%效率, 11dBm输出功率
JSSC 2014第12期Data Converters
A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS Y
一款28 nm CMOS工艺的连续时间MASH ADC，实现88 dB动态范围和53 MHz带宽。
28nm CMOS, 0.9/1.8/-1.0V, 3.2GHz, 235mW
JSSC 2014第12期Clocking & PLLsPLLVCO
A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector Wei-Sung Chang, Po-Chun Huang, and Tai-Cheng Lee
提出一种采用子采样锁相环的无分频器低噪声分数N锁相环，实现2.3GHz输出频率下112dBc/Hz的低带内相位噪声。
0.18μm CMOS, 9.6mA, 239.1dB FoM, 266fs rms抖动
JSSC 2014第12期RF & Wireless
A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS Hui Pan, Y uan Y ao, Mostafa Hammad, Junhua Tan, Kar im Abdelhalim, Evelyn Wenting Wang, Rick C. J. Hsu
一种用于千兆以太网的全双工线路驱动器，采用轨到轨Class-AB输出，提高能效。
28 nm CMOS, 2.5 V/3.3 V电源
JSSC 2014第12期RF & Wireless
A Low-Power, Low-V oltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS
提出一种低功耗低电压WBAN兼容的PSK接收器，采用数字密集型架构，适用于传感器网络。
65nm CMOS, 0.6V, 1.3mW, 91dBm/96dBm灵敏度
JSSC 2014第12期Power ManagementNeural Network Accelerator
A Recursive Switched-Capacitor DC-DC Converter Achieving Ratios With High Ef ficiency Over a Wide Output V oltage Range Loai G. Salem , Student Member , IEEE, and Patrick P . Mercier , Member , IEEE
提出递归开关电容DC-DC转换器，实现高效率和宽输出范围。
0.8–2.2 V输出范围，85.8%峰值效率，2.5V输入
JSSC 2014第12期Clocking & PLLsVCOClock Generation
A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range Pei-Y uan Chiang, Student Member , IEEE, Zheng Wang , Student Member , IEEE
一款基于90nm SiGe BiCMOS工艺的300GHz频率合成器，采用三重推挽VCO和三相位注入分频器，实现宽锁定范围和低相位噪声。
相位噪声-77.8dBc/Hz@100kHz(-82.5dBc/Hz@1MHz), 锁定范围280.32-303.36GHz(7.9%)
JSSC 2014第12期RF & WirelessTransceiver
A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications
一种采用功能复用和增益提升N路径技术的多ISM频段ZigBee接收器
8.1±0.6dB NF, 50±2dB增益, -20.5±1.5dBm带外IIP3, 1.15±0.05mW功耗@0.5V
JSSC 2014第12期Power ManagementEnergy HarvestingNeural Network Accelerator
An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor V oltage Doubler Wanyeong Jung, Student Member , IEEE , Sechang Oh , Student Member , IEEE , Suyoung Bang, Student Member , IEEE , Y
提出一种基于自振荡开关电容的完全集成能量收集器，在低光条件下实现高效能量转换。
0.18µm CMOS, 250mV-4V, 7nW输入, 5nW-5µW输出, 35%端到端效率
JSSC 2014第12期Wireline I/OEqualizerNeural Network Accelerator
Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS
提出一种用于10 Gb/s的功率可扩展连续时间FIR均衡器，适用于多模光纤链路中的色散补偿。
28nm LP CMOS, 10-25 Gb/s, 55-90 mW
JSSC 2014第12期Digital CircuitsNeural Network Accelerator
CMOS Impedance Analyzer for Nanosamples Investigation Operating up to 150 MHz With Sub-aF Resolution Davide Bianchi, Student Member , IEEE
提出一种新型CMOS阻抗分析器，用于纳米样品研究，工作频率高达150 MHz。
0.35 µm CMOS, 1 kHz–150 MHz, 0.4 aF分辨率
JSSC 2014第12期RF & WirelessNeural Network Accelerator
Channel Selection at RF Using Miller
利用米勒带通滤波器实现射频接收器的信道选择，显著降低线性要求，实现低功耗紧凑设计。
65nm CMOS, 噪声系数2.9dB/5.1dB, 带宽350kHz-20MHz
JSSC 2014第12期Other
Digital Object Identi fier 10.1109/JSSC.2014.2372639
无摘要提供，无法生成概要。
无
JSSC 2014第12期Other
INFORMATION FOR AUTHORS Content The IEEE Journal of Solid-State Circuits publishe s papers each month in the broad area of solid-state circuits with particular emphasis on transisto r-level design of inte-
IEEE JSSC期刊专注于集成电路与VLSI设计，鼓励实验验证，强调原创性和未发表性。
无
JSSC 2014第12期RF & Wireless
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC)
2014年IEEE国际固态电路会议精选论文特刊，涵盖模拟、数据转换器、RF、无线和有线通信等领域的最新创新。
0.35μm CMOS, 1 kHz–150 MHz, 0.4 aF分辨率
JSSC 2014第12期RF & Wireless
Low-Noise Active Cancellation of Transmitter Leakage and Transmitter Noise in Broadband Wireless Receivers for FDD/Co-Existence
提出一种宽带接收机中主动消除发射机泄漏和噪声的技术，显著提升接收机性能。
0.3–1.7 GHz接收机，+2 dBm峰值TX泄漏消除，68 dB三阶互调，+33 dBm有效IIP3，NF增加<0.8 dB
JSSC 2014第12期RF & Wireless
Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier
提出一种天线负载阻抗检测与自动调谐技术，提升3G/4G效率。
VSWR约2.5时，峰值PAE保持在40%以上；VSWR约6时，损耗0.3-4.6dB
JSSC 2014第12期Analog Circuits
Switched-Mode Operational Ampli fiers and Their Application to Continuous-Time Filters in Nanoscale CMOS
提出新型开关模式运算放大器(SMOA)，在65nm CMOS中实现高效低电压连续时间滤波器
65nm CMOS, 0.6V供电, 70MHz带宽, 25.4mW功耗, 55.8dB SNDR