JSSC 年份

2024

331 篇期刊论文

JSSC 2024第1期Wireline I/O
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%–99.99% Error Coverage in Intel 4 CMOS
一款抗故障注入攻击的AES-256加密引擎，采用Intel 4 CMOS工艺，实现100Gbps吞吐量和99.1%错误覆盖率。
Intel 4 CMOS, 100Gbps, 99.1% error coverage, 13,400× laser injection margin
JSSC 2024第1期RF & WirelessHigh-Speed LinkEqualizer
A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology
一款支持112 Gb/s的多标准串行链路收发器，采用7nm FinFET工艺，功耗和面积效率高。
112 Gb/s, 43.9-dB IL补偿, 690-mW功耗, 0.63-mm²面积
JSSC 2024第1期Other
A 1.5-µW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive
提出了一种28nm CMOS工艺的低功耗关键词检测SoC，采用跳帧RNN算法实现动态功耗优化。
28nm CMOS, 1.48 µW, 92.8% accuracy
JSSC 2024第1期Data Converters
A 3.58 nJ/Node Dual Cross Correlation Analog-Front-End Circuit With ADC for Mutual
提出一种用于互容面板的双互相关模拟前端电路，降低功耗和面积，提高ADC精度。
110nm CMOS, 12-bit SAR-VCO ADC, 3.58 nJ/node, 0.988 mm², 46.1/50.2 dB SNR
JSSC 2024第1期Other
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ
4纳米工艺HBM3接口，采用电阻调谐偏移校准和原位余量检测技术，实现9.0 Gb/s/pin高速访问。
4nm FinFET, 0.66/0.30V, 9.0 Gb/s/pin, 0.29 pJ/bit
JSSC 2024第1期RF & WirelessPAM-4
A 4-nm 16-Gbspin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter C
4纳米CMOS工艺下16Gbps单端PAM-4收发器，采用切换抖动补偿技术提升时序裕度
16-Gb/s/pin, 0.764-pJ/b
JSSC 2024第1期Analog Circuits
A 9-Mb HZO-Based Embedded FeRAM With 1012-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier Qiqiao Wu , Student Member , IEEE, Yue Cao
提出一种基于HZO的9Mb嵌入式FeRAM，具有高耐久性和快速读写性能。
2×剩余极化>30 µC/cm², >1012次耐久性, 7ns写入和5ns读取时间, <3V工作电压, 85℃下10年数据保持
JSSC 2024第1期RF & WirelessEqualizer
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS
28nm CMOS工艺下实现200Gb/s有线接收机的五抽头延迟线前馈均衡器
200Gb/s, 17.2dB损耗通道均衡, 0.42pJ/b能效
JSSC 2024第1期MemorySRAM
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI
提出一种混合域结构的浮点6T SRAM内存计算宏，实现高能效和高精度
72.14 TFLOPS/W (BF16输入/权重, FP32输出, 128次累加)
JSSC 2024第1期MemorySRAMEmerging Memory
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and
提出一种异构RRAM内存计算和SRAM近内存计算的SoC，用于融合帧和事件视觉处理。
40nm TSMC ULP工艺
JSSC 2024第1期Other
A High-Efficiency High-Power 170–176-GHz Frequency Stabilized
本文提出了一种高效高功率的170-176GHz频率稳定正交辐射器，适用于短相干时间成像和无线通信应用。
170-176GHz, +24.6 dBm EIRP, 9.2% dc-to-RF efficiency
JSSC 2024第1期Clocking & PLLsVCO
A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer Ziyi Lin
提出一种采用三线圈变压器的低相位噪声VCO，具有共模谐振扩展和本征差分二次谐波输出。
12.3-15.2 GHz, -118.0 dBc/Hz @1MHz, 8.4-9.6 mW, 0.06 mm2
JSSC 2024第1期MemoryCIM
A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–V oltage-Hybrid Readout Scheme Hung-Hsi Hsu
提出一种采用混合模式ReRAM的非易失性AI边缘处理器，解决能效与计算延迟问题。
22nm工艺, 51.4 TOPS/W, 472.7µs唤醒响应时间, 67.2 TOPS/W（8位输入/8位权重/22-24位输出）
JSSC 2024第1期MemoryEmerging MemoryNeural Network Accelerator
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices
提出一种基于STT-MRAM的8位精度近存计算宏，采用系统-电路协同设计解决能效和延迟问题。
22nm STT-MRAM, 436GB/s读取带宽, 20ns计算延迟, 53.6-190.2 TOPS/W能效
JSSC 2024第1期Clocking & PLLsPLLVCO
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
提出一种基于耦合锁相环技术的CMOS正交压控振荡器新架构，优化相位噪声和正交误差。
28nm CMOS, 24-29.2GHz, -134dBc/Hz@10MHz, 0.9°正交误差, 60mW, -184dBc/Hz FoM
JSSC 2024第1期Data Converters
Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining
宽带连续时间流水线ADC设计与分析，采用热噪声估计数字重构滤波器抽头，实现高效能转换。
65nm CMOS, 1.2V, 800MS/s, 12.5-bit, 59mW
JSSC 2024第1期Digital Circuits
C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN
提出一种结合CNN和SNN的互补DNN处理器，实现高效能推理与训练。
85.8 TOPS/W (CIFAR-10), 79.9 TOPS/W (CIFAR-100)
JSSC 2024第1期OtherEqualizer
CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of
提出一种基于锁存器的连续时间伊辛机，用于高效解决组合优化问题。
0.656 × 0.680 mm², 40 × 36 自旋阵列
JSSC 2024第1期MemoryDRAM
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell
DynaPlasia是一种基于eDRAM内存计算的可重构空间加速器，通过动态可重构核心架构和新型三模式单元提升能效和面积效率。
28nm CMOS, 20.25mm² die area, 9.6Mb cell capacity, 19.5 TOPS peak throughput, 56.0 TOPS/W peak efficiency
JSSC 2024第1期Clocking & PLLsDLLEqualizer
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration
提出一种采用DTC控制注入时序的分数N数字MDLL，通过注入误差扰乱和校准技术降低杂散。
800-fs rms抖动, -67dBc分数杂散, -58dBc参考杂散
JSSC 2024第1期Other
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)
2023年IEEE ISSCC会议精选论文特辑，涵盖有线/无线电路、数字电路技术、机器学习加速器等前沿领域。
无
JSSC 2024第1期Power Management
MARSELLUS : A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive
MARSELLUS是一款异构RISC-V AI-IoT终端SoC，支持DNN加速与高能效计算。
180 Gop/s软件算力，637 Gop/s硬件加速，12.4 Top/s/W能效
JSSC 2024第1期Digital Circuits
MetaVRain A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-
MetaVRain是一款面向移动设备的低功耗神经3D渲染处理器，采用仿生视觉感知架构解决NeRF渲染的高运算强度问题。
未明确提及（需补充具体数据如功耗/算力指标）
JSSC 2024第1期MemoryCIM
MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit
MulTCIM是一种基于数字内存计算的Transformer加速器，通过混合稀疏性优化能效。
2.24 µJ/Token, 2.50×–5.91×能效提升
JSSC 2024第1期Digital Circuits
Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and
提出一种支持任意量化的深度学习加速器，具有高效能和多格式数据处理能力。
28nm LP CMOS, 1-8 bit, 30% sparsity, 0.87-5.55 TOPS, 15.1-95.9 TOPS/W
JSSC 2024第1期Other
New Associate Editor I
IEEE JSSC期刊新增副编辑徐洪涛教授，专注于模拟、射频及毫米波电路与无线系统研究。
无
JSSC 2024第1期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊论文分析
无关键性能指标
JSSC 2024第1期Analog Circuits
Thin-Film Transistor-Based Sensor Interface Circuits Enabling Distributed Local In-Module Solar Cell Temperature Monitoring Seyed Mojtaba Sadati Faramarzi , Student Member , IEEE, Bin Luo, Student Member , IEEE
薄膜晶体管传感器接口电路实现分布式太阳能模块监测
无
JSSC 2024第2期MemorySRAM
A 0.05-mm 2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS Fei Tan , Student Member , IEEE
一款低功耗、高精度的关键词识别芯片，采用28nm CMOS工艺，实现2.91µW功耗和90%准确率。
28nm CMOS, 2.91µW, 2.91nJ/decision, 2ms/decision, 0.05mm² core area
JSSC 2024第2期Other
A 039-mm 2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution C
本文提出了一种基于电荷重分配的高效CMOS湿度传感器，具有低误差和高性能。
55nm CMOS, 9.57 µW, ±0.8%RH误差, 197 aF电容分辨率, 0.094%RH湿度分辨率
JSSC 2024第2期Clocking & PLLsCrystal Oscillator
A 12-/13.56-MHz Crystal Oscillator With Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8- µs
一种采用二分搜索辅助两步注入技术的12/13.56MHz晶体振荡器，实现快速低能耗启动。
0.7V, 45.8µs启动时间, 5.0nJ能耗, 28.4µW稳态功耗, -143.7dBc/Hz@1kHz相位噪声
JSSC 2024第2期Clocking & PLLsPLL
A 12.8–15.0-GHz Low-Jitter Fractional- N Subsampling PLL Using a V oltage-Domain Quantization-Error Cancellation
提出一种低抖动、低分数杂散的分数-N子采样锁相环，采用DAC后消除量化误差技术
65nm CMOS, 7.3mW, 104fs rms抖动, -58dBc分数杂散
JSSC 2024第2期Memory
A 134 × 132 4-Tap CMOS Indirect Time-of-Flight Range Imager Using In-Pixel Memory Array With 10 Kfps High-Speed Mode and High Precision Mode Chia-Chi Kuo , Student Member , IEEE
本文介绍了一种高速4抽头间接飞行时间CMOS成像器，具有高精度和高速深度成像能力。
22.4 H × 16V µm像素尺寸，134 H × 132V 4抽头像素阵列，<1.82%深度噪声（高速模式），<1.77%深度噪声（高精度模式）
JSSC 2024第2期Digital CircuitsNeural Network AcceleratorBiosignal
A 136-G Input-Impedance Active Electrode for Non-Contact Biopotential
一种136GΩ输入阻抗的有源电极电路，用于非接触式生物电位信号检测。
136GΩ@60Hz, 19.5fF, 700mVpp, 0.72µVrms, 10.46µW@1.2V
JSSC 2024第2期Other
A 144-Element Beam-Steerable Source Array With 9.1-dBm Radiated Power and 30.8-dBm Lensless EIPR at 675 GHz
144单元可波束转向太赫兹源阵列，输出功率9.1dBm，频率675GHz。
675GHz, 9.1-dBm辐射功率, 30.8-dBm无透镜EIRP, -90.9dBc/Hz相位噪声, 0.245%效率
JSSC 2024第2期Data ConvertersSAR ADCNeural Network Accelerator
A 15.4-ENOB, Fourth-Order Truncation-Error- Shaping NS-SAR-Nested 16 Modulator With Boosted Input Impedance and Range for
一种高输入阻抗、宽线性输入范围的16调制器，用于生物医学信号采集。
94.5-dB SNDR, 1–500-Hz带宽, 600-mV PP输入, 174.3 dB FoM SNDR, 175.8 dB FoM DR, 208 MΩ@dc输入阻抗
JSSC 2024第2期Other
A 46.6 µg/√Hz Single-Chip Accelerometer Exploiting a DTC-Assisted
一款采用DTC辅助斩波放大器的单芯片加速度计，实现超低噪声和偏置不稳定性。
46.6 µg/√Hz热噪声, 472 µg偏置不稳定性, >1000 g满量程
JSSC 2024第2期RF & Wireless
A 4.9–7.1-GHz High-Efficiency Post-Matching GaN Front-End Module for Wi-Fi 7 Application
提出一种改进的GaN前端模块架构，提升Wi-Fi 7应用的发射效率。
4.9–7.1 GHz, 37.1–38.6 dBm, 45%–52.4% PAE
JSSC 2024第2期RF & WirelessCDRPAM-4
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
一款60Gbs PAM-4接收器，采用抖动补偿CDR技术，实现低抖动传输与高带宽容忍。
40nm CMOS, 30-60Gb/s, <-8dB JTRAN, 40MHz JTOL带宽, 60%抖动补偿率
JSSC 2024第2期Power ManagementBuck Converter
A Dual-Inductor Ladder Buck Converter for Li-Ion Battery-Operated Sub-V olt SoCs
提出一种双电感阶梯式降压转换器，用于锂离子电池供电的亚伏SoC，实现高效高功率密度。
65nm CMOS, 90.6%峰值效率, 0.93W/mm²峰值功率密度, 1.35W最大功率输出
JSSC 2024第2期Power ManagementLDONeural Network Accelerator
A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 05-V
提出一种四相时间开关电容LDO，具有13ns快速响应和低静态电流。
28nm CMOS, 0.45-1V输入, 0.35-0.95V输出, 400mA负载, 3.0fs FoM
JSSC 2024第2期RF & WirelessPower Amplifier
A Fully Integrated Digital Polar Transmitter With Single-Ended Doherty PA and DL
本文提出了一种集成数字极性发射器，采用单端多尔蒂功率放大器和数字时间转换器，显著提高了功率附加效率。
28nm CMOS, 2.1GHz, 峰值输出功率27.7dBm, 峰值PAE 33.4%
JSSC 2024第2期RF & Wireless
A Low-Power Radiation-Hardened K a-Band CMOS Phased-Array Receiver for Small
一种用于小型卫星通信的低功耗抗辐射K a波段CMOS相控阵接收器
3.4mW功耗，-22dBm IIP3，3.8dB噪声系数，0.2mm²芯片面积
JSSC 2024第2期Clocking & PLLs
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-V oltage Multivoltage/ Frequency-Domain Network-on-Chip
提出一种预测和缓解时钟域交叉中亚稳态风险的技术MPAM，显著提升NoC的可靠性和性能。
40nm LP工艺, 亚稳态条件率降低10^10倍, 延迟降低58%, 吞吐量提升13.4%, 能效提升8.6%
JSSC 2024第2期OtherPhased Array
A Pitch-Matched High-Frame-Rate Ultrasound Imaging ASIC for Catheter-Based 3-D P
一种用于导管式3D超声成像的ASIC，实现高帧率和小型化设计。
TSMC 0.18-µm HV BCD, 30V TX, 1.12 mW/element RX
JSSC 2024第2期OtherBoost ConverterEnergy Harvesting
A Quad-Mode Structure-Reconfigurable Regulating Rectifier With Shared-Inductor D
提出一种四模式结构可重构调节整流器，结合交流-直流调节整流器和直流-直流升压转换器于单级，提高无线能量传输效率。
5V输出电压，3.7V存储电压，91.8%峰值接收效率，64.7%系统效率
JSSC 2024第2期RF & Wireless
An Interference-Resilient Bit-Level Duty-Cycled ULP Receiver Leveraging a Dual-C
提出一种抗干扰超低功耗接收器，适用于430MHz ISM频段的物联网应用。
28nm CMOS, 2.5kb/s, 110µW, -103dBm灵敏度
JSSC 2024第2期Power ManagementLDO
An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-µs Short-Period
一种采用TM-MOS和动态钳位技术的NMOS LDO，适用于手机应用中的高频负载瞬态。
0.35-µm CMOS, 1-µF输出电容, 0-300mA负载, 50/36mV低频瞬态下冲/过冲, 68/36mV高频瞬态下冲/过冲, 8.2-µA静态电流, 99.68%电流效率
JSSC 2024第2期MemorySRAMNeural Network Accelerator
An SRAM-Based Reconfigurable Cognitive Computation Matrix for Sensor Edge Applications Sheng-Yu Peng
提出了一种适用于传感器边缘应用的SRAM可重构认知计算矩阵，支持多象限乘法和多种激活函数。
0.18-µm CMOS, 3.355 TOPS/W
JSSC 2024第2期OtherDLL
An Ultrasonic Driver Array in Metal-Oxide Thin-Film Technology Using a Hybrid TF
本文提出了一种基于IGZO薄膜晶体管技术的24V高压超声波驱动器，用于触觉反馈，采用新型混合硅/IGZO DLL架构。
36 pF, 3.54 bit相位分辨率, 250 kHz, 800 × 800 µm
JSSC 2024第2期Data ConvertersEmerging MemoryNeural Network Accelerator
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip Junjie Wang , Teng Zhang, Shuang Liu , Yihe Liu, Yuancong Wu
设计并实现了一种基于180nm CMOS技术的1Mb RRAM存内计算芯片，采用时间分复用电路和稀疏感知技术，免除了DAC和ADC需求。
180nm CMOS, 13.32 Mb/mm2 (22nm节点归一化), 17.36 TOPS/W (INT4)
JSSC 2024第2期RF & WirelessPower Amplifier
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SO
22nm FD-SOI工艺下高效宽带毫米波收发前端，适用于5G基站。
18.3dBm饱和输出功率, 15.9dBm 1dB压缩点, 5.8%功率附加效率
JSSC 2024第2期Power Management
Highly Efficient Differential Frequency Doubler With Output Resistance Boosting Feedback
采用互补MOS晶体管的V波段高效差分倍频器和D波段四倍频器设计
15.3% CE/3.5dBm输出功率（倍频器），4.7% CE/1.3dBm输出功率（四倍频器）
JSSC 2024第2期Other
New Associate Editor I
Priyanka Raina成为IEEE JSSC新副编辑，专注于特定领域加速器架构与电路研究。
无
JSSC 2024第2期OtherBandgap Reference
Sub-µW Auto-Calibration Bandgap V oltage Reference With 1 σ Inaccuracy of ±0.12% Within −40 ◦C to 120 ◦C Chi-Wa U
提出一种基于电流的带隙电压参考自动校准技术，降低校准成本并提高精度。
22.3 ppm/°C, 1.26 mV/V, ±0.12%
JSSC 2024第2期Clocking & PLLs
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-V oltage Bitcoin
TICA技术通过动态感知PVT变化并调整时钟频率，减少超低电压电路中冗余时序裕度。
28nm CMOS, 0.59%原位检测器插入率, 1.4%面积开销
JSSC 2024第2期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
本文介绍了IEEE固态电路期刊的出版信息及相关组织架构。
无
JSSC 2024第3期Other
A 0.61- µW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN
提出一种全集成近麦克风关键词检测芯片，功耗低至0.61 µW，适用于物联网设备。
28nm CMOS, 0.36V NN, 0.9V AFE, 8KHz
JSSC 2024第3期OtherNeural Network Accelerator
A 14–32 GHz SiGe-BiCMOS Gilbert-Cell Frequency Doubler With Self-Adjusted Reduced Duty-Cycle
提出一种新型基于混频器的频率倍增器，通过自调节减少开关四极管占空比，实现宽带高效频率倍增。
1.5V电源电压，6dB转换增益，5.7dBm Psat，17%效率，14-32GHz带宽
JSSC 2024第3期RF & Wireless
A 1.54-mm 2, 264-GHz Wake-Up Receiver With Integrated Cryptographic Authentication for Ultra-Miniaturized Platforms
首款亚太赫兹唤醒接收器，集成加密认证功能，适用于超小型物联网平台
264GHz频段, 1.54mm²面积, -48dBm灵敏度, 2.9μW功耗
JSSC 2024第3期MemoryCIM
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed D
提出一种无需校准的4位电流编程存内计算宏，采用3T1C eDRAM单元，提升能效和精度。
65nm CMOS, 233-304 TOPS/W, 0.4ms刷新间隔, CIFAR10 >90%推理准确率
JSSC 2024第3期Data ConvertersPipeline ADC
A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware
提出一种PVT鲁棒的环形放大器，实现高速无增益校准的12位250 MS/s流水线ADC。
65nm CMOS, 12-bit, 250 MS/s, SNDR > 57.7 dB
JSSC 2024第3期RF & WirelessLNA
A 5273-GHz LNA With Tri-Coupled Transformer for Gm Boosting and Enhanced Noise C
基于三耦合变压器的宽带低噪声放大器，实现增益提升和噪声抵消。
40nm CMOS, 3.8dB NF, 22.4dB增益, 22.1GHz带宽, 34mW功耗
JSSC 2024第3期Power Management
A 63% Efficiency 1.29-W Single-Link Multiple-Output (SLiMO) Isolated DC–DC Converter Using FPC Micro-Transformer With Local V oltage and Global
一种小型单链路多输出隔离DC-DC转换器设计，采用微变压器和双控制方案，实现高效能和高功率密度。
0.18-µm CMOS, 3.3-V IO, 63%峰值效率, 1.29-W最大输出功率
JSSC 2024第3期Other
A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques
提出一种72通道电阻电容传感器接口芯片，采用噪声正交化和焊盘共享技术，实现高效低功耗传感。
65nm CMOS, 0.74 µW/Channel, 0.038 mm²/Channel, 286 Ω, 162 fF
JSSC 2024第3期Data ConvertersNeural Network Accelerator
A 7 GHz ERBW 1.1 GS/s 6-bit PVT Tolerant Asynchronous Charge-Injection SAR With Only 8.5 fF Input Capacitance in 28 nm CMOS
一款6位1.1GS/s异步电荷注入SAR ADC，具有7GHz ERBW和PVT容差能力。
28nm CMOS, 0.9-1.1V, 1.1GS/s, 35.2dB SNDR, 25.5fJ/conv.-step
JSSC 2024第3期Other
A 9-V-Tolerant Stacked-Switched-Capacitor Stimulation System With Level-Adaptive Switch Control and Rapid Stimulus-Synchronized Charge Balancing for
提出一种无需外部高压电源的9V耐压堆叠开关电容刺激系统，采用自适应开关控制实现高效刺激。
71.4%刺激效率（充电效率72.6%，放电效率99.9%），1μF电容0-4V充电，残余电压抑制至±30mV
JSSC 2024第3期Clocking & PLLs
A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain
提出一种无需DTC的分数N BBPLL，采用FIR嵌入式注入锁定振荡器降低量化噪声。
65nm CMOS, 0.9V, 4.3mW, 2.6GHz输出
JSSC 2024第3期RF & Wireless
A Frequency-Division Transceiver for Long-Range Neural Signal Recording From
提出一种用于长距离多点多通道神经信号记录的频分收发器SoC，显著降低功耗。
4.18 mW功耗, 16通道神经信号记录, -5 dBm发射功率, -91 dB接收灵敏度, 8米工作距离
JSSC 2024第3期RF & WirelessDAC
A Fully Integrated 135-GHz Direct-Digital 16-QAM Wireless and Dielectric Waveguide Link in 28-nm CMOS Carl D’heer
本文介绍了一种135 GHz全集成直接数字16-QAM通信链路。
28nm CMOS, 32 Gb/s无线信道, 24 Gb/s介质波导信道, 9 pJ/b能效
JSSC 2024第3期Other
A GaN-on-Si Gate Driver With Self-Pumped Drive Enhance and Short-Period Negative V oltage Techniques for Reduction of 14.7 × Tailing Power Loss and 37% Reverse Conduction Loss Hsing-Yen Tsai
提出一种具有自泵驱动增强和短周期负电压技术的GaN-on-Si栅极驱动器，显著降低损耗并提升效率。
14.7×尾部电流损耗降低，37.0%反向导通损耗减少
JSSC 2024第3期Digital CircuitsNeural Network Accelerator
A Li-Ion Battery Input Highly Integrated LED Driver With 96.8% Peak Efficiency and Dual-Color
一款高效集成的锂离子电池供电LED驱动器，峰值效率达96.8%，支持双色混合调光。
0.18-µm BCD, 2.7–4.2V, 270-550mA, 96.8% peak efficiency
JSSC 2024第3期mm-Wave
A Low-Power, Wide-Bandwidth, Three-Axis MEMS Accelerometer ASIC Using Beyond-Resonant-Frequency Sensing
首款采用超谐振频率传感技术的三轴MEMS加速度计ASIC，扩展带宽至4kHz和8kHz。
4kHz, 25µg/√Hz, ±8g, 375µA; 8kHz, 59µg/√Hz, ±30g, 550µA
JSSC 2024第3期Clocking & PLLsCharge PumpPLL
A Sub-50-fsrms Jitter Fractional- N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity
提出了一种基于双DTC辅助时间放大PFD的24-28GHz亚50fs抖动分数N CPPLL。
37.1 fs rms jitter (integer-N), 45.6 fs rms jitter (fractional-N)
JSSC 2024第3期Other
A Thin Elastic NFC Forum Type 1 Compatible RFID
提出一种基于IGZO工艺的柔性NFC Type-1兼容RFID标签，实现智能包装应用。
IGZO工艺，NFC Type-1兼容，完全射频场供电
JSSC 2024第3期Data ConvertersDAC
A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology Daniel Widmann , Tobias Tannert , Xuan-Quang Du, Thomas Veigel , Markus Grözing
首次在28nm FD-SOI CMOS技术中集成双子DAC和主动模拟多路复用器，实现118 GS/s的高采样率。
28nm CMOS, 118 GS/s, 4W@100GS/s
JSSC 2024第3期Other
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense
Amber是一款16nm SoC，集成粗粒度可重构阵列，用于加速密集线性代数应用。
538 INT16 GOPS/W, 483 BFloat16 GFLOPS/W
JSSC 2024第3期Data ConvertersSAR ADC
An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing E
基于全电流处理的面积高效智能温度传感器设计
180nm CMOS, 1.8V, 34µA, 0.057mm², 92mK分辨率
JSSC 2024第3期Data ConvertersSAR ADCDelta-Sigma ADC
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R
提出一种无额外环路延迟补偿的20MHz带宽四阶连续时间ΣΔ调制器，采用二阶噪声整形CT-SAR ADC技术。
28nm CMOS, 1.5-1V, 750MHz采样频率, 20MHz带宽, 75.5dB SNDR, 2.78mW功耗
JSSC 2024第3期MemorySRAM
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm Chuan-Tung Lin
提出一种新型数字内存计算宏DIMCA，通过近似算术提高面积效率，同时保持计算密度。
327 kb/mm², 458–990 TOPS/W, 8.27–392 TOPS/mm², 90.41% accuracy for CIFAR-10
JSSC 2024第3期Digital Circuits
EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning
EPU是首个专为可解释AI设计的硬件加速器，提升系统性能并减少内存占用。
无
JSSC 2024第3期Digital Circuits
FreFlex: A High-Performance Processor for Convolution and Attention Computations via Sparsity-Adaptive Dynamic Frequency
FreFlex处理器通过稀疏自适应动态频率调制和二维脉动阵列提升卷积和注意力计算的能效和性能。
160 GOPS/s/mm², 1.1 GHz, 0.6–1.0 TOPS/W
JSSC 2024第3期Other
Guest Editorial 2023 Custom Integrated Circuits Conference T HIS Special Issue o
2023年CICC会议精选论文特刊，涵盖RF、毫米波、硅光子等多个IC设计领域。
无
JSSC 2024第3期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE固态电路期刊的编辑和委员会成员信息
无
JSSC 2024第4期RF & Wireless
A 0190-pJbit 252-Gbswire Inverter-Based AC-Coupled Transceiver for Short-Reach D
提出一种基于反相器的短距离交流耦合收发器，用于硅中介层通信。
5nm CMOS, 0.75V, 25.2 Gb/s/wire, 0.190 pJ/bit
JSSC 2024第4期Image SensorsNeural Interface
A 1024-Channel 268-nW/Pixel 36 × 36 µm2/ Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain–Computer Interfaces
一种1024通道数据压缩神经记录芯片，用于高带宽脑机接口。
1024-Channel, 268-nW/Pixel, 36×36 µm² Channel
JSSC 2024第4期Data Converters
A 120-MHz BW, 122-dBFS SFDR CT 16 ADC With a Multi-Path Multi-Frequency
提出多路径多频率斩波技术，抑制1/f噪声，实现120MHz带宽下122dBFS SFDR的高性能CT 16 ADC。
6GHz采样率，120MHz带宽，122dBFS SFDR，-98.3dBc THD
JSSC 2024第4期Data ConvertersDACNeural Network Accelerator
A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators
一种高效能电平交叉ADC，适用于稀疏信号数字化，采用动态自偏置比较器和新型DAC架构。
65nm CMOS, 64dB SNDR, 20kHz带宽, 1.8fJ/conv.-step
JSSC 2024第4期Other
A 187-dB FoM S Power-Efficient Second-Order Highpass 16 Capacitance-to-Digital C
提出一种高分辨率能效高的二阶高通16位电容数字转换器架构。
5.85 aF rms分辨率, 46 fJ/转换步, FoMS 187.4 dB
JSSC 2024第4期MemoryEmerging Memory
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 59-ns Random Read Access and 74-
22纳米32Mb嵌入式STT-MRAM宏，实现59ns随机读取和74%写入能耗降低。
22nm CMOS, 59ns随机读取, 7.4MB/s写入吞吐量
JSSC 2024第4期RF & Wireless
A 2.4-GHz Full-Duplex Transceiver With Broadband, Linearity-Enhanced, and Long-Delay Spread Self-Interference Cancellation
一款24GHz全双工收发器，采用多种自干扰消除技术，支持宽带线性增强和长延迟扩展。
62dB自干扰抑制（120MHz带宽，0-0.28ns延迟扩展），23dB自干扰消除（120MHz带宽，0.4-174ns延迟扩展）
JSSC 2024第4期MemorySRAM
A 3-nm FinFET 276-Mbitmm 2 Single-Port 6T SRAM Enabling 04812 V Wide Operating R
提出一种3nm FinFET 6T SRAM宏，采用远端预充电和弱位跟踪电路，提升读写速度并扩展工作电压范围。
0.48-1.2V宽电压工作，1.9GHz@0.75V，27.6Mbit/mm²密度
JSSC 2024第4期Image SensorsCMOS Image Sensor
A 336-µm-Pitch SPAD Photon-Counting Image Sensor Using a Clustered Multi-Cycle C
提出一种3.36微米像素间距的单光子计数图像传感器，实现120dB高动态范围和150帧/秒成像。
120dB动态范围, 150帧/秒, 748×448像素, 104mW功耗
JSSC 2024第4期MemorySRAM
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology Jeongkyun Kim , Byungho Yook, Youngo Lee , Taemin Choi, Kyuwon Choi, Chanho Lee, Juchang Lee, Hyeongcheol Kim, Seok Yun, Changhoon Do
4nm FinFET工艺下4.13GHz超高速伪双端口SRAM，采用BL充电时间减少和飞行字线架构。
4.13 GHz, 0.85 V, 100°C
JSSC 2024第4期Data ConvertersPipeline ADCDAC
A 64-GSs 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DA
提出一种采用时间交织子ADC-DAC路径的连续时间流水线ADC，提升带宽和信号消除性能。
16nm FinFET, 64GS/s, 1GHz带宽, 61.7dB SNR, 240mW功耗, 0.77mm²面积
JSSC 2024第4期Data ConvertersDAC
A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-
一种采用多级级联10位DAC和真直流技术的面积高效显示源驱动IC
180nm CMOS, 1.8/5V, 最大DNL -0.37 LSB, 最大INL 1.17 LSB, 最大DVO 15.5mV
JSSC 2024第4期OtherDelta-Sigma ADC
A Highly Digital 143.2-dB DR Sub-1 ◦ Phase Error Impedance Monitoring IC With Pulsewidth
一款高动态范围、低相位误差的数字阻抗监测芯片
143.2 dB动态范围, 0.675°相位误差, 310.9 µW功耗, 1.2V供电
JSSC 2024第4期RF & WirelessEqualizer
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for
提出一种18Gb/s单端接收器，结合增益增强型有源电感CTLE和参考选择DFE，优化单端内存接口性能。
18Gb/s, -15dB信道损耗补偿, 0.14pJ/bit能效, 0.009pJ/bit/dB FoM
JSSC 2024第4期RF & Wireless
A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO
首款亚太赫兹全双工相控阵收发器，集成自干扰消除技术，实现高速数据传输。
88–136 GHz, >60 dB SI suppression, 6 Gb/s (8PSK), 4 Gb/s (16QAM), 112 Gb/s (TX-to-RX)
JSSC 2024第4期RF & Wireless
A Sub-mm 3 Wireless Neural Stimulator IC for
提出一种用于视觉皮层刺激的无束缚、自由浮动且可单独寻址的无线神经刺激器IC。
无具体性能指标数据
JSSC 2024第4期RF & WirelessPower AmplifierNeural Network Accelerator
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter
提出一种基于1位ΔΣ调制和时间模式调制的数字正交功率放大器，实现高功率回退效率。
65nm CMOS, 2.6GHz, 26.4% PAE@64-QAM 40MSymbol/s, 20.9% PAE@256-QAM 20MSymbol/s
JSSC 2024第4期RF & WirelessNeural Interface
A Wireless Sensor-Brain Interface System for Tracking and Guiding Animal Behaviors Through Closed-Loop Neuromodulation in
一种用于闭环神经调控的无线传感器-脑接口系统，通过神经刺激引导大鼠在水迷宫中导航。
180-nm CMOS, 无线通信, 闭环神经调控
JSSC 2024第4期Clocking & PLLsSAR ADCDelta-Sigma ADC
An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer Hsiang-Wen Chen , Student Member , IEEE
提出一种结合VCO-CTDSM与NS-SAR量化器的混合架构，通过AAF实现高阶噪声传递函数。
28nm CMOS, 1-MHz带宽, 100 MS/s, 1.62 mW功耗
JSSC 2024第4期Power ManagementNeural Network Accelerator
An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-M
提出一种基于变压器优先的离散时间模拟前端，通过输入阻抗提升环路实现超高输入阻抗和低噪声。
389MΩ@1kHz输入阻抗，1.36µVrms输入参考噪声，370nW功耗，NEF=0.34，PEF=0.1
JSSC 2024第4期Power ManagementSAR ADCEnergy Harvesting
An Incremental Step Sensing MPPT Based SI-SIDO Energy Harvester With 99 Peak MPP
提出一种基于增量步进传感的MPPT算法，实现高效能量收集系统。
99.5% MPPT效率，88%转换效率，1.8 µW静态功耗
JSSC 2024第4期Power ManagementBuck Converter
An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter With Relieved C
提出一种相位交错混合降压转换器，缓解电容充电电流并提升效率。
180nm CMOS, 1.8-3.3V输入, 0.8-1.8V输出, 峰值效率97.3%, 电流密度585mA/mm³
JSSC 2024第4期Other
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile
Arvon系统集成FPGA与DSP芯片，实现高性能异构计算。
14-nm FPGA, 22-nm DSP, 4.14 TFLOPS, 1.8 TFLOPS/W, 4 Gb/s/pin
JSSC 2024第4期Power ManagementEnergy Harvesting
Comments and Corrections Corrections to “A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting”
对同步开关能量收集整流器的表格数据进行了更正。
JSSC 2024第4期Other
Concurrent Body-Coupled Powering and Communication ICs With a
提出一种利用单电极实现体耦合供电与通信并发的集成电路设计
40-nm CMOS, 89.1%效率
JSSC 2024第4期Other
Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits Mototsugu Hamada and Ron Kapusta This Special Issue of IEEE J OURNAL OF SOLID -STATE CIRCUITS highlights some of the outstanding circuit papers presented at the Symposium on VLSI Technology and Circuits. The Symposium was held in person, June 11–16, 2023, in Kyoto, Japan. After 35 years of existence as two co-located conferences
2023年VLSI技术与电路研讨会特刊介绍，合并后的会议规模创历史新高。
无
JSSC 2024第4期Power Management
Monolithic 230-V RMS-to-12-VDC ACDC Converter at 9 mWmm 2 Enabled by a 31325-V D
采用180nm高压SOI CMOS工艺实现的全集成230V交流至12V直流转换器，功率密度达9mW/mm²。
180nm SOI CMOS, 230Vrms输入, 12Vdc输出, 9mW/mm²功率密度, 55.1%效率
JSSC 2024第4期Other
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-U
介绍超截止晶体管技术和皮瓦级功耗模拟电路模块，应用于无电池光唤醒接收器。
180-nm CMOS, 37-dB dc gain, 22.4-Hz gain-bandwidth, 25-µV input-referred noise, 6.87 pW
JSSC 2024第4期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，提供固态电路领域的最新研究成果。
无
JSSC 2024第5期OtherVCO
A 10.8–14.5-GHz Eight-Phase 12.5%-Duty-Cycle Nonoverlapping LO Generator With Automatic Phase-and-Duty-Cycle Calibration Khoi T. Phan
一款10.8-14.5GHz八相12.5%占空比非重叠LO发生器，用于60GHz八路径滤波子采样接收机。
10.8-14.5GHz, 77.8mW, 1V, 0.1°相位误差, -5dBm四次谐波输出
JSSC 2024第5期RF & Wireless
A 28 nm CMOS Dual-Band Concurrent WLAN and Narrow Band Transmitter With On-Chip Feedforward TX-to-TX Interference Cancellation Path for Low Antenna-to-Antenna Isolation in IoT Devices
提出一种28nm CMOS双频并发WLAN和窄带发射机，采用片上干扰消除技术提升IoT设备性能。
28nm CMOS, IMD3降低25dB, 并发输出功率提升至17dBm
JSSC 2024第5期Power ManagementBuck Converter
A 4-Phase DAB Current-Mode Hysteretic Controlled Buck Converter With Relaxed Inductor Requirements and Enhanced DC and Dynamic Performance Lei Zhao , Student Member , IEEE, Junyao Tang , Student Member , IEEE
提出一种四相电流模式滞环控制降压转换器，采用双自适应边界控制解决延迟和失配问题。
180nm CMOS, 1.8V输入, 0.6-1.5V输出, 93.9%峰值效率, 10/25MHz开关频率
JSSC 2024第5期RF & Wireless
A 400-GHz Efficient Radiator and OOK Transceiver for Multi-Gb/s Wireless Communication in Silicon
90nm SiGe BiCMOS工艺下实现400GHz高效辐射器及OOK收发器，支持多Gb/s无线通信。
90nm SiGe BiCMOS, +20.6dBm EIRP, 0.2%效率, 10Gb/s(发射), 5Gb/s(收发系统)
JSSC 2024第5期Digital Circuits
A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit Jin-O Seo
提出一种具有抗PVT变化模拟数据路径的CNN处理器，实现高能效和低计算误差。
28nm CMOS, 437.9 TOPS/W (模拟数据路径), 44.2 TOPS/W (全系统), ±10%电压变化, -20°C至85°C温度变化下精度损失<0.5%
JSSC 2024第5期Other
A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System With Level-Adaptive Duty Modulation and Offset
提出一种高效电感充电开关电容刺激系统，实现92%的充电效率和增强的刺激效果。
1-µF电容充电至3V，50µs（0V起始）或28µs（1.5V起始），充电效率90%-92.7%
JSSC 2024第5期RF & Wireless
A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multi-Band Phased-Array Transceivers Fuyuan Zhao
采用电感突变技术的毫米波收发前端，实现多频段相控阵收发器的频带切换。
28nm CMOS, 峰值增益19.1/17.2 dB (PA), 21.3/18.3 dB (LNA), OP1dB 17.8/15.0 dBm (PA)
JSSC 2024第5期Power ManagementBoost ConverterNeural Network Accelerator
A Battery-Input Three-Mode Buck–Boost Hybrid DC–DC Converter With 97.6% Peak Efficiency Shuangxing Zhao
提出一种适用于锂离子电池的三模式非反相升降压混合转换器，峰值效率达97.6%。
0.18-µm CMOS, 3.3-V, 2-MHz, 2.7-4.2V输入, 3.3V输出, 100-800mA
JSSC 2024第5期RF & WirelessPower Amplifier
A Broadband Four-Way Parallel–Series Doherty Power Amplifier for 5G Communications
提出一种宽带四路并联-串联Doherty功率放大器，支持5G通信的宽带操作和深度功率回退效率提升。
22.5–23.9-dBm OP 1dB, 26.2%–38.2% PAEOP1dB, 18.1%–34.5% PAE 6dB PBO, 10.7%–22.1% PAE 12dB PBO
JSSC 2024第5期RF & WirelessPAM-4
A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for
首款低温CMOS 40-Gb/s PAM4有线发射器，用于量子计算数据传输。
40nm CMOS, 40-Gb/s (36-Gb/s), 2.46 pJ/b (2.47 pJ/b), 97.8% (96.6%) RLM
JSSC 2024第5期Clocking & PLLsPLL
A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing
一款基于DPLL的192-210GHz快速回锁啁啾信号发生器，具有59dBm峰值输出
192-210GHz, +5.9/+19.2dBm EIRP, 3.0% dc-to-THz效率
JSSC 2024第5期RF & Wireless
A Four-Channel BiCMOS Transmitter for a Quantum Magnetometer Based on Nitrogen-V
基于氮空位中心的量子磁力计四通道BiCMOS发射器设计
412mA pp输出电流，6.4-8GHz频率范围，170µT磁场强度
JSSC 2024第5期Power ManagementBuck ConverterNeural Network Accelerator
A High-Efficiency Wide Output Range Reconfigurable Capacitive-Sigma DC–DC Converter
高效可重构电容-Σ DC-DC转换器，峰值效率达98.4%
98.4%峰值效率，1.2V/0.4V输出，2A负载范围
JSSC 2024第5期mm-Wave
A Low-Loss Passive D-Band Phase Shifter for Calibration-Free, Precise
提出一种用于D波段的低损耗无源移相器，实现无需校准的精确相位控制。
140 GHz, 5-bit, 11.25° steps, 360° tuning range, 11.5 ± 0.8 dB insertion loss, 1.2° rms phase error, >12.9 dBm IP1dB
JSSC 2024第5期Other
A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive
提出一种新型双路径自干扰消除方案，支持瓦级功率处理，噪声和线性度表现优异。
65nm CMOS, 600 MHz, 45-dB SIC, 12-dBm RX SI peak power, 4-dB NF degradation, 207-mW power consumption
JSSC 2024第5期RF & Wireless
A Monolithic O-Band Coherent Optical Receiver for Energy-Efficient Links
展示了一种用于短距离光互连的1310nm相干光接收器，支持56-GBd符号率，能效优异。
56-GBd符号率（112 Gbps），接收器能效0.73 pJ/bit
JSSC 2024第5期Other
A Monolithically Integrable Reconfigurable Antenna Based on Large-Area Electronics
基于大面积电子学的单片集成可重构天线，实现高频段波束控制和频率调谐
9×9 cm²天线面积，11×11子辐射器阵列，208个TFT射频开关，90°波束控制，200MHz频率调谐
JSSC 2024第5期Power Management
A Simultaneous Energy Transferring SIBO Converter Achieving Low Ripple and High Efficiency for AMOLED Applications Hyo-Jin Park
提出一种用于AMOLED显示的低纹波高效率单电感双极输出转换器。
24.5/28mV纹波, 94.1%峰值效率, 1.46mm²面积, 300mA负载电流
JSSC 2024第5期Other
A Sub-5mW Monolithic CMOS-MEMS Thermal Flow Sensing SoC With 6 ms Linear Range W
提出一种功耗低于5mW的CMOS-MEMS单片集成热流传感器SoC，具有高灵敏度和宽线性范围。
156mV/(m/s)灵敏度，±11m/s检测范围，±6m/s线性范围，86μm/s检测限，<5mW功耗
JSSC 2024第5期Power Management
A Through-Power-Link Hysteretic-Controlled Capacitive Isolated DC–DC Converter With Enhanced Efficiency and Common-Mode
本文提出了一种电容隔离DC-DC转换器，通过创新设计实现了高效率、快速瞬态响应和高共模瞬态抗扰度。
68%峰值效率，±8kV共模瞬态抗扰度，414/828mW功率容量
JSSC 2024第5期RF & Wireless
A Wideband Sliding Digital-IF Quadrature Digital Transmitter for Multimode NB-IoT/BLE Applications
提出一种宽带滑动数字中频正交数字发射器，适用于多模多频窄带物联网/蓝牙低功耗应用。
28nm CMOS, 0.9/1.8V, 28.7dBm峰值输出功率, 47.7%系统效率
JSSC 2024第5期Data ConvertersCIM
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong
提出一种支持稀疏性和高利用率的存内计算神经网络处理器，能效达9.5 TOPS/W。
65nm CMOS, 9.5 TOPS/W at 4-bit precision
JSSC 2024第5期mm-WaveNeural Network Accelerator
Compact mm-Wave Ultra-Wideband and Low-Noise Phase Alternately Distributed Quasi-Circulators
28nm CMOS工艺下的超宽带低噪声准循环器设计
28nm CMOS, 20.5−35.5 GHz带宽, 4.5 dB TX-to-ANT增益, 3.6 dB ANT-to-RX插入损耗, >21 dB TX-to-RX隔离
JSSC 2024第5期Power Management
Design of Direct 48-V/1-V Three-Path Four-State Switching Power Converter With Adaptive VCF Rebalancing and Dual-Edge tdead Modulation Yuanqing Huang , Student Member , IEEE
提出一种新型三路径四状态（3P4S）混合开关电源转换器，实现高效48V至1V直接转换。
峰值效率90.7%（12V输入）和85.6%（48V输入），有效开关频率4.5MHz
JSSC 2024第5期Wireline I/OPAM-4
Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS
28nm CMOS工艺下设计的非相干100Gbps双波段PAM-4塑料光纤链路
28nm CMOS, 100Gb/s@3m, 574mW, BER<2.2e-4
JSSC 2024第5期RF & Wireless
Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium T
2023年RFIC研讨会精选论文特辑，涵盖射频与毫米波集成电路的前沿技术与应用。
无
JSSC 2024第5期Other
New Associate Editor I
Jane Gu教授成为IEEE JSSC期刊的新副编辑，专注于高速集成电路和系统研究。
无
JSSC 2024第5期RF & WirelessHigh-Speed Link
Parallel Versus Serial: Design of an Optical Receiver With Integrated Blue Photodetectors and Digitally Tunable Low-End Cutoff Frequency for MicroLED-Based Parallel
比较并行与串行光链路的能效，提出集成蓝光光电探测器的并行光接收机设计。
130nm CMOS SOI, 2Gbps, -19.3dBm灵敏度, 0.5pJ/bit能效
JSSC 2024第5期RF & WirelessNeural Network Accelerator
RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback Jacob Dean , Student Member , IEEE
本文介绍了一种采用频率转换负反馈的多波段直接下变频接收器。
45nm SOI CMOS, 6-50 GHz, 25-dB增益, 4.1-17-dB噪声系数, 71 mW核心功耗
JSSC 2024第5期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，介绍其组织结构和委员会成员。
无
JSSC 2024第6期RF & WirelessCDREqualizer
A 10-Gbs Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for F
一种用于FSO-WDM系统的10Gbps有线接收器，采用线性波特率CDR和模拟均衡器。
3.8 pJ/bit, 0.147 mm²
JSSC 2024第6期Clocking & PLLsPLL
A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL Pratap
提出一种16GHz电荷泵锁相环，用于高效FMCW雷达信号生成。
16GHz, 29.3MHz/µs chirp slope, 41kHz rms-frequency error, 16.5mW
JSSC 2024第6期RF & WirelessPower Amplifier
A 200-GHz Power Amplifier With 18.7-dBm Psat in 45-nm CMOS SOI: A Model-Based Large-Signal Approach on Cascaded Series-Connected
提出一种新型级联功率放大器设计，在45nm CMOS SOI工艺下实现200GHz高频高功率输出。
45nm CMOS SOI, 200GHz, 18.7-dBm Pout, 4.8% PAE, 14.6dB增益
JSSC 2024第6期RF & WirelessPower Amplifier
A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control
提出一种27W无线功率收发器，采用紧凑单级调节Class-E架构，提升系统效率。
27W, 6.78MHz, 63.0% E2E效率, 80.0%峰值E2E效率
JSSC 2024第6期Data ConvertersDACSRAM
A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations
提出一种基于PMOS的8T SRAM存内计算宏设计，采用BL电荷共享技术降低DAC和ADC硬件成本。
28nm CMOS, 0.6-1.2V, 50.1-TOPS/W, CIFAR-10准确率91.26%
JSSC 2024第6期Digital Circuits
A 288-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring Po-S
本文提出了一种基于暗通道先验的盲图像去模糊加速器，显著降低了计算延迟和功耗。
40nm CMOS, 0.65V, 65MHz, 28.8mW
JSSC 2024第6期Power Management
A 30-µW 94.7-dB SNDR Noise-Shaping Current-Mode Direct-to-Digital Converter Using Triple-Slope Quantizer for PPG/NIRS Readout
一种低功耗、高动态范围的电流模式直接数字转换器，采用噪声整形三斜率量化器。
55nm CMOS, 30µW, 94.7dB SNDR, 136.5dB DR
JSSC 2024第6期RF & Wireless
A 65-nm Sub-10-mW Communication/Ranging Quadrature Uncertain-IF IR-UWB Transceiver With Twin-OOK Modulation
65纳米工艺下实现低于10mW功耗的通信测距正交不确定中频IR-UWB收发器
65nm CMOS, 6-8GHz, 10Mb/s, -71dBm灵敏度, 0.96cm测距精度
JSSC 2024第6期Power Management
A 934 Peak Efficiency CLOAD-Free Multi-Phase Switched-Capacitor DCDC Converter A
提出一种高效率多相开关电容DC-DC转换器，支持快速动态电压调节，峰值效率达93.4%。
65nm CMOS, 1.2V, 93.4%峰值效率, 222.5 mV/ns DVS速度
JSSC 2024第6期Power ManagementBuck Converter
A 94.9% Efficiency Always-Power-Delivered SIDO Buck Converter With Continuous Current Balancing and Complementary Adaptive-Switching Regulation
提出一种高效单电感双输出降压转换器，实现持续功率输出并降低电压波动。
180nm CMOS, 5V输入, 1.8V/3.3V输出, 峰值效率94.9%
JSSC 2024第6期OtherEnergy Harvesting
A Bias-Flip Rectifier With Duty-Cycle-Based MPPT for Piezoelectric
提出一种基于占空比的最大功率点跟踪算法，用于压电能量收集的偏置翻转整流器。
98%峰值MPPT效率，738%输出功率增强
JSSC 2024第6期Other
A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile
一款基于SPAD成像和直接脉冲计算的仿生脉冲视觉芯片，实现高动态范围2D/3D视觉和实时智能处理。
128×128 SPAD图像传感器
JSSC 2024第6期RF & WirelessPower AmplifierNeural Network Accelerator
A Dual-Path Transformer-Based Multiband Power Amplifier for mm-Wave 5G
基于双路径变压器的毫米波5G双频段功率放大器设计
28/39 GHz频段饱和输出功率15.3/14.0 dBm，峰值效率34.1%/30.2%
JSSC 2024第6期Clocking & PLLs
A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS
提出一种基于单晶振的全集成低成本低噪声时钟管理IC，适用于5G移动设备。
0.68-ppm/°C稳定性, 48.2µW RTC功耗, 1.08mW XO功耗, -158.2dBc/Hz@100kHz相位噪声
JSSC 2024第6期Power ManagementLDO
A Fully Synthesizable All-Digital Dual-Loop Distributed Low-Dropout Regulator
全数字双环路分布式低压差稳压器，采用全局控制器和可扩展本地稳压器，实现高精度和快速瞬态响应。
28nm CMOS, 54mV droop under 1.35A/10ns load step, 3mV/A load regulation
JSSC 2024第6期RF & Wireless
A Highly Selective Receiver With Programmable Zeros and Second-Order TIA Mohammad
本文提出一种宽带抗干扰接收器，适用于5G用户设备，具有高选择性和低功耗。
40nm CMOS, 1.3V, 100MS/s
JSSC 2024第6期OtherPhased Array
A Multimode 157 µW 4-Channel 80 dBA-SNDR Speech Recognition Frontend With Direction-of-Arrival Correction
一种多模式157µW语音识别前端系统，通过创新贪婪阻塞矩阵和自动方向误差补偿提升性能。
40nm CMOS, 157µW/72µW高低功耗模式, 0.94mm²面积
JSSC 2024第6期RF & Wireless
A Wideband Full-Duplex Receiver With Multi-Domain Self-Interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers
提出一种基于电容堆叠延迟单元的全双工接收机，实现多域自干扰消除，支持0.5-4GHz宽频带操作。
65nm CMOS, 0.5-4GHz, 29-32dB增益, 射频消除器2-7.5ns延迟/10mW, 基带消除器9-15ns延迟/4.4mW
JSSC 2024第6期Other
An SP10T Switch With Reconfigurable Matching and Symmetrical Routing Topologies Functioning From DC to 18 GHz
一种宽带低插入损耗的SP10T开关，采用三种创新拓扑结构实现从直流到18GHz的优异性能。
0.15-µm GaAs pHEMT, 1.1-3.2dB IL, DC-18GHz BW, >24dB隔离度
JSSC 2024第6期OtherNeural Network Accelerator
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies Hikmet Çeliker , Member , IEEE, Florian
分析比较五种逻辑架构在a-IGZO TFT技术中的性能与适用性。
6英寸玻璃晶圆和柔性基板上的a-IGZO TFT
JSSC 2024第6期MemorySRAMCIM
Cramming More Weight Data Onto Compute-in- Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS
提出一种基于1T-MLC ROM的存内计算宏单元，以提高存储密度和能效。
未明确提及具体性能指标
JSSC 2024第6期Power Management
Design of Dual Lower Bound Hysteresis Control in Switched-Capacitor DC–DC Converter for Optimum Efficiency and Transient Speed in Wide Loading Range for IoT Application
提出双下界滞环控制方法，提升SC DC-DC转换器在IoT应用中的效率和响应速度。
180-nm CMOS, 75%效率, 80.4%峰值效率, 80ns响应时间
JSSC 2024第6期Other
Enabling Online GaN Power Device Self-Health Monitoring With Analog SGD Supervised Learning and TJ-Independent
利用模拟SGD监督学习实现GaN功率器件在线自健康监测
180nm BCD工艺, 2.9mm²芯片面积, 3.3MHz工作频率, 5-40V输入, 9W输出功率
JSSC 2024第6期Digital Circuits
HGRP: A 181- µW Real-Time Hand Gesture Recognition Processor Based on Bi-Directional Convolution and Iteration-Free
提出一种基于双向卷积的181µW超低功耗实时手势识别处理器。
65nm CMOS, 0.58V, 181µW
JSSC 2024第6期MemorySRAM
MACC-SRAM A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM M
提出一种基于电容耦合的多步累加存内计算SRAM宏，用于4位深度卷积神经网络推理。
128×128 9T1C单元阵列，6位SAR ADC
JSSC 2024第6期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，提供固态电路领域的最新研究成果。
无
JSSC 2024第6期Other
V oltage Level Detection for Near-VTH Computing Asaf Feldman Graduate Student M
提出了一种无毛刺的低压电压检测器，适用于近阈值计算，检测电压低至385mV，功耗217nW，延迟10µs。
385 mV, 217 nW, 10 µs, 6900 µm², 105 µW/°C, 8 mV
JSSC 2024第7期Data ConvertersSAR ADC
A 0.004-mm 2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp
一种采用kT/C噪声消除技术和鲁棒输入的小面积高速SAR ADC
28nm CMOS, 13-bit, 200MS/s, 0.004mm², 1.3mW
JSSC 2024第7期Wireline I/O
A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method
一款基于StrongARM锁存比较器和平方取中法的10Gb/s全数字真随机数生成器
28nm CMOS, 10Gb/s吞吐量, 0.121pJ/bit能效
JSSC 2024第7期RF & WirelessDACEqualizer
A 116-Gb/s PAM4 0.9-pJ/b Transmitter With Eight-Tap FFE in 5-nm FinFET Yevgeny Perelman , Zeev Toroker
一篇关于116-Gb/s PAM4电压模式发射器的IEEE JSSC论文，采用5-nm FinFET工艺实现高效能传输。
116-Gb/s PAM4, 0.9 pJ/bit, 0.082 mm²面积
JSSC 2024第7期Other
A 22-dBA Digital Optical MEMS Microphone Niccolò de Milleri
本文提出了一种结合MEMS技术和创新光学传感技术的数字光学麦克风，显著降低了系统固有噪声并提高了信噪比。
SNR 71.6 dBA, 输出灵敏度 -21 dBFS/Pa, 封装尺寸 5 × 5 × 2 mm³
JSSC 2024第7期Data ConvertersClock Generation
A 2.5-GHz Dynamic Performance-Enhanced Nonlinear DAC-Based Direct-Digital Frequency Synthesizer in 65-nm CMOS Process
提出了一种基于DAC的直接数字频率合成器，通过固定权重解码器和三态解码方案提升性能。
最差无杂散动态范围（SFDR）57.35 dBc @2.5 GHz，功耗104 mW
JSSC 2024第7期Digital CircuitsNeural Network Accelerator
A 3.8-mW 1.9-m/ √Hz Electrical Impedance Tomography IC With High Input Impedance and Loading Effect Calibration for 3-D Early Breast Cancer
一款低功耗高输入阻抗的3D电阻抗断层成像芯片，提升接触阻抗变化下的稳定性。
3.8mW功耗（不包括注入电流），1.9mΩ/√Hz阻抗分辨率，2.9GΩ@100Hz输入阻抗，230kΩ@1MHz输入阻抗
JSSC 2024第7期Data ConvertersSAR ADCNeural Network Accelerator
A 511-µW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique Hao-Hsuan Chang , Ci-Ren Chen , and Tai-Cheng Lee
提出了一种混合两级ADC，结合SAR ADC和ISDM ADC，提升SNDR和功率效率。
370kHz频率，185kHz带宽，511µW功耗，89.3dB SNDR
JSSC 2024第7期MemoryEmerging MemoryCIM
A 65-nm RRAM Compute-in-Memory Macro for
首款基于RRAM的存内计算宏单元，专为基因组处理优化。
65nm CMOS, 1.0V, 2.07 TOPS/W, 2.12 G suffixes/J
JSSC 2024第7期MemorySRAMDRAM
A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS Rob A. Damsteegt , Ramon W. J. Overwater
本文比较了40nm CMOS工艺下SRAM与DRAM在室温至4.2K低温下的性能，提出低温存储器设计指南。
40nm CMOS, 4.2K, 75kHz
JSSC 2024第7期Other
A Chip-PCB Hybrid SC PUF Used for Anti-Desoldering and Depackaging-Attack Protection Meilin Wan , Zhen Zhang , Yin Zhang , Zhangqing He , Haoshuang Gu
通过检测芯片与PCB间寄生电容变化实现防拆解和防封装攻击的物理不可克隆功能
28-nm CMOS, 14-nm FinFET, 7-nm FinFET
JSSC 2024第7期RF & WirelessPLL
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering
提出一种基于谐波混频器双反馈和分频反馈的分数N环PLL，实现低相位噪声和抖动。
65-nm CMOS, −229.4-dB jitter-power FoM, −49-dBc worst-case fractional spurs, 40-MHz reference
JSSC 2024第7期MemoryEmerging Memory
A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for
基于22nm FD-SOI工艺的256kb MRAM存内计算宏，采用差分读出架构解决电源和耦合噪声问题。
256kb, 22nm FD-SOI, 128-512行和512列全并行
JSSC 2024第7期RF & WirelessPower Amplifier
A Highly Linear and Efficient V -Band CMOS Power Amplifier Using Hybrid NMOSPMOS
采用混合NMOS/PMOS技术的V波段高效线性CMOS功率放大器
45nm CMOS SOI, 35.4% PAE, 16.3dBm Psat, AM-PM<2°@13.5dBm, EVM<-25dB@64-QAM
JSSC 2024第7期RF & Wireless
A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking Bo Zhou , Yifan Li , Zuhang Wang
一种低复杂度FM-UWB发射器，采用数字重用和模拟堆叠技术
65nm CMOS, 0.46mW, 100kb/s, -14.3dBm, -86.2dBc/Hz
JSSC 2024第7期OtherPAM-4
A Low-Power High-BW PAM4 VCSEL Driver With Three-Tap FFE in 12-nm CMOS FinFET
12nm CMOS FinFET工艺下的低功耗高带宽PAM4 VCSEL驱动器，支持64Gb/s数据传输。
12nm CMOS, 1/2/-1.5V, 50Gb/s NRZ, 64Gb/s PAM4, 0.82pJ/b
JSSC 2024第7期Clocking & PLLsPLL
A Multireference PLL: Theory and Implementation
提出多参考时钟PLL架构，降低参考相位噪声，实现16.1 fs抖动。
65nm CMOS, 16.1 fs抖动
JSSC 2024第7期RF & WirelessPower Amplifier
A Quadrature Digital Power Amplifier With Wide Efficiency Enhancement Coverage and High Dynamic
提出一种15位正交数字功率放大器，具有宽效率增强覆盖和高动态功率范围。
28nm CMOS, 29.9 dBm峰值输出功率, 38.0% PAE, 70.4-dB动态功率范围
JSSC 2024第7期Power ManagementProcessor/CPU
A Sub-µW Energy-Performance-Aware IoT SoC With a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and
提出一种采用三模式电源管理单元的超低功耗物联网SoC，实现自适应功耗-性能调节和最小能耗运行。
194.3 nW @180Hz, 92.6%峰值效率, 379 pW空闲功耗
JSSC 2024第7期Power ManagementBuck Converter
A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node
提出一种高效十级串联电容24V至1V降压转换器，采用三种技术提升效率和可靠性。
峰值功率效率93.89%（负载电流405mA），效率提升高达34.74%
JSSC 2024第7期MemorySRAMCIM
An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI
一种采用时域增量技术的8位精度6T SRAM存内计算宏单元，实现高能效MAC运算。
28nm CMOS, 39.31 TOPS/W能效, 6.6ns计算延迟, 8b-MAC运算, 64次累加/周期, 22b输出精度
JSSC 2024第7期Image Sensors
An Ultra-High 6318-PPI Pixel Circuit for Micro-OLED Displays With Vth Compensated up to 10-bit
提出一种8T2C像素电路，实现6318 PPI微OLED显示并支持10位Vth补偿。
6318 PPI, 10-bit Vth补偿, 0.64V动态范围
JSSC 2024第7期Other
An Ultralow-Power Triaxial MEMS Accelerometer With High-V oltage Biasing and Electrostatic
一种采用高压偏置技术的超低功耗三轴MEMS加速度计，显著提升信噪比并降低功耗。
121µg/√Hz噪声密度, ±1.5g动态范围, <1%线性误差, 184nW/轴功耗（含高压生成）
JSSC 2024第7期Other
DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation
提出动态自校准可调复制关键路径（DSC-TRCP）方法，结合原位和间接监测优势，降低功耗并提升频率。
28nm CMOS, 0.55V, 31MHz, 58%功耗降低, 232%频率提升
JSSC 2024第7期RF & Wireless
Design of a Low-Power, High-Data-Rate, and Crystal-Less All-Digital IR-UWB Transmitter for High-Density Neural Implants Jiaxin Lei , Student Member , IEEE, Xiliang Liu
设计了一种低功耗高数据速率且无需晶振的全数字IR-UWB发射器，用于高密度神经植入物。
1.8 Gbps数据速率，4.09 mW功耗，2.3 pJ/bit能效
JSSC 2024第7期MemoryEmerging Memory
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density
EMBER提出高效多比特RRAM宏设计，优化读写电路并提升存储密度与可靠性。
100 MHz, 64k×48=3M cells
JSSC 2024第7期RF & Wireless
Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines Sasank Garikapati , Student Member , IEEE
利用时间交织多路径开关电容电路实现宽带高功率射频自干扰消除的全双工接收机
0.1至1 GHz工作频率
JSSC 2024第7期Clocking & PLLsPLL
Guest Editorial IEEE 2023 European Solid-State Circuits Conference W ELCOME to t
IEEE JSSC期刊介绍2023年欧洲固态电路会议精选论文，涵盖PLL、电压模式驱动器、声学传感、3D EIT成像系统和节能技术等创新研究。
40-Gb/s NRZ, 50-Gb/s PAM4, 1.4 dBm, 0.82 pJ/b
JSSC 2024第7期MemoryCIM
PRESTO: A Processing-in-Memory-Based k-SAT Solver Using Recurrent Stochastic Neural Network With
基于存内计算的k-SAT求解器PRESTO，采用随机神经网络和混合信号电路架构
65nm CMOS, 0.4mm²核心面积, 100-500MHz工作频率, 35.4mW峰值功耗
JSSC 2024第7期Power ManagementEnergy Harvesting
Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC–DC for MPPT
提出一种新型八相自偏置翻转压电能量收集接口，实现高效能量回收与转换。
电压翻转效率达80%，最大输出功率提升率4.88×
JSSC 2024第7期MemoryEmerging Memory
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural
16nm异构RISC-V SoC Siracusa，集成MRAM神经引擎，提升XR能效。
65.2 GOp/s/mm², 8.84 TOp/J
JSSC 2024第7期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE固态电路期刊的编辑和委员会成员信息
无
JSSC 2024第8期Digital Circuits
ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-µJ/Sample On-Chip Learning for Edge-AI Applications
提出一种28nm异步脉冲神经网络处理器，通过优化学习算法降低片上学习能耗。
28nm CMOS, 0.56V, 40MHz, 1.25mm², <0.1µJ/样本学习能耗
JSSC 2024第8期RF & Wireless
A 0.68-THz Receiver With Third-Order Subharmonic Mixing in 65-nm CMOS
65nm CMOS工艺下实现0.68-THz接收机，采用三次谐波混频技术提升性能。
682GHz下噪声系数28.4dB，输入频率范围138GHz
JSSC 2024第8期RF & WirelessPhased Array
A 125 µm-Pitch-Matched Transceiver ASIC With Micro-Beamforming ADC and Multi-Level Signaling for 3-D
本文介绍了一种用于经囟门超声检查的可穿戴设备中的125µm间距匹配收发器ASIC。
180nm BCD, 1.83 mW/element, 3.84 Gb/s, 3.3 pJ/bit
JSSC 2024第8期RF & WirelessPower AmplifierNeural Network Accelerator
A 13.56-MHz Single-Input Dual-Output Wireless Power and Data Transfer System for Bio-Implants
一种用于生物植入物的13.56MHz单输入双输出无线功率与数据传输系统，采用可重构功率放大器和动态功率分配方案。
423.75 kb/s上行数据速率，6mm距离下62.7%功率传输效率
JSSC 2024第8期Data ConvertersSAR ADCPipeline ADC
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC Jae-Hyun Chung
提出了一种高效能高分辨率的双残差流水线-SAR ADC，结合噪声整形技术。
81.2-dB SNDR, 89.9-dB SFDR, 1.5-MHz BW, OSR=8, 170.4-dB Schreier FoM
JSSC 2024第8期RF & Wireless
A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links Woohyun Kwon , Hyosup Won, Taeho Kim, Sejun Jeon , Soon-Won Kwon , Ha-Il Song
提出一种高速帧脉冲宽度调制收发器，通过时域调制方案提高频谱效率。
28nm CMOS, 0.9V, 26Gb/s
JSSC 2024第8期MemoryCIM
A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-
提出一种28nm浮点存内计算处理器，采用密集-稀疏架构提升能效。
28nm CMOS
JSSC 2024第8期Analog CircuitsNeural Network Accelerator
A 64-Channel Inverter-Based Neural Signal Recording Amplifier With a Novel Differential-Like OTA Achieving an NEF of 0.84 Qiuzhen Xu , Gen Li, Yanyan Liu
提出一种基于逆变器的64通道低功耗低噪声神经信号记录放大器，采用新型差分OTA设计。
NEF 0.84, 每通道平均电流422nA, 每通道面积0.044mm²
JSSC 2024第8期Power ManagementBuck Converter
A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum
提出一种高效单电感多输出降压转换器，通过非线性控制和混合数字LDO提升性能
2.1 A/ns瞬态处理能力，2.2 A最大电流容量，96.1%峰值效率
JSSC 2024第8期Medical & BioEnergy Harvesting
A Battery-Free Neural-Recording Chip Achieving 5.5 cm Fully-Implanted Depth by Galvanically- Switching Passive Body
提出一种无电池神经记录芯片，通过电导切换被动体通信技术实现5.5厘米植入深度。
55nm CMOS, 5.5cm通信范围, 4.4×10−6误码率
JSSC 2024第8期RF & WirelessPower Amplifier
A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS
一款支持5G及未来的宽带毫米波线性功率放大器，采用异步调谐耦合谐振器电路模型和自适应反馈线性化技术。
28nm CMOS, 19.7-43.8 GHz, 18.7-20.3-dBm Psat, 24.9%-35.5% PAE max
JSSC 2024第8期RF & Wireless
A D-Band OOK Transmitter With 50-GHz Bandwidth Achieving 32-Gbps Data Rate in 28-nm CMOS
一款D波段OOK发射器，在28nm CMOS工艺下实现32Gbps数据速率
28nm CMOS, 1V电源电压, 5dBm输出功率, 167mW功耗, 32Gbps数据速率
JSSC 2024第8期Clocking & PLLsPLL
A Fractional- N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD
提出一种3.3-4.5 GHz分数-N采样锁相环，结合恒定斜率DTC和采样PD，降低噪声和非线性。
203 fs rms抖动, 2.4 mW功耗, FoM -250 dB
JSSC 2024第8期Analog Circuits
A Fully Dynamic Event-Driven Capacitive Sensor Interface Circuits Based on Self-
提出一种基于事件驱动的多通道电容传感器接口电路，降低功耗和数据负担。
55nm CMOS, 2.244mm², 51dB SNR, 7.2µW/Ch
JSSC 2024第8期Power ManagementBuck Converter
A Fully Integrated Multi-Phase V oltage Regulator With Flying-Capacitor-Based Inter-Inductor Current Self-Balancing Scheme and Charge-Recycling
提出一种高功率密度、快速动态电压调节的自平衡电感电流集成电压调节器。
200 MHz/phase, 45 V/µs DVS rate, 40 mA/ns transient slew rate, 0.9 W/mm² power density, 79.1% peak efficiency
JSSC 2024第8期OtherNeural Network Accelerator
A High-Efficiency 4068-MHz Single-Stage Dual-Output Regulating Rectifier With ZV
一种高效40.68MHz单级双输出调节整流器，采用ZV开关控制。
65nm CMOS, 2.2V/1.1V双输出, 60.5mW, 90.1%峰值效率
JSSC 2024第8期Other
A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver With Quad-Drive Control Technique for High dV/dt 1700-V SiC Power Switch Sheng-Hsi Hung
提出一种具有高共模瞬态免疫力的GaN-on-SOI栅极驱动器，采用四驱动控制技术降低功耗和栅极振铃效应。
109 kV/µs压摆率，100kHz下效率>90%(800-1700V)，峰值效率98.6%(800V)
JSSC 2024第8期RF & Wireless
A Phase-Modulation Phase-Shifting Phased-Array Transmitter With Phase Self-Calibration and Deep PBOs
提出一种带相位自校准的数字相位调制相移相控阵发射机，采用40nm CMOS工艺实现高性能。
40nm CMOS, 2.1-2.9GHz, 26.95dBm峰值输出功率, 0.4°rms相位误差, 42.05dBm峰值EIRP
JSSC 2024第8期RF & Wireless
A Phased-Array Transceiver With 2-Dimension Continuously Auto Link-Tracking Operation and Time
一款支持23-40GHz自动链路追踪的八单元相控阵收发器，采用40nm CMOS工艺。
40nm CMOS, 7µs链路追踪时间, 25.3%峰值发射效率, 支持4.8Gb/s 64-QAM和8Gb/s 16-QAM传输
JSSC 2024第8期Memory
A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial
提出一种可重构、可扩展的近内存位串行硬件加速器，用于高效求解2-D/3-D偏微分方程。
65nm CMOS, 1V, 25.6MHz, 0.7nJ/1.14nJ per grid update
JSSC 2024第8期RF & WirelessHigh-Speed LinkPAM-4
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4
一种采用共模NRZ和差分PAM-4混合信号实现3比特/符号传输的线缆收发器。
28nm CMOS, 48 Gb/s, 0.117 mm², BER 10⁻¹² at 9.0
JSSC 2024第8期Clocking & PLLsVCO
An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and I
提出一种增强型Class-F双核VCO，采用共模噪声自抵消和隔离技术，降低噪声并提升性能。
65nm CMOS, 11.5-14.3 GHz, -119.2 dBc/Hz PN, 192.8 dBc/Hz FoM, 5.6-10 mW
JSSC 2024第8期RF & Wireless
An IEEE 8021544z Coherent Quadrature Hybrid Correlation UWB Receiver in 65-nm CM
提出一种基于正交混合相关法的低功耗超宽带接收机架构，采用模拟相关和时间交错采样技术。
65nm CMOS, 17.3mW, -88dBm灵敏度, 1.9cm测距误差
JSSC 2024第8期RF & WirelessHigh-Speed Link
An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and
提出一种新型八进制调制技术SNRE-8，通过调制脉冲宽度、位置和幅度提升信噪比。
27-Gb/s, BER 10^-8, 5.39 pJ/bit
JSSC 2024第8期RF & WirelessEnergy Harvesting
DiTTO A Distance Adaptive Over 100-mW Wireless Power Transfer System With 1695-M
提出一种距离自适应无线充电系统，支持高速上行数据传输和双输出稳压整流。
1.695-Mb/s上行数据率，108 mW功率输出，10–42 mm单链路距离
JSSC 2024第8期Other
FlexSpin A CMOS Ising Machine With 256 Flexible Spin Processing Elements With 8-
提出一种256个灵活处理单元的CMOS Ising机器，用于高效解决复杂组合优化问题。
65nm CMOS, 256 PEs, 8-bit coefficients, 28 spin interactions
JSSC 2024第8期MemoryEmerging Memory
RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM
RoboVisio是一款高效灵活的专用SoC，用于微型机器人自主导航中的视觉任务。
22nm CMOS, 0.22 nJ/pixels, 3.5 TOPS/W
JSSC 2024第8期MemoryCIM
SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator With Local Error Prediction for Area/Energy-Efficient On-Device Learning
SP-PIM是一种超流水线内存计算加速器，通过局部误差预测提升边缘设备学习效率。
训练速度提升7.31倍，外部内存访问减少59.09%
JSSC 2024第8期Data ConvertersDRAMCIM
Scaling-CIM eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and A
提出一种基于eDRAM的高效能内存计算加速器，通过动态缩放ADC提升信噪比并降低开销。
28nm CMOS, 2.03mm² die area, 800kb eDRAM, 39.7-TOPS/W (8–9 b)
JSSC 2024第8期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，介绍其组织结构和委员会成员。
无
JSSC 2024第9期Power ManagementNeural Network Accelerator
A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC
提出一种24V输入的高集成交错电感多步降压混合DC-DC转换器，采用新型拓扑和片上栅极驱动方案，实现高效能和小尺寸。
24V输入，1-3.5V输出，峰值效率90.4%，最大负载电流5A，效率82%
JSSC 2024第9期RF & WirelessPhased Array
A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX
一款24-30GHz相控阵收发前端，采用130nm BiCMOS工艺，支持5G FR2频段，具有高功率效率和低噪声系数。
130nm BiCMOS, 22%-24% TX效率, 2.8-3.1dB RX NF, 15.6-16.2dBm OP1dB, 17.8-18.8dBm PSAT
JSSC 2024第9期MemorySRAMCIM
A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs
提出一种基于双比特6T SRAM的浮点计算内存宏，支持高能效浮点乘加运算。
31.6 TFLOPS/W能效比，2.05 TFLOPS/mm²面积效率，支持BF16格式
JSSC 2024第9期Digital Circuits
A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching
提出一种28nm能效稀疏神经网络处理器，用于点云应用，支持2-D/3-D统一稀疏卷积。
28nm CMOS, 4.68-TOPS/W峰值能效
JSSC 2024第9期Power ManagementBuck ConverterBoost Converter
A 2.8 µs Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications
提出一种消除右半平面零点的混合升压转换器，实现快速瞬态响应和高效率。
95.1%峰值效率，4.2V输入6V输出，2.8µs稳定时间
JSSC 2024第9期RF & WirelessPAM-4Neural Network Accelerator
A 2 × 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS
一种基于主动串扰消除的2×56 Gb/s PAM-4接收器，能效达0.78 pJ/b。
56 Gb/s PAM-4, BER <1e-10, 24-dB Nyquist loss, 0.78 pJ/b/lane
JSSC 2024第9期RF & WirelessLNA
A 300-µW 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA Martin Lee , Motaz
一种基于亚阈值参考的300µW 24GHz LNA，通过闭环反馈抑制PVT变化
13.96dB增益，4.51dB噪声系数，300µW功耗
JSSC 2024第9期OtherCMOS Image Sensor
A 3 THz CMOS
本文提出了一种3 THz CMOS图像传感器，采用列并行读出架构和紧凑的双晶体管像素设计，实现了高灵敏度和带宽。
753 V/W灵敏度，0.78 THz带宽，73 dB动态范围，130 fps帧率
JSSC 2024第9期RF & WirelessDAC
A 50-Gbs Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET
22nm FinFET工艺下采用DAC极坐标驱动器的50Gbs多载波发射机
22nm FinFET, 1.2V, 50Gb/s, BER<10−4, 1.68pJ/b
JSSC 2024第9期Clocking & PLLsClock Generation
A 6 to 12-GHz Fractional- N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback
一款6至12GHz分数N频率合成器，采用数字技术解决反馈分频器延迟问题。
65nm CMOS, 1V, 66mW, 280kHz带宽, 400-500fs抖动
JSSC 2024第9期MemoryCIM
A Compute-in-Memory Annealing Processor With Interaction Coefficient Reuse and S
提出了一种基于存内计算的数字退火处理器，用于高效解决组合优化问题。
55nm CMOS, 0.9V, 2.4fJ/spin, 402µm²/spin
JSSC 2024第9期Digital Circuits
A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis Ruoyang Liu
提出动态执行神经网络处理器，支持细粒度混合精度训练，提升能效和面积效率。
13.2-TFLOPS/W能效, 1.07-TFLOPS/mm²面积效率
JSSC 2024第9期Power ManagementEnergy Harvesting
A High-Efficiency Low-Cost Multi-Antenna Energy Harvesting System With Leakage S
提出一种多天线射频能量收集系统，通过泄漏抑制和共享缓冲电容实现高效低成本。
180nm CMOS, 1.8V, 44%峰值转换效率
JSSC 2024第9期Clocking & PLLs
A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques
提出一种采用多磁耦合和主动源退化技术的模式切换振荡器，实现宽频率调谐和低相位噪声。
频率调谐范围2.88至5.87 GHz，功耗20.5至27.9 mW，相位噪声-135.8 dBc/Hz @1MHz偏移
JSSC 2024第9期RF & Wireless
A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR Cong Tao , Student Member , IEEE
一款低功耗紧凑型0.1-5.5GHz LNTA优先接收器，适用于软件定义无线电。
40nm LP CMOS, 36mW静态功耗, 3.5dB NF, 40dBm OIP3, 0.1mm²核心面积
JSSC 2024第9期Other
A Partially Feedback NSSAR Embedded Third-Order DeltaSigma Modulator With Gain-B
提出一种低功耗高精度开关电容ΔΣ调制器，嵌入5位NSSAR量化器实现稳定三阶噪声传递函数。
55nm CMOS, 93.7dB SNDR@10kHz, 800kS/s, OSR=40, 33.2µW
JSSC 2024第9期Clocking & PLLsPLLClock Generation
A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET
22nm FinFET工艺下抗辐射15-22GHz频率合成器设计
22nm FinFET, -240.89dB FoM@15GHz, -64dBc杂散
JSSC 2024第9期RF & WirelessVCOEqualizer
A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based T
提出一种单端阻抗匹配发射器，采用环形振荡器时域ZQ校准，实现低误码率和高效能。
65nm CMOS, 12 Gb/s, 1.145 pJ/bit, FoM 0.11 pJ/bit/(dB/pin)
JSSC 2024第9期RF & Wireless
A Single-Stage Bipolar-Output Regulating Rectifier With Negligible Cross-Regulation for Wireless Display
提出一种用于AMOLED显示的单级双极输出调节整流器，具有高效率和低交叉调节特性。
180nm BCD工艺，5V器件，±5V输出，500mA最大输出电流，86.4%峰值效率
JSSC 2024第9期RF & WirelessEnergy Harvesting
A Single-Stage Dual-Output Regulating V oltage Doubler for Wireless
提出一种用于生物医学无线充电的单级双输出调节电压倍增器，具有高效率与快速负载瞬态响应。
180nm BCD, 6.78MHz, 1.8V/3.3V, VCR 1.875, PCE 92.95%, 2.6-90.5mW
JSSC 2024第9期Data ConvertersSAR ADCDAC
An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC Cong Wei , Student Member , IEEE
提出一种动态范围增强的离散时间ΔΣ调制器，适用于物联网应用，具有高能效和低功耗特性。
94.7dB动态范围, 92.4dB SNDR, 700Hz带宽, 2.3μW功耗
JSSC 2024第9期Digital CircuitsNeural Network Accelerator
An Energy-Efficient Neural Network Accelerator With Improved Resilience Against
一款具有抗故障攻击能力的能效神经网络加速器ASIC。
高错误检测能力，面积开销5.9%，对NN精度影响可忽略
JSSC 2024第9期Data ConvertersNeural Network AcceleratorBiosignal
Analysis and Design of a 10.4-ENOB 0.92–5.38-µW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications Jonah Van Assche , Student Member , IEEE
提出一种新型事件驱动电平交叉ADC，采用自适应时钟方案，显著降低功耗并提升系统兼容性。
8-bit 15-kHz BW, 0.92-5.38 µW
JSSC 2024第9期OtherBandgap Reference
Cryo-CMOS V oltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K Job van Staveren , Pinakin M. Padalia
本文提出了一种在300K至低温环境下工作的亚1V CMOS电压基准源家族。
0.99V供电, 2.7%/V线性调整率, 111ppm/K温度系数
JSSC 2024第9期RF & Wireless
Design of High Dynamic Range HBT N-Path Receivers With Dual-Resonant-Mode LO Drive
130nm SiGe BiCMOS工艺下实现高动态范围HBT N-Path接收器设计
20-40GHz工作范围,8.9-9.7dBm OOB B1dB,8.55-10.9dB NF
JSSC 2024第9期Data ConvertersCIM
FLEX-CIM A Flexible Kernel Size 1-GHz 1816-TOPSW 2563-TOPSmm2 Analog Compute-in-
FLEX-CIM提出一种灵活核大小的存内计算架构，提升CNN加速器的能效和吞吐密度。
28nm CMOS, 4-bit MAC精度, 181.6 TOPS/W能效, 25.63 TOPS/mm2吞吐密度
JSSC 2024第9期Digital Circuits
INTIACC: A Programmable Floating- Point Accelerator for Partial Differential
INTIACC是一种可编程浮点加速器，用于高精度求解多种偏微分方程。
65nm CMOS, 1V, 570MHz, 9.12GFLOPS
JSSC 2024第9期Other
Monolithic Electronic–Biophotonic System-on-Chip for Label-Free Real-Time
开发首个全集成电子-光子无标记分子传感器，用于实时分子检测。
60个5µm半径微环谐振器，检测限等效于单个140nm病毒颗粒
JSSC 2024第9期mm-WavePhased Array
Physical Layer Security Through Directional Modulation With Spatio-Temporal Millimeter-Wave
提出一种时空调制阵列技术，通过CMOS集成电路和封装天线实现物理层安全通信。
71-76 GHz, CMOS ICs, packaged antennas
JSSC 2024第9期MemoryFlash MemoryEmerging Memory
Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro B
提出智能写入算法提升RRAM宏的性能与可靠性
128kb RRAM宏, 130nm CMOS, 28.1µA读取裕度, BER<10⁻⁷
JSSC 2024第9期Other
The IEEE J OURNAL OF SOLID -STATE CIRCUITS is published by the IEEE Solid-State
IEEE JSSC期刊由IEEE固态电路学会出版，介绍了其组织结构和委员会成员。
无
JSSC 2024第10期MemoryEmerging Memory
AIMMI: Audio and Image Multi-Modal Intelligence via a Low-Power SoC With 2-MByte On-Chip MRAM for IoT Devices
提出了一种超低功耗多模态信号处理SoC，集成DNN引擎和音像信号处理加速器，适用于物联网场景。
3-10 TOPS/W峰值能效，功耗0.25-3.84 mW
JSSC 2024第10期Digital CircuitsNeural Network Accelerator
A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses Xiang’ao Qi
一款支持128/256可重构神经元的SNN加速器，实现LIF和IZ神经元模型切换，峰值能效达5.37 TSOPs/W。
峰值能效5.37 TSOPs/W，吞吐量25.6 MSOPs/s，图像特征提取能耗9.27 pJ/pixel
JSSC 2024第10期Wireline I/ODRAM
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications Hyun-A Ahn
提出第四代10nm 16Gb LPDDR5x DRAM的I/O电路和控制方法，实现8.5Gbps低功耗运行。
8.5Gbps, 0.66UI Tx眼宽, 0.57UI Rx眼宽, 功耗降低20%
JSSC 2024第10期RF & Wireless
A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable
一种用于无线供电生物医学设备的带分数电容自动调谐环路的主驱动器。
13.56 MHz, 200 mW输出功率, 31.5%调谐范围, 1.89 ns调谐误差
JSSC 2024第10期Data ConvertersSAR ADC
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling Dong-Hun Lee , Kent
采用SAR辅助DNC技术和MASH结构的高分辨率连续时间ΔΣ调制器
28nm CMOS, 1.1V, 25kHz带宽, 97.4dB SNDR, 260µW功耗
JSSC 2024第10期RF & WirelessPhased Array
A 28-GHz Hybrid Beamforming Transmitter With Spatial Notch Steering Enabling Concurrent Dual Data Streams for 5G MIMO Applications
提出一种28GHz混合波束成形发射器，通过空间凹槽转向抑制干扰，提升信号质量。
19.7-dBm OP1 dB, 20.4-dBm P SAT, 30.6% peak PAE at 29 GHz, 29.8-dBm EIRP 1 dB
JSSC 2024第10期MemorySRAMCIM
A 28-nm 36 Kb SRAM CIM Engine With 0.173 µm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications Chenyang Zhao , Jinbei Fang, Xiaoli Huang, Deyang Chen, Zhiwang Guo, Jingwen Jiang , Jiawei Wang
28纳米36Kb SRAM存内计算引擎，采用0.173µm² 4T1T单元，支持自加载0权重更新。
28nm CMOS, 263.1/412.1 TOPS/W (FF/BP), 2.5/4.9 TOPS/mm² (FF/BP)
JSSC 2024第10期RF & WirelessEqualizerPAM-4
A 4 × 112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics
一款4×112 Gb/s硅光收发芯片组，用于线性驱动共封装光学应用。
180nm SiGe BiCMOS, 35GHz带宽, 112Gb/s PAM-4, 4.8pJ/bit(OTX), 2.95pJ/bit(ORX)
JSSC 2024第10期Power ManagementLDO
A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3 Jinook Jung , Jun-Han Choi , Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong
提出基于翻转电压跟随器的快速LDO，4ns建立时间，适用于HBM3内存，减少电源抖动。
4ns建立时间，40mV下冲，46mV过冲，20pF负载电容，0.0061mm²面积
JSSC 2024第10期Digital Circuits
A 73.8k-Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition Tzu-Wei Tong, Tai-Jung Chen , Yi-Yen Hsieh , and Chia-Hsiang Yang
一款用于脑模式识别的低功耗SVM学习加速器，采用CP-SVM算法和硬件优化，显著提升能效。
40nm CMOS, 0.85V, 40MHz, 9.68mW, 73.8k inference/mJ
JSSC 2024第10期RF & WirelessEnergy Harvesting
A 92.7%-Efficiency 6.78-MHz Energy-Resuscitating Resonant Regulating Rectifier With Dual Outputs for Wirelessly
提出一种能量复苏谐振调节整流器（ER4），用于无线功率传输系统，实现高效率双输出电压调节。
92.74%峰值效率，107.5mW输出功率，6.78MHz载频，1-4.5V可调电压
JSSC 2024第10期Power Management
A BW-Extended Fourth-Order Gain-Boosted N-Path Filter Employing a Switched gmC N
采用开关gm-C网络的带宽扩展四阶增益提升N路径滤波器，具有高线性度和宽通带特性。
65nm CMOS, 10.7-12.7dB增益, 5.3-6.2dB噪声系数, 18.2dBm OOB-IIP3, 50MHz通带带宽, >50dB阻带抑制, 11.1-15.9mW功耗, 0.083mm²面积
JSSC 2024第10期RF & WirelessPower Amplifier
A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS
提出一种紧凑型E波段负载调制平衡功率放大器，采用耦合传输线输出网络，显著提高效率和输出功率。
峰值功率附加效率（PAE）34.9%，饱和输出功率（Psat）22.1-dBm，OP1dB 21.1-dBm，最大功率增益17.8-dB
JSSC 2024第10期RF & WirelessLNA
A Compact Millimeter-Wave Reconfigurable Dual-Band LNA With Image-Rejection in 28-nm Bulk CMOS for 5G Applications Ning-Zheng Sun
一种用于5G毫米波应用的可重构双频带低噪声放大器，具有高图像抑制比和紧凑尺寸。
28nm CMOS, 14mW, 18.1/18.9dB gain, 3.5dB NF, 32.7dBc IRR
JSSC 2024第10期Power ManagementBuck Converter
A Cross-Coupled Hybrid Switched-Capacitor Buck Converter With Extended Conversion Range and Enhanced DCR
一种交叉耦合混合开关电容降压转换器，优化宽电压转换比下的电感平均电流降低。
180nm BCD, 2.7∼4.2V输入, 1∼1.8V输出, 4.2A最大负载, 91%峰值效率
JSSC 2024第10期Power ManagementNeural Network Accelerator
A Fully Integrated Nine-Ratio Switched-Capacitor Converter With Overlapped-Conversion-Ratio Modulation for IoT Applications
一款全集成九比率开关电容转换器，适用于物联网应用，具有高功率密度和转换效率。
87%峰值效率，最大输出功率421mW，输入电压2.5-5V，输出电压0.1-3.67V
JSSC 2024第10期RF & WirelessDACEqualizer
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing
一款基于28nm CMOS工艺的全集成D波段收发器，支持QPSK和16-QAM调制，具有混合信号基带处理能力。
28nm CMOS, 24-Gb/s QPSK, 48-Gb/s 16-QAM, TX带宽21 GHz, RX带宽18 GHz, TX Psat 13.1 dBm, TX OP 1 dB 7.5 dBm, RX NF 9.3 dB
JSSC 2024第10期Data ConvertersSAR ADC
A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter A
提出一种高效可调的循环充电浮点放大器，应用于流水线-SAR ADC，实现高能效。
65nm CMOS, 1.2V, 2 MS/s, SNDR 74.0 dB, SFDR 85.5 dB, 72.3 µW
JSSC 2024第10期Clocking & PLLsPLL
A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor Yong-Jo Kim
提出一种可编程抖动的数字Bang-Bang锁相环，通过随机抖动监测和自动带宽控制实现目标抖动调节。
2.88 GHz, 0.26 ps rms jitter, -225 dB FoM
JSSC 2024第10期RF & WirelessRadar
A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-
一款采用级联PLL拓扑的54至69GHz宽带2T2R FMCW雷达收发器，具有温度补偿技术和高集成度。
40nm CMOS, 54-69GHz带宽, RX转换增益67dB调节范围, 10dB噪声系数, TX PSAT 12.8dBm
JSSC 2024第10期Other
A Portable Wideband CMOS NMR Spectrometer for Multinuclear
便携式宽频CMOS NMR光谱仪，支持多核分子指纹识别
输入参考噪声小于1.2 nV/√Hz，带宽1-100 MHz
JSSC 2024第10期RF & Wireless
A Reusable Superheterodyne Dual-Band Down-Conversion Mixer With Hybrid Linearity-Enhanced Technique for 5G Non-Contiguous Multiband NR
提出一种双频段高线性下变频混频器，适用于5G毫米波非连续多频段操作。
IP1dB: 11.32/11.06/9.85 dBm, IIP3: 22.8/23.6/20.8 dBm, LO-to-RF隔离: >32.7 dBc, LO-to-IF隔离: >58.6 dBc
JSSC 2024第10期RF & Wireless
Advisor for several companies, such as Samsung Electronics; LG Elec- tronics, Seoul; SK Hynix, Icheon-si, South Korea; DB HiTek, Bucheon-si, South Korea; and One Semiconductor, Suwon-si. In 2020, he returned to Samsung Electronics and an Executive Vice President of Memory Business Unit. Dr. Yoo was a Technical Committee Member for several international conferences, such as the IEEE International Solid-State Circuits Conference, IEEE VLSI Circuits Symposium, and IEEE European Solid-State Circuits Conference. He was an Associate Editor for the IEEE M ICROWAVE AND WIRELESS COMPONENTS LETTERS .
该论文介绍了多位专家在半导体和电路设计领域的职业经历与研究兴趣。
无
JSSC 2024第10期MemoryEmerging Memory
Algorithm 1 NE Code Example for CONV 1: procedure CONVOLUTION LAYER 2: #Load weights from MRAM to weight cache 3: LD_WEIGHT(addr_MRAM, addr_WeightCache, . . . ) 4: convolution_loop: 5: #Load activation from activation memory to local memory. Then do convolution. 6: MOV(row, col, addr_ActMem, addr_LocalMem, . . . ) 7: CONV(row, col, channel, kernel_size, stride, . . . ) 8: #Register control in NCU for for-loop
论文提出了一种基于MRAM的卷积神经网络加速器设计，优化了权重加载和卷积计算流程。
1.5-kB双端口FFT内存，8-kB乒乓存储器，支持32/64 Mel通道
JSSC 2024第10期Power Management
An Isolated DC–DC Converter Using a Cross-Coupled Shoot-Through-Free Class-D Oscillator With Low EMI Emissions
提出一种低EMI隔离DC-DC转换器，采用交叉耦合无直通Class-D振荡器和电压串联组合变压器。
峰值效率51%，最大输出功率1.2W，满足CISPR-32 Class B标准
JSSC 2024第10期Digital Circuits
Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and
Ayaka是一款多功能Transformer加速器，通过低秩估计和异构优化解决计算瓶颈问题。
无
JSSC 2024第10期Digital Circuits
CIMFormer A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-
CIMFormer是一种基于脉动CIM阵列的Transformer加速器，通过令牌剪枝优化注意力计算。
无
JSSC 2024第10期Other
Cryo-CMOS Dual-Qubit Homodyne Reflectometer Array With Degenerate
提出一种基于低温CMOS的双量子位零差反射计阵列，采用简并参量放大器提升性能。
2 RX通道, 1 TX通道
JSSC 2024第10期Clocking & PLLsClock Generation
Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <−103-dBc Spurious Tones Using Digital
采用数字杂散消除技术的多输出分数频率合成器，实现90飞秒抖动和-103dBc杂散性能。
28nm CMOS, 0.9V, 2.6mW, 0.15mm², 0.5-2.5GHz, 90-fs抖动, -103dBc杂散
JSSC 2024第10期Other
Guike Li was born in Shandong China in 1980
该论文介绍了多位作者在微电子和固态电子学领域的研究背景和兴趣。
无
JSSC 2024第10期Analog Circuits
III C YCLICALLY CHARGED FIA A Operation and Stably Controllable Amplifier Bias P
提出新型CC-FIA，通过分时充电小电容组替代传统大电容，实现稳定可控的放大器偏置。
NC-OVL, NSW, CRES, fSW, IS, VT, VOV等参数控制
JSSC 2024第10期RF & WirelessPower AmplifierLNA
K/Ka-Band Hybrid-Packaged Four-Element Four-Beam Phased-Array Transmitter and Receiver Front-Ends With Optimized Beamforming
本文提出了一种K/Ka波段四元素四波束相控阵收发前端，采用混合封装技术，结合65nm CMOS波束成形器和0.1µm GaAs功率放大器/低噪声放大器。
23.5–26.5 dB增益, 21.2–23.2 dBm P1dB, 26%–30% PAE
JSSC 2024第10期MemoryCIM
LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell
LOG-CIM处理器通过对数量化提升内存计算能效和密度。
28nm CMOS, 0.85V, 120MHz, 192 TOPS/W, 116.4 TOPS/W
JSSC 2024第10期RF & WirelessPAM-4DRAM
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for H
提出一种采用PAM-4调制、数据总线反转和ZQ校准的单端DRAM接口发射机设计，提升能效并降低噪声。
38 Gb/s, 26.16 mW, 0.688 pJ/bit
JSSC 2024第10期Other
VI C ONCLUSION This article demonstrates a hybrid-integrated 112-Gbs SiPh O-TRX
本文展示了一种混合集成的112Gb/s硅光子光收发器，优化功耗并实现紧凑可靠性能。
112Gb/s, 10dB通道损耗
JSSC 2024第12期Analog CircuitsNeural Network Accelerator
A 0.00055% THD + N Class-D Audio Amplifier With Capacitive Feedforward PWM and Wide-Band
提出一种采用电容前馈PWM和宽带线性增强技术的D类音频放大器，显著降低失真和噪声。
THD + N 0.00055% (−105.2 dB), FoM THD + N 2119, 静态电流 0.81 mA
JSSC 2024第12期Clocking & PLLsPLLRadar
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
基于数字PLL的10GHz啁啾信号发生器，采用新型数字预失真算法优化DCO非线性调谐曲线。
28nm CMOS, 21mW功耗, 680MHz/µs斜率, 680MHz带宽, 150kHz RMS频率误差, -116.5dBc/Hz@1MHz相位噪声
JSSC 2024第12期Data ConvertersTime-Interleaved ADCNeural Network Accelerator
A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized
本文介绍了一种12-GS/s 12位4×时间交织ADC，采用全局抖动注入技术实现输入无关的时序偏差校准。
28nm CMOS, 1.2V, 12-GS/s
JSSC 2024第12期Power ManagementBuck ConverterNeural Network Accelerator
A 12-to-1–1.8-V Hybrid DC–DC Converter With a Charge Converging Phase for Inductor
提出一种带电荷汇聚相的混合降压转换器，显著降低电感电流和传导损耗。
12V输入, 1-1.8V输出, 峰值效率95.4%, DCR 10.5mΩ
JSSC 2024第12期Data ConvertersDACNeural Network Accelerator
A 121.7-dB DR and −109.0-dB THD +N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level
提出一种高压无滤波器数字输入D类放大器，动态范围达121.7 dB。
121.7 dB DR, -109.0 dB THD+N, 14 W, 90%效率
JSSC 2024第12期Analog CircuitsDACBandgap Reference
A 14-b BW /Power Scalable Sensor Interface With a Dynamic
一种14位带宽可扩展的传感器接口，采用动态带隙参考和电容偏置浮置逆变放大器技术。
14位分辨率，98 Hz至5.9 kHz带宽，84.5 dB SNDR，1.7–50.8 µW功耗
JSSC 2024第12期RF & WirelessVCONeural Network Accelerator
A 167-µW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double- Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO
一款采用无源正交前端的高效BLE接收器设计
71dB增益,8.5dB噪声系数,20.1dBm OOB-IIP3,71.7dB SFDR
JSSC 2024第12期Data ConvertersSAR ADC
A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm
提出一种新型动态偏置环形放大器，应用于12位400MS/s流水线-SAR ADC，无需偏置校准，具有高增益和低功耗。
12-bit, 400-MS/s, 2.08 mW, 64.4-dB SNDR, 77.6-dB SFDR
JSSC 2024第12期Clocking & PLLsPLL
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid
一种基于功能复用VCO缓冲器的低抖动快速锁定亚采样锁相环，适用于毫米波频率合成。
28nm CMOS, 0.065mm², 26GHz, 48.3fs rms jitter, 19.1mW, -66dBc ref. spur, 55 ref. cycles locking time
JSSC 2024第12期Clocking & PLLsVCO
A 7.5-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120 × Multiplying Factor and 92.3-fs RMS Jitter Including
提出一种低抖动和低参考杂散的75GHz次谐波注入锁定时钟倍频器
28nm CMOS, 7.5GHz, 67.7-fs rms jitter, -56.6 dBc reference spur, 2.33 mW
JSSC 2024第12期RF & WirelessLNATransceiver
A 7.6-mW IR-UWB Receiver Achieving −17-dBm Blocker Resilience With a Linear RF Front-End Anoop
提出一种低功耗线性射频前端，用于兼容802.15.4a/z的IR-UWB接收器，具有高线性度和抗阻塞能力。
22nm FDSOI CMOS, 5-10GHz, 6dB NF, -17dBm blocker resilience, 7.6mW
JSSC 2024第12期Data ConvertersPipeline ADCDAC
A −90-dBFS-IM3, −164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors
一款高性能连续时间流水线ADC，具有低失真和低噪声特性。
16nm FinFET, 6.4GS/s, -90dBFS IM3, -164dBFS/Hz NSD, 700MHz带宽, 703mW功耗
JSSC 2024第12期RF & Wireless
A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter
一种采用非均匀离散时间FIR滤波器的抗阻塞非均匀子采样接收器，可调谐频率陷波并降低ADC要求。
28nm CMOS, 1V, 100MSymbol/s, 42dB blocker rejection, 24mW
JSSC 2024第12期RF & WirelessPower Amplifier
A Chain-Weaver Balanced Power Amplifier With an Embedded ImpedancePower Sensor M
一种具有嵌入式阻抗/功率传感器的毫米波链式平衡功率放大器，提升线性度和增益稳健性。
40nm CMOS, 25.19-dBm PSAT, 16.19% PAE, -30.3dB EVM
JSSC 2024第12期RF & WirelessEnergy Harvesting
A Coupling-Adaptive Wireless Power Transfer System With V oltage-/Current-Mode Receiver and Global Digital-PWM Regulation
一种13.56MHz无线能量传输系统，适用于生物医学植入设备，具有耦合适应性和高效率。
1.8V, 13.56MHz, 72.3% E2E效率, 7.2cm传输距离
JSSC 2024第12期Power ManagementLDO
A Fully Integrated, Domino-Like-Buffered LDO Regulator With High Power-Supply Rejection Across the Full Frequency Spectrum Jun-Gi Lee
提出一种全集成多米诺缓冲LDO稳压器，具有高频谱范围的高电源抑制比。
28nm CMOS, 200mV压差, 10mA负载, 50pF片上电容, 0.012mm²面积
JSSC 2024第12期RF & WirelessPower AmplifierNeural Network Accelerator
A High-Efficiency Envelope-Tracking Supply Modulator Using a Class-G Linear Amplifier and a Single-Inductor Dual-Input-Dual-Output Converter for 5G NR
提出一种用于5G NR功率放大器的高效包络跟踪电源调制器，结合Class-G线性放大器和SIDIDO转换器技术。
65nm CMOS, 1-5V输出摆幅, 200MHz跟踪带宽, 83.4%峰值效率
JSSC 2024第12期Power Management
A Hybrid Single-Inductor Bipolar-Output Converter With a Concise PWM Control for AMOLED Displays
提出一种紧凑型单电感双极输出转换器，用于AMOLED显示，具有高效率和快速瞬态响应。
94.5%峰值效率，3.99 W/mm²片上功率密度，15.32-mm³总片外组件体积
JSSC 2024第12期Clocking & PLLsPLLVCO
A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm
一种低抖动、小面积且支持快速多变量校准的分数N数字锁相环。
88fs抖动，0.12mm²面积，15.7mW功耗
JSSC 2024第12期RF & WirelessPower Amplifier
A Millimeter-Wave Four-Way Doherty Power Amplifier With Over-GHz
本文提出了一种毫米波四路Doherty功率放大器设计，用于提升5G NR信号的能量效率。
47-GHz, 24.0-dBm PSAT, 26.8% PAEPEAK, 13.1% PAE12 dB
JSSC 2024第12期Power ManagementNeural Network Accelerator
A Monolithic 12.7 W/mm 2, 92% Peak-Efficiency Switched-Capacitor DC–DC Converter Using CSCR-First Topology
提出一种新型单片开关电容电压调节器，实现高功率密度和高效率。
12.7 W/mm²峰值功率密度，92%峰值效率
JSSC 2024第12期Other
A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4-ppm/◦C From −20 ◦C to 125 ◦C
提出一种宽温范围内低温度系数的子范围电流参考源，无需芯片校准。
平均TC为11.4-ppm/°C，线性和负载灵敏度分别为365和181 ppm/V，集成噪声38.9 pA rms
JSSC 2024第12期Power Management
A Power-Efficient Single-Mode Buck–Boost DC–DC Converter With Bilaterally Symmetrical Hybrid Topology Dae-Hyeon Kim
提出一种双边对称混合降压-升压转换器，实现高效单模式操作。
180nm CMOS, 2.7-4.2V输入, 3.4V输出, 1A, 96.9%峰值效率
JSSC 2024第12期RF & WirelessPLL
A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving −46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal Jongsoo Lee , Jaehyuk Jang, Wooseok Lee, Bosung Suh, Heeyong Yoo
一款采用14nm FinFET工艺的高线性度Wi-Fi 7三频双并发收发器，实现了-46.1dB的TX EVM性能。
14nm FinFET, -46.1dB TX EVM@7.1GHz, -55.2dBc IPN(双核VCO), 支持4K-QAM 320MHz
JSSC 2024第12期Other
A β-Compensated NPN-Based Temperature Sensor With 01 C 3σ Inaccuracy From 55 C
提出一种基于NPN的高精度CMOS温度传感器，采用β补偿技术，实现±0.1°C的精度。
0.18µm CMOS, 1.4-2.2V, 2.5µA, ±0.1°C (3σ), 200fJ·K²
JSSC 2024第12期Power ManagementLDONeural Network Accelerator
According to the magnitude and polarity (positive or neg- ative) of the differential input, the class-G LA exhibits four operating conditions. Consider the operation of the PLDO as an example. When the differential input is positive but the amplitude is low, the PLDO tends to regulate its outputVDD_AB to a voltage lower than VDDL. However, due to the presence of the diode DP, VDD_AB is clamped to VDDL minus the diode drop. As a result, the input pair of EA P experiences a large voltage difference and turns off the transistor MP, redirecting the current in AB-LA to flow from VDDL via DP rather than
该论文探讨了PLDO在不同输入条件下的工作原理及其在AB-LA电路中的应用。
200 MHz envelope BW, 4 V output swing, 4.5-V supply voltage
JSSC 2024第12期Power Management
An Integrated Dual-Side Series/Parallel Piezoelectric Resonator-Based DC–DC Converter Wen-Chin B. Liu , Student Member , IEEE, Gaël Pillonnet , Senior Member , IEEE, and Patrick P. Mercier , Senior Member , IEEE
提出一种基于双面串并联压电谐振器的混合DC-DC转换器，实现低电压转换比下的高效转换。
峰值效率92.9%（20V转2.2V）
JSSC 2024第12期Other
Arthur Admiraal was born in Noordwijk
论文介绍了三位研究人员的学术背景及研究方向，涉及微型海洋探测机器人、GaN单片功率电子和D类放大器等领域。
无
JSSC 2024第12期RF & Wireless
As depicted in Fig. 1, VSWR variation influences the gain, output compression power levels, and linearity. Therefore, frequency-dependent VSWR leads to gain, power, and EVM deviation over frequency within the modulation bandwidth. This imposes many design challenges through the link and increases total power consumption. For instance, the PA must deliver an average output power (PA VG) to support the specified EIRP. Hence, the required peak power (P Peak) in the presence of VSWR can be calculated as PPeak = PA VG+ PAPR + 1P (1)
VSWR变化影响增益和输出压缩功率，增加设计挑战和功耗。
16波束成形元件，20-dBm峰值功率，30%效率
JSSC 2024第12期Other
Gururaja Kasanadi
多位作者在RF设计、测量及医疗成像硬件开发领域的研究背景介绍。
无
JSSC 2024第12期Power Management
III. C IRCUIT IMPLEMENTATION The circuit diagram of the converter is depicted in Fig. 4, integrating all power switches along with their corresponding gate drivers and level shifters onto a single die using 180 nm BCD technology. On the other hand, all passive components, including the PR, flying capacitors, and bootstrap capacitors, are implemented off-chip. Additionally, due to the complexity of the control timing, off-chip digital control is utilized. A. Floating Gate Driving Strategy In this design, all of the power switches in the DSPPR
该论文提出了一种采用180nm BCD技术的浮动栅驱动策略，用于多电源开关的集成电路设计。
180nm BCD技术
JSSC 2024第12期Other
Implementation and Application of Harmonic Reset Switching in
本文提出了一种在硬开关无源混频器中实现谐波抑制的合成方法。
34.8–64.5 mW, 0.25–4 GHz, 0.68 mm²
JSSC 2024第12期RF & Wireless
To simplify the analysis, assuming M3 and M4 to be perfect complementary pair as well gives iM3,NL2 = iM4,NL2 = iM34,NL2. Now, the second-order components io,m,NL2 and io,p,NL2 respectively of io,m and io,p are equal and can be written as follows: io,m,NL2 = io,p,NL2 = io,pm,NL2 = iM34,NL2 × α1 + iM34,NL2 × α2. (14) The first-order components io,m,L and io,p,L respectively of io,m and io,p can be written as follows: io,m,L = −io,p,L = io,pm,L = Gm × vi × (1 − α1) (15)
分析LNA拓扑结构的噪声性能，提出简化假设并比较不同结构的噪声电流。
噪声电流分析，Gm值计算
JSSC 2024第12期Other
VI. C ONCLUSION This work presents an NPN-based temperature sensor implemented in 0.18- µm CMOS that achieves both state- of-the-art one-point trimmed accuracy and energy efficiency while occupying a small area. A compact NPN-based front end is proposed along with an efficient circuit implementation to remove β errors introduced by the NPNs. Applying tech- niques, such as DEM, chopping, and resistor ratio calibration, along with a PTAT trim results in an accuracy of ±0.1 ◦C (3σ ) from −55 ◦C to 125 ◦C. Furthermore, the sensor achieves
提出一种基于NPN的高精度温度传感器，具有小面积和低功耗特性。
±0.1°C精度（-55°C至125°C），200fJ·K²分辨率FoM，面积0.07mm²