JSSC 2020 — ISSCC & JSSC 知识库

JSSC 2020第1期Clocking & PLLsDLLEqualizer

A 1.1-V 10-nm class 6.4-Gb/s/pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx Dongkyun Kim, Minsu Park , Sungchun Jang, Jun-Y ong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han, Kibong Koo, Y ongmi Kim, Dong Uk Lee, Jaein Lee, Kihun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jongsam Kim, Seungwook Oh, Dain Im, Y ongsung Lee, Mingyu Park, Jonghyuck Choi

10nm级CMOS工艺下1.1V 6.4Gb/s/pin 16Gb DDR5 SDRAM，性能与功耗优于DDR4。

1.1V, 6.4Gb/s/pin, 16Gb

JSSC 2020第1期MemoryNeural Network Accelerator

A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efﬁcient

提出一种基于时间域的全数字CNN引擎，采用双向存储器延迟线实现高效卷积运算。

40-nm CMOS, 537 mV, 12.08 TOPS/W, 0.365 GOPS

JSSC 2020第1期RF & WirelessEqualizerPAM-4

A 128-Gb-s 13-pJ-b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

14nm CMOS FinFET技术实现的128Gb/s PAM-4发射机，具有可重构3抽头FFE和高效能设计。

128 Gb/s, 1.33 pJ/b, 1-V ppd输出幅度

JSSC 2020第1期MemoryFlash Memory

A 133-Tb 4-Bit-Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology

一款具有133-Tb容量、4位元存储单元的3D闪存，采用96层字线技术，实现8.5 Gb/mm²的高密度存储。

133-Tb容量, 4-bit/cell, 96-WL-layer, 8.5 Gb/mm²

JSSC 2020第1期RF & WirelessEqualizer

A 161-mW 56-Gb-s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-

14nm FinFET工艺下，实现56Gb/s速率、161mW功耗的DMT接收器数据路径。

56 Gb/s, 161 mW, 1.2 pJ/b (DSP), 2.9 pJ/b (RX), BER < 2e-4

JSSC 2020第1期Digital Circuits

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications Y utaka Y amada , Member , IEEE, Toru Sano, Y asuki Tanabe, Y

一款面向ADAS应用的高性能低功耗异构SoC，集成DNN加速器和ISP，具备高可靠性设计。

16nm工艺, 94.52mm²面积, 20.5TOPS算力, 9.78W功耗

JSSC 2020第1期RF & WirelessDACPAM-4

A 243-mW 1.25–56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET

一款基于ADC-DAC的7nm FinFET技术收发器，支持3.5-56 Gb/s PAM-4，功耗仅243mW。

56 Gb/s PAM-4, 243 mW, 4.3 pJ/b

JSSC 2020第1期Digital CircuitsProcessor/CPU

A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D

一款28纳米汽车闪存微控制器，支持虚拟化辅助处理器，满足下一代汽车架构需求。

28nm CMOS, 600MHz, 0.52W

JSSC 2020第1期MemorySRAM

A 28-nm Compute SRAM With Bit-Serial Logic/ Arithmetic Operations for Programmable In-Memory Vector Computing Jingcheng Wang , Student Member , IEEE,X i a o w e iW a n g, Student Member , IEEE, Charles Eckert , Student Member , IEEE, Arun Subramaniyan , Student Member , IEEE

提出一种28纳米混合内存计算SRAM，支持多种位宽和运算类型，适用于物联网处理器。

28nm CMOS, 1.1V, 475MHz, 30 GOPS, 1.4 GFLOPS, 0.56 TOPS/W (8-bit乘法), 5.27 TOPS/W (8-bit加法)

JSSC 2020第1期MemoryCIM

A2 × 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing- In-Memory Approach for Solving Large-Scale Combinatorial

开发了首个基于内存计算方法的2×30k自旋多芯片CMOS退火处理器，用于解决大规模组合优化问题。

40nm CMOS, 22μs退火时间, 比传统CPU快2.6×10^4倍

JSSC 2020第1期Other

A 65-nm 8-to-3-b 1.0–0.36-V 9.1–1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating

提出一种65nm混合数字模拟信号计算平台，支持群机器人算法，能效随数据路径分辨率可调。

65nm CMOS, 峰值能效9.1 TOPS/W（3b）至1.1 TOPS/W（8b）

JSSC 2020第1期Digital Circuits

A 65-nm Neuromorphic I mage Classiﬁcation Processor With Energy-Efﬁcient Training Through Direct Spike-Only Feedback Jeongwoo Park, Student Member , IEEE, Juyun Lee, Student Member , IEEE

提出一种65nm工艺的神经形态图像分类处理器，实现高效能训练。

236 nJ/image, 97.83%分类准确率

JSSC 2020第1期Wireline I/ODRAM

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With V arious High-Speed and Low-Power Techniques Kyung-Soo Ha , Chang-Kyo Lee , Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Y oung-Hwa Kim, Y oung Hoon Son, Byongwook Na, Seungseob Lee, Y oun-Sik Park, Hyuck-Joon Kwon, Tae-Y oung Oh, Y oung-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, and Jung-Bae Lee

本文介绍了一种采用1xnm DRAM工艺的8Gb LPDDR5 SDRAM，通过多种高速和低功耗技术实现7.5 Gb/s/pin的带宽。

7.5 Gb/s/pin, 8-Gb, 21% read power reduction, 33% write power reduction, 25% self-refresh power reduction

JSSC 2020第1期Other

A Self-Regulated and Reconﬁgurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization Dai Li , Student Member , IEEE, and Kaiyuan Y ang , Member , IEEE

提出一种65nm CMOS技术的可重构物理不可克隆函数设计，具有高稳定性和低能耗。

65nm CMOS, 0.7-1.4V, 0.00182% BER, 15.3 fJ/bit

JSSC 2020第1期Digital Circuits

A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal O

通过动态电压调节和自适应体偏置技术实现物联网处理器能量最优运行

6.4 pJ/cycle @0.55V/500kHz, 能效偏离最优值<4.6%(-20°C~125°C)

JSSC 2020第1期MemorySRAM

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge P

提出一种基于双8T SRAM的存内计算单元宏，用于多比特CNN边缘AI处理，提升能效和带宽。

55nm工艺, 5ns访问时间, 37.5-45.36 TOPS/W能效

JSSC 2020第1期MemoryNeural Network AcceleratorCIM

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Y u Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Y uan Huang, Ting-Wei Chang, Tung-Cheng Chang, Hui-Y ao Kao, Y en-Cheng Chiu, Chun-Ying Lee, Y a-Chin King , Chrong-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh

提出基于1Mb ReRAM的内存计算宏，支持多比特输入和权重，实现高效MAC操作。

55nm工艺, 14.6ns MAC延迟, 53.17 TOPS/W能效

JSSC 2020第1期OtherDAC

Sequence-Coded Multilevel Signaling for High-Speed Interface

提出一种32Gb/s序列编码多电平信号传输技术，通过自收敛简化网格结构实现高效能PAM-4/PAM-5调制。

32Gb/s, 2.6pJ/bit, 30dB损耗补偿, 52mW接收功耗

JSSC 2020第2期Power Management

A 0.3 lx–1.4 Mlx Monolithic Silicon Nanowire Light-to-Digital Converter With Temperature-Independent Offset Cancellation Cyuyeol Rhee , Junyoung Park, Student Member , IEEE

本文介绍了一种基于硅纳米线的单片光数字转换器，具有低噪声和高动态范围。

0.18µm CMOS, 235 fA/√Hz, 106.7动态范围, 0.3 lx至1.4 Mlx

JSSC 2020第2期Power ManagementLDONeural Network Accelerator

A 10-mA LDO With 16-nA IQ and Operating From 800-mV Supply

提出一种低静态电流、低电压工作的LDO稳压器，适用于低功耗应用。

55nm CMOS, 800mV, 16nA IQ, 10mA负载电流

JSSC 2020第2期Data ConvertersSAR ADCPipeline ADC

A 125-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

提出一种SAR辅助噪声整形流水线ADC，突破现有SAR ADC的速度瓶颈。

65nm CMOS, 1.2V, 125MHz带宽, 77.1dB SNDR, 4.5mW

JSSC 2020第2期Medical & BioBiosignal

A 13.9-nA ECG Ampliﬁer Achieving 0.86/0.99 NEF/PEF Using AC-Coupled OTA-Stacking Somok Mondal, Student Member , IEEE, and Drew A. Hall , Senior Member , IEEE

提出一种用于植入式传感器的超低功耗ECG放大器，采用AC耦合OTA堆叠技术提升噪声和功率效率。

13.2 nW (三堆叠版本), 18.7 nW (五堆叠版本), NEF 0.86, PEF 0.99

JSSC 2020第2期Digital Circuits

A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control Shuo-An Huang, Student Member , IEEE, Kai-Chieh Chang, Horng-Huei Liou, and Chia-Hsiang Y ang , Senior Member , IEEE

一款用于癫痫发作控制的19mW SVM处理器，支持片上主动学习

96.6%检测准确率，0.28/h误报率，0.71s延迟，1.9mW功耗

JSSC 2020第2期RF & WirelessNeural Network Accelerator

A 292-Gbps per W and 043-Gbps per MG Flexible and Scalable CGRA-Based Baseband P

提出基于动态粗粒度可重构阵列的基带处理器，支持大规模MIMO检测的高灵活性和可扩展性。

28nm CMOS, 292Gbps/W, 043Gbps/MG

JSSC 2020第2期RF & Wireless

A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques Yang-Hang Fan , Student Member , IEEE, Ankur Kumar , Student Member , IEEE, Takayuki Iwai

一款32-Gbps同步双向收发器，采用新型电压模式驱动器和自适应回声消除系统，实现低功耗高效数据传输。

32-Gb/s, 1.83 mW/Gb/s, 10.2-dB loss补偿, BER <10^-12

JSSC 2020第2期RF & Wireless

A 6.5–8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efﬁciency and Energy Detection Haixin Song ,D a n gL i u , Yining Zhang

本文提出了一种用于移动认证与位置验证的脉冲收发器架构，采用飞行时间测量方法抵御中继攻击。

65nm CMOS, 6.0 mW, -69 dBm sensitivity, 2.0 cm ranging accuracy, 20 ns demodulation latency

JSSC 2020第2期Data ConvertersDAC

A 766-dB-SNDR 50-MHz-BW 292-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity T

提出一种双环路噪声耦合辅助的连续时间坚固多级噪声整形调制器，无需多位数模转换器线性化技术。

28nm CMOS, 1.2V/1.5V供电, 1.2GHz采样率, 50MHz带宽

JSSC 2020第2期Clocking & PLLsPLLNeural Network Accelerator

A 951-fs rms Period Jitter 3.2% Modulation Range In-Band Modulation Spread-Spectrum Clock Generator Hyuk Sun , Student Member , IEEE, Kazuki Sobue

提出一种基于带内相位调制的扩频时钟发生器，实现低抖动和宽调制范围。

0.18-µm CMOS, 1.8V, 352MHz输出频率, 951-fs rms周期抖动, 9.98mW功耗

JSSC 2020第2期Data Converters

A BJT-Based Temperature-to-Digital Converter With a ±0.25◦C3 σ-Inaccuracy From − 40◦Ct o +180◦C Using Heater-Assisted V oltage Calibration

一种基于BJT的温度数字转换器，通过加热辅助电压校准实现高精度。

±0.25°C 3σ精度，-40°C至+180°C范围，0.15mm²面积，1.8V供电

JSSC 2020第2期RF & Wireless

A Batteryless Padless Crystalless 116 μm× 116 μm “Dielet” Near-Field Radio With On-Chip

一款无电池、无引脚、无晶振的116微米微型近场无线电芯片，采用双音技术提升上行信号质量。

116µm × 116µm, 65nm CMOS

JSSC 2020第2期RF & WirelessPLLNeural Network Accelerator

A CMOS 7681-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp G

65nm CMOS工艺的76-81GHz FMCW雷达收发器，支持MIMO处理与可重构调频波形。

65nm CMOS, 4GHz带宽, 110kHz RMS频率误差, 13.4dBm TX输出功率, 15.3dB RX噪声系数

JSSC 2020第2期RF & Wireless

A CMOS Two-Element 170-GHz Fundamental-Frequency Transmitter With Direct RF-8PSK

一款采用65nm CMOS工艺的170GHz基频发射器，实现直接RF-8PSK调制，传输速率达15Gb/s。

15 Gb/s, EVM -14.8 dB, EIRP 4 dBm, 560 mW

JSSC 2020第2期Other

A Discrete-Time Audio Modulator Using Dynamic Ampliﬁer With Speed Enhancement and Flicker Noise Reduction Techniques Song Ma

一种采用动态放大器速度增强技术的离散时间音频ΔΣ调制器

65nm CMOS, 0.8V, 49μW, 91dB DR, 89.6dB SNDR

JSSC 2020第2期RF & Wireless

A Reconfigurable Spectrum-Compressing Receiver for Non-Contiguous Carrier Aggregation in CMOS SOI

提出一种可重构频谱压缩接收器，用于非连续载波聚合，支持快速信道切换。

100 MHz–1.4 GHz, 49 dB out-of-band rejection, −86 dBm sensitivity, 0.55 mm², 23.1 mW

JSSC 2020第2期Data ConvertersPLLVCO

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-

提出一种基于VCO的第二阶连续时间ΔΣ ADC，采用改进DPLL结构，实现高效能转换。

40nm CMOS, 1.1V, 260 MS/s, 69.4 dB SNDR, 5.2-MHz带宽, 0.86 mW

JSSC 2020第2期Data ConvertersSAR ADCPipeline ADC

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Ampliﬁer Wenning Jiang, Student Member , IEEE,Y a nZ h u , Member , IEEE

一种温度稳定的12位1GS/s SAR辅助流水线ADC，SNDR超过60dB。

28nm CMOS, 1V, 1GS/s, 60dB SNDR, 7.6mW

JSSC 2020第2期OtherNeural Network Accelerator

An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization Hongying Wang , Student Member , IEEE

提出一种用于物联网无线网络的事件驱动准电平交叉Δ调制器ADC，具有自适应分辨率。

28nm CMOS, 1.42MHz信号带宽, 53dB峰值SNDR, 205µW功耗, 0.0126mm²面积

JSSC 2020第2期Image Sensors

Combined In-Pixel Linear and Single-Photon Avalanche Diode Operation With Integrated Biasing for Wide-Dynamic-Range Optical Sensing Hyunkyu Ouh , Student Member , IEEE, Boyu Shen, Student Member , IEEE, and Matthew L. Johnston , Member , IEEE

提出一种结合线性和单光子雪崩二极管操作的全集成光学传感器阵列，具有宽线性动态范围。

129-dB DR, 20 Hz双模式帧率

JSSC 2020第2期Digital CircuitsProcessor/CPU

Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS

一种自主调节供电电压以实现最小总能耗的架构，适用于近阈值和亚阈值电压操作。

65nm CMOS, 0.38-0.58V, MEP跟踪误差<5mV

JSSC 2020第2期Power ManagementLDO

Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO

通过数字低压差稳压器增强加密引擎的功耗和电磁侧信道分析抗性。

130nm CMOS, 25× TVLA泄漏降低, 3579×/2182×/500× MTD提升

JSSC 2020第2期RF & Wireless

High Linearity Transmit Power Mixers

通过基带电流反馈提升发射混频器线性度的设计

130nm: ACLR -41.3/-40.4/-37.6 dBc (LTE5/10/20), 噪声-148.6 dBc/Hz @80MHz, CIM3 -53.8 dBc; 65nm: 4dBm输出功率(EDR), 50.5mW功耗

JSSC 2020第2期Digital Circuits

STICKER- An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS

STICKER是一款高效能卷积神经网络处理器，通过充分利用稀疏性提升能效。

65nm CMOS, 峰值能效62.1 TOPS/W

JSSC 2020第2期OtherPLLRadar

Table of contents

IEEE JSSC期刊论文涵盖了多种CMOS技术应用，包括雷达收发器、无电池射频芯片、可重构接收器等。

多种性能指标，如76–81-GHz雷达、116 μm × 116 μm芯片尺寸、12.5-MHz带宽等

JSSC 2020第3期Clocking & PLLsPLL

A 0025-mm2 08-V 785-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- --

提出一种基于VCO的传感器读出电路，采用混合PLL-ΣΔ调制结构，实现高能效和小面积。

40nm CMOS, 0.8V, 78.5dB SNDR, 10kHz带宽, 4.68μW, 0.025mm²

JSSC 2020第3期OtherEnergy HarvestingNeural Network Accelerator

A 1-10-MHz Frequency-Aware CMOS Active Rectifier With Dual-Loop Adaptive Delay C

一种适用于1-10MHz频率范围的双环自适应延迟补偿CMOS有源整流器，用于生物医学植入物的电容无线能量传输。

0.18μm CMOS, 1-10MHz, >84.4% PCE (峰值91.5%), >88.6% VCR (峰值95.1%), 最大输出功率232mW

JSSC 2020第3期Data ConvertersSAR ADC

A 10-bit 120-MS-s SAR ADC With

提出一种参考电压纹波消除技术，用于高速SAR ADC，通过反向耦合路径抵消纹波影响。

10-bit, 120-MS/s, 55 dB SNDR, 3-pF decoupling capacitor

JSSC 2020第3期RF & WirelessSAR ADCTDC

A 128-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer

本文展示了一种基于ADC的接收器，支持NRZ/PAM4调制，集成了IIR均衡器，采用65nm CMOS工艺，能效为2.43-pJ/b。

65nm CMOS, 12.8-Gbaud PAM4, 2.43-pJ/b, 4.84 peak ENOB, 36.3 mW, 0.24 mm²

JSSC 2020第3期Clocking & PLLsPLLPAM-4

A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

一款14GHz Bang-Bang数字PLL，集成抖动低于150fs，用于高速有线通信。

14GHz, 143-fs rms抖动, 56-Gb/s PAM-4, 40mW功耗

JSSC 2020第3期Data ConvertersSAR ADC

A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration Mingqiang Guo , Student Member , IEEE, Jiaji Mao, Student Member , IEEE

提出一种16GS/s、122mW的七/八路分割时间交织SAR ADC，实现54.2dB SNDR。

28nm CMOS, 1.6 GS/s, 54.2-dB SNDR, 67.1-dB SFDR, 2.5-GHz ERBW

JSSC 2020第3期OtherVCO

A 1770- --mu- m2 Leakage-Based Digital Temperature Sensor With Supply Sensitivity Suppression in 55-nm CMOS

一种基于漏电流的数字温度传感器，具有低电源敏感性和小面积特性。

1770 μm², 0.8-1.3V, ±0.70°C(3σ)

JSSC 2020第3期Other

A 1.8-GHz Near-Field Dielectric Plethysmography Heart-Rate Sensor With Time-Based

提出一种低功耗近场介电体积描记心率传感器，采用18GHz边缘电场检测心率信号。

0.18-µm CMOS, 20.1 µW, 100 Hz采样率, 1.64 bpm误差

JSSC 2020第3期Clocking & PLLsVCO

A 230-GHz High-Power and Wideband Coupled Standing Wave VCO in 65-nm CMOS

65nm CMOS工艺下实现230GHz高功率宽带耦合驻波VCO，最大输出功率3.4dBm。

219–238 GHz (8.35% tuning range), 3.4-dBm max output power, -105.8 dBc/Hz phase noise @10MHz, 195 mW @1.5V

JSSC 2020第3期Clocking & PLLs

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide A VFS System

提出一种双向零延迟自适应时钟电路，用于28nm宽范围AVFS系统，显著降低功耗并减少吞吐量损失。

28nm CMOS, 38.6%–69.4% power gains at near threshold

JSSC 2020第3期RF & WirelessPower Amplifier

A CMOS 12-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With B

本文提出了一种采用CMOS工艺的12V混合电流和电压模式三路数字Doherty功率放大器，具有内置大信号相位非线性补偿功能。

38.5%峰值漏极效率，22.4dBm饱和输出功率，3.4-/9.3-dB PBO下32.1%/18.7%效率

JSSC 2020第3期Power ManagementLDO

A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM

提出一种基于动态高阻抗电荷泵的LDO，具有数字LDO特性，响应速度快且功耗低。

6.9ns响应时间/65ns稳定时间，4.9µA静态电流，<15mV输出纹波，1µA–105mA负载范围

JSSC 2020第3期Clocking & PLLsPLL

A Fractional- N PLL With Space–Time Averaging for Quantization

提出一种时空平均技术，显著降低分数N锁相环的量化噪声

2.4-GHz, 40-nm CMOS, 相位噪声降低10dB（1MHz偏移）和21dB（10MHz偏移）, 集成rms抖动从9.55ps降至2.26ps

JSSC 2020第3期Data Converters

A Highly Linear OTA-Less 1-1 MASH VCO-Based ADC With an Efﬁcient Phase Quantization Noise

提出一种高效技术，实现高线性VCO基1-1 MASH ΔΣ ADC，无需OTA和功耗大的线性化方法。

82.7/88.7/80.3/79.7 dB DR/SFDR/SNR/SNDR, 2 MHz BW, 1.248 mW功耗, 0.9V供电

JSSC 2020第3期Clocking & PLLsVCOCrystal Oscillator

A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques Amr Khashaba , Student Member , IEEE

提出一种基于环形振荡器的低噪声频率合成器，通过多相生成和组合技术降低抖动积累引起的相位噪声。

65nm CMOS, 54MHz输入, 5GHz输出, 245fs rms抖动, 8.2mW总功耗

JSSC 2020第3期Other

A Physical Unclonable Function With Bit Error Rate - 23 --times- 10-8 Based on C

基于接触形成概率的物理不可克隆函数(PUF)，具有极低误码率和高可靠性。

0.13-µm CMOS, 49.99% uniqueness, 0.99973 entropy, bit error rate 23×10^-8

JSSC 2020第3期Other

A Symmetric Modiﬁed Multilevel Ladder PMIC for Battery-Connected Applications Abdullah Abdulslam , Student Member , IEEE, and Patrick P . Mercier , Senior Member , IEEE

本文提出一种对称改进多级梯形转换器，可直接从锂离子电池电压转换为SoC兼容电压，使用低压MOSFET，效率高达90%。

峰值效率90%，峰值功率密度0.52 W/mm²，转换比16.7×

JSSC 2020第3期Power ManagementBoost Converter

A Three-Level Boost Converter With Full-Range Auto-Capacitor-Compensation Pulse Frequency Modulation Wen Chuen Liu , Student Member , IEEE,P e iH a nN g

提出一种三电平升压转换器，采用自动电容补偿脉冲频率调制控制器，实现高效电压转换。

0.3-3.0V输入, 2.4-5.0V输出, 96.8%峰值效率, 83mA峰值输出电流, 8倍升压比

JSSC 2020第3期Data Converters

A Wearable Real-Time CMOS Dosimeter With Integrated Zero-Bias Floating Gate Sensor and an 861-nW 18-Bit Energy-Resolution Scalable Time-Based Radiation to Digital Converter Baibhab Chatterjee , Student Member , IEEE

首款单片集成CMOS可穿戴实时辐射剂量计，具有高灵敏度和低功耗特性。

14Ω/rad灵敏度, 18-bit分辨率, 861nW@1S/s, 3.29pJ/转换步

JSSC 2020第3期OtherVCO

A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm

提出一种28nm CMOS工艺下宽范围、抗环境变化的物理不可克隆函数(PUF)，通过延迟单元拓扑和在线校准系统显著提升稳定性。

28nm CMOS, 0.4-1.3V, -40至125°C, 最差误码率0.55%

JSSC 2020第3期Wireline I/OEqualizer

An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication—Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit Yusang Chun , Student Member , IEEE

提出一种无需均衡器的ISI弹性Dicode编码方案，用于低带宽有线通信。

65-nm CMOS, 2.56-2.66 pJ/bit, 13.6-16 Gb/s, BER < 10^-12

JSSC 2020第3期Clocking & PLLsPLLVCO

An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO

一种采用两级架构的低噪声毫米波频率合成器，具有鲁棒锁定参考采样技术。

45nm PDSOI CMOS, 35.84GHz, 251-fs抖动, 20.6mW

JSSC 2020第3期Other

Design and Analysis of a Microwave-Optical Dual

提出一种高灵敏度与选择性的微波-光学双模态生物分子传感器

28nm CMOS, 0.2 ppm/√Hz频率灵敏度, 11.5mW功耗, 500/s暗计数率, 300ps定时抖动

JSSC 2020第3期Power ManagementLDO

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR

分布式LDO微调节器网络实现亚微秒级动态电压频率调节和IR降补偿

95.2%峰值能效，99.1%电流效率，82.3W/mm²功率密度

JSSC 2020第3期Power Management

Errata Erratum to “A Flying-Inductor Hybrid DC–DC Converter for 1-Cell and 2-Cell Smart-Cable Battery Chargers”

IEEE JSSC期刊论文勘误，更正作者Hanh-Phuc Le的职位信息。

无

JSSC 2020第3期Digital Circuits

Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit

提出一种基于机器学习的抗侧信道攻击方法，通过优化汉明距离概率保护加密电路。

28-nm CMOS, 1.5 million traces resistance, 38% power overhead, 36% area overhead

JSSC 2020第3期Digital Circuits

OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers

OPTIMO是一款65纳米工艺的16位可编程空间阵列处理器，用于分布式优化问题求解。

65nm CMOS, 279 GOPS/W

JSSC 2020第4期RF & WirelessTime-Interleaved ADCEqualizer

112-Gb-s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels

采用10nm FinFET工艺实现的112Gb/s PAM4 ADC基SERDES接收器，支持长距离通信。

112Gb/s, -35dB Nyquist通道, 1e-6预FEC BER

JSSC 2020第4期Digital Circuits

A 032-128 TOPS- Scalable Multi-Chip-Module-Based Deep Neural Network Inference A

基于多芯片模块的可扩展DNN加速器，实现高效能推理

16nm工艺, 1.29-TOPS/mm²面积效率, 0.11 pJ/op能效, 127.8 TOPS峰值性能

JSSC 2020第4期RF & Wireless

A 102-pJ-b 2083-Gb-s-Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET

一种采用CNRZ-5信号的高能效超短距离收发器，具有低敏感性和高抗噪性。

16nm FinFET, 1.02 pJ/b, 20.83 Gb/s/wire, 417 Gb/s/mm

JSSC 2020第4期Other

A 4900- --mu- m2 839-Mb-s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS W

本文提出了一种抗侧信道攻击的AES-128硬件加速器，采用随机字节顺序洗牌和线性掩码技术，显著提升了安全性。

14nm CMOS, 750mV, 839Mb/s, 11mW

JSSC 2020第4期Data ConvertersCMOS Image Sensor

A 640 --times- 640 Fully Dynamic CMOS Image Sensor for Always-On Operation

介绍了一种640×640全动态CMOS图像传感器，适用于常开操作。

110-nm CMOS, 0.3% peak non-linearity, 6.1 e-rms RN, 67-dB dynamic range, 2.1 mW at 44 fps, 140 µW at 5 fps

JSSC 2020第4期RF & WirelessEnergy Harvesting

A 678-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage C

一款6.78MHz单级无线充电器，采用CC-CV充电技术，实现高效低成本充电。

0.35µm CMOS, 8mm², 1.5A, 92.3%峰值效率

JSSC 2020第4期Other

A 7-nm 4-GHz Arm 1-Core-Based CoWoS1 Chiplet Design for High-Performance Computing Mu-Shan Lin , Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Y u-Chi Chen, Sandeep

采用7nm工艺和CoWoS技术的双芯片组八核处理器，实现4GHz高频操作和高速数据传输。

7nm CMOS, 4GHz, 320GB/s, 0.56-pJ/bit, 1.6-Tb/s/mm2

JSSC 2020第4期Power ManagementCharge PumpPLL

A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control Chen-Ting Ko , Ting-Kuei Kuan , Ruei-Pin Shen, and Chih-Hsien Chang

7nm FinFET CMOS PLL设计，采用跟踪保持电荷泵和自动环路增益控制，实现388fs抖动和-80dBc参考杂散。

4.0 GHz, 0.9V, 5.9 mW, 388-fs rms抖动, -80 dBc参考杂散

JSSC 2020第4期Digital Circuits

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconﬁgurable Sparse Matrix–Matrix Multiplication Accelerator Dong-Hyeon Park , Student Member , IEEE, Subhankar Pal , Student Member , IEEE, Siying Feng, Student Member , IEEE, Paul Gao, Student Member , IEEE,J i e l u nT a n ,Student Member , IEEE, Austin Rovinski , Student Member , IEEE

一款40nm CMOS工艺的可重构稀疏矩阵乘法加速器，具有48个异构核心和可重构内存层次结构。

40nm CMOS, 12.6×能效提升, 11.7×带宽效率提升, 17.1×计算密度提升

JSSC 2020第4期Other

A CMOS Temperature Stabilized 2-D Mechanical Stress Sensor With 11-bit Resolution Umidjon Nurmetov , Tobias Fritz, Ernst Müllner, Christopher M. Dougherty, Michael Szelong

采用130nm CMOS工艺设计的2-D应力传感器，具有11位分辨率和66dB动态范围。

11-bit分辨率, 66dB动态范围, 357µW功耗

JSSC 2020第4期Data ConvertersSAR ADCNeural Network Accelerator

A Continuous-Time Zoom ADC for Low-Power

一种用于低功耗音频应用的连续时间缩放ADC

108.1-dB peak SNR, 106.4-dB peak SNDR, 108.5-dB dynamic range, 618 µW power consumption

JSSC 2020第4期Clocking & PLLsPLLClock Generation

A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer With Frequency- Tracking Loop in 65-nm CMOS

提出一种全集成亚太赫兹频率合成器，采用注入锁定倍频器和频率跟踪环路技术

61.2-273.6GHz调谐范围，-95.4dBc/Hz相位噪声，159fs抖动，0.58mm²核心面积

JSSC 2020第4期RF & WirelessOptical I/O

A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators Nandish Mehta , Student Member , IEEE,S e nL i n , Member , IEEE, Bozhi Yin, Student Member , IEEE

45nm SOI CMOS工艺中采用激光转发相干收发器，显著降低激光功率需求并提升接收灵敏度。

10 Gb/s, BER <10^-9, 2.3 pJ/bit, -15.6-dBm OMA灵敏度

JSSC 2020第4期Data ConvertersSAR ADC

A Pipeline SAR ADC With Second-Order

提出一种二阶级间增益误差整形技术，显著降低流水线ADC中的量化泄漏误差。

40nm CMOS, 100MS/s, 12.5MHz带宽, 75.8dB SNDR, 1.54mW功耗, 174.9dB Schreier FoM

JSSC 2020第4期RF & Wireless

A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-

智能隐形眼镜控制器IC，支持双模式无线遥测，低功耗设计。

143 nW功耗，89 dB输入动态范围

JSSC 2020第4期Other

A Time Domain Artiﬁcial Intelligence Radar System Using 33-GHz Direct Sampling for Hand Gesture Recognition Jungwoon Park , Junyoung Jang , Geunhaeng Lee , Hyunmin Koh, Changhwan Kim, and Tae

介绍了一种基于时域AI的33GHz直接采样雷达系统，用于手势识别。

65nm CMOS, 95mW功耗, 93.2%/90.5%识别率

JSSC 2020第4期Image SensorsCMOS Image Sensor

A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7- μm Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation

一款采用65nm BSI工艺的VGA间接飞行时间CMOS图像传感器，具有4-tap 7-µm全局快门像素。

VGA (640×480), 60帧/秒, 160mW功耗, 0.57%深度噪声, 4米工作距离

JSSC 2020第4期Power ManagementLDO

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response Khondker Zakir Ahmed , Harish K. Krishnamurthy

一种基于事件驱动计算控制器的自适应数字LDO稳压器，具有快速瞬态响应。

100 mV droop for 500 mA (2 A/ns di/dt), <20 ns settling times

JSSC 2020第4期Analog CircuitsNeural Network Accelerator

An Energy-Efficient Comparator With

一种采用动态浮动逆变器放大器的能效比较器设计，显著提升能效并降低噪声。

180nm CMOS, 1.2V, 46µV输入噪声, 1pJ/次比较

JSSC 2020第4期Other

Design of a 50-Gb-s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET

16nm FinFET工艺下设计的50Gb/s硅光子光学链路

50Gb/s, BER<10^-12, -10.9dBm OMA, 3.16pJ/bit能效

JSSC 2020第4期Power Management

Direct 48-/1-V GaN-Based DC–DC Power Converter With Double Step-Down Architecture and Master–Slave AO2T Control Dong Yan, Student Member , IEEE, Xugang Ke, Student Member , IEEE,a n dD .B r i a nM a, Senior Member , IEEE

提出一种基于GaN的单级双降压架构48V至1V直流转换器，采用自适应ON-OFF时间控制提升效率。

峰值效率85.4%@100kHz, 79%@250kHz, 56.8%@2MHz

JSSC 2020第4期RF & WirelessPAM-4

Errata Erratum to “A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconﬁgurable 3-Tap FFE in 14-nm CMOS”

关于论文作者照片错误的更正声明

无

JSSC 2020第4期Power ManagementProcessor/CPU

Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW

提出一种支持超宽功率范围的无电池依赖电源管理单元，实现从nW到mW的连续微控制器运行。

180nm CMOS, 1.85nW-1mW功率范围, 0.8mm²片上太阳能电池

JSSC 2020第4期MemoryEmerging MemoryCIM

Liquid Silicon A Nonvolatile Fully Programmable Processing-in-Memory Processor W

Liquid Silicon是一款非易失性全可编程存内计算处理器，结合了FPGA的灵活性和专用加速器的高效性。

650mV低电压操作，1.2V下60.9 TOPS/W神经网络推理，480 GOPS/W基于内容的相似性搜索

JSSC 2020第4期Data ConvertersTDC

Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High T

提出一种直接射频到数字转换器，支持1024-APSK调制，适用于极坐标接收器。

1.94 GB/s, 1024-APSK, 6 GHz, 3.8 mW, 1.1 V

JSSC 2020第4期Other

Table of contents

IEEE JSSC期刊特刊论文合集，涵盖多种前沿芯片设计与传感器技术

11-bit分辨率, 10-µW关键词识别, 33-GHz直接采样, 7-µm全局快门像素

JSSC 2020第4期Power ManagementLDO

V ocell: A 65-nm Speech-Triggered Wake-Up SoC for 10- µW Keyword Spotting and Speaker V eriﬁcation Juan Sebastian P . Giraldo , Steven Lauwereins, Student Member , IEEE, Komail Badami, Student Member , IEEE, and Marian V erhelst , Senior Member , IEEE

一款65nm工艺的超低功耗语音唤醒SoC，支持关键词检测和说话人验证，功耗低至10.6μW。

65nm CMOS, 18.3μW最坏情况功耗, 10.6μW典型实时场景功耗

JSSC 2020第5期Data Converters

A 102.2-dB, 181.1-dB FoM Extended Counting Analog-to-Digital

本文介绍了一种高效能的增量型模数转换器（IADC），采用新颖的电容器缩放技术和扩展计数方案，实现了16位SNDR和17位动态范围。

102.2 dB动态范围，2.04 kHz带宽，25 µW功耗

JSSC 2020第5期OtherLNANeural Network Accelerator

A 1.7-dB Minimum NF, 22–32-GHz Low-Noise Feedback Ampliﬁer With Multistage Noise Matching in 22-nm FD-SOI CMOS

采用22nm SOI-CMOS工艺实现的多级噪声匹配低噪声反馈放大器，最小噪声系数1.7dB，带宽22-32GHz。

22nm SOI-CMOS, 1.7dB NF, 21.5dB gain, 22-32GHz BW, 17.3mW power

JSSC 2020第5期RF & Wireless

A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation

提出一种用于5GNR FR2频段和回程通信的宽带正交数字发射机架构，通过合成阻抗变化补偿提高效率。

28nm CMOS, 1V, 20-32GHz, 峰值输出功率19.02dBm, 峰值效率34.4%

JSSC 2020第5期RF & Wireless

A 24.5–43.5-GHz Ultra-Compact CMOS Receiver Front End With Calibration-Free Instantaneous Full-Band Image Rejection for Multiband 5G Massive MIMO Min-Yu Huang , Student Member , IEEE

本文介绍了一种超宽带24.5-43.5 GHz CMOS接收前端，无需校准即可实现全频段图像抑制。

峰值35.2-dB转换增益，18-dB增益调谐，12-Gb/s 64-QAM信号接收

JSSC 2020第5期Power Management

A 30-GHz CMOS SOI Outphasing Power Ampliﬁer With Current Mode Combining for High Backoff Efﬁciency and Constant Envelope Operation Kang Ning , Student Member , IEEE, Yihao Fang, Navid Hosseinzadeh, Student Member , IEEE,a n d James F. Buckwalter , Senior Member , IEEE

一种30GHz CMOS SOI外推功率放大器，采用电流模式组合实现高效率和低损耗。

45nm CMOS SOI, 40% 6-dB回退效率, 17-dBm峰值输出功率, 50.5%峰值效率, 20 Gb/s比特率

JSSC 2020第5期RF & Wireless

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude C

本文提出了一种39GHz 64单元相控阵收发芯片组，用于5G NR，具有内置相位和幅度校准功能。

65nm CMOS, 53 dBm EIRP, -30.0-dB EVM

JSSC 2020第5期RF & WirelessOptical I/OPAM-4

A 50-Gb-s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS

一款50Gb/s PAM4硅光发射器，采用数字辅助分布式驱动器和混合集成技术。

50Gb/s PAM4, 40nm CMOS, 180nm SOI CMOS

JSSC 2020第5期RF & Wireless

A Code-Domain RF Signal Processing Front End With High Self-Interference Rejection and Power Handling for Simultaneous Transmit and Receive Hussam AlShammary , Student Member , IEEE,C a m e r o nH i l l, Student Member , IEEE, Ahmed Hamza , Student Member , IEEE, and James F. Buckwalter , Senior Member , IEEE

提出了一种具有高自干扰抑制能力的码域射频信号处理前端，采用积分-丢弃N路径滤波器和RF斩波开关技术。

1GHz工作频率，200Mc/s码率，RX功耗18mW，TX功耗<40mW@300Mc/s

JSSC 2020第5期RF & WirelessPower Amplifier

A Coupler-Based Differential mm-Wave Doherty Power Amplifier With

提出一种基于耦合器的差分毫米波Doherty功率放大器，采用阻抗逆变和缩放巴伦结构实现高效负载调制。

未明确提及

JSSC 2020第5期RF & Wireless

A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter-Mixer

提出一种利用新型电容堆叠技术的低功耗抗干扰混频器前端，实现13dB增益。

13dB电压增益，OOB IIP3/IIP2 +25/+66 dBm，5dB噪声系数，600µW功耗，LO=1GHz

JSSC 2020第5期Power ManagementBuck ConverterNeural Network Accelerator

A High-V oltage Dual-Input Buck Converter Achieving 52.9% Maximum End-to-End Efﬁciency for Triboelectric Energy-Harvesting Applications

提出一种用于摩擦电能量收集的高压双输入降压转换器，实现52.9%的最大端到端效率。

70V最大输入电压，52.90%最大端到端效率

JSSC 2020第5期RF & Wireless

A Time-Interleaved Resonant V oltage Mode Wireless Power Receiver With Delay-Based Tracking Loops for Implantable

提出一种基于谐振电压模式的无线充电接收器，采用延迟控制策略实现高效能量转换

13.56MHz工作频率，67.8%接收效率，7mm×7mm接收线圈

JSSC 2020第5期Other

A Wideband Low-Power Cryogenic CMOS Circulator for

首款全集成CMOS循环器，用于低温量子计算平台，具有宽带宽和低功耗特性。

6.5 GHz中心频率，28%分数带宽，2.2 dB插入损耗，2.4 dB噪声系数，18 dB隔离度，2.5 mW核心功耗

JSSC 2020第5期RF & WirelessEnergy Harvesting

A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efﬁciency and Supporting 0.1% Modulation Depth for ASK Demodulation Dawei Y e , Member , IEEE,Y uW a n g , Member , IEEE, Yingfei Xiang, Liangjian Lyu, Student Member , IEEE

一种用于植入式生物医学设备的无线能量与数据传输接收器，通过动态阻抗匹配和低调制深度解调技术实现高效能量转换。

BER 10^-3, 100kb/s数据速率, 75.4% PCE

JSSC 2020第5期RF & Wireless

An 80211ba-Based Wake-Up Radio Receiver With Wi-Fi

集成于Wi-Fi收发器的802.11ba低功耗唤醒接收机，面积0.13mm²，功耗495µW。

0.13mm², 495µW@0.6/0.9V, -92.6dBm灵敏度, -40.5dBm邻道抑制

JSSC 2020第5期Power ManagementNeural Network Accelerator

An 8.2-μW 0.14-mm 2 16-Channel CDMA-Like Capacitance-to-Digital Converter Y

一种采用连续时间沃尔什编码多路复用的16通道电容数字转换器

11.4 ENOB, 482 µs转换时间, 0.51 µW/通道

JSSC 2020第5期Data ConvertersDelta-Sigma ADCVCO

An OTA-Less Second-Order VCO-Based CT --Delta-Sigma- Modulator Using an Inherent

提出一种无OTA的二阶VCO连续时间ΔΣ调制器，利用VCO固有特性实现高效噪声整形。

40nm CMOS, 590μW@330MHz, 68.7dB SNDR/6MHz, 22fJ/step FoM

JSSC 2020第5期RF & WirelessPhased ArrayNeural Network Accelerator

Code-Domain Multiplexing for Shared IF/LO Interfaces in Millimeter-Wave MIMO Arrays Manoj Johnson , Student Member , IEEE, Armagan Dascurcu, Student Member , IEEE, Kai Zhan, Student Member , IEEE, Arman Galioglu, Student Member , IEEE, Naresh Kumar Adepu, Student Member , IEEE, Sanket Jain, Student Member , IEEE

提出了一种码域复用技术，用于毫米波MIMO系统中的共享IF-LO接口。

28 GHz, 65-nm CMOS, 1.2 V, 60 mA, 5.75 mm²

JSSC 2020第5期RF & Wireless

Design and Analysis of Enhanced Mixer-First Receivers Achieving 40-dB-decade RF

提出二阶无源混频优先接收器，提升信道选择性、线性度和噪声性能。

28nm CMOS, OOB IIP3 +33 dBm, 阻塞P1dB +12 dBm, NF 4.4 dB

JSSC 2020第5期Other

Highly Integrated Guidewire Ultrasound Imaging System-on-a-Chip

本文介绍了一种用于血管成像的高度集成导丝超声成像系统芯片。

32–42 MHz发射带宽，32.7–37.5 MHz接收带宽，9.66 nA输入参考噪声

JSSC 2020第5期Other

Information

IEEE JSSC期刊介绍投稿要求和流程，强调集成电路设计与实验验证。

无

JSSC 2020第5期RF & Wireless

Millimeter-Scale Node-to-Node Radio Using a Carrier Frequency-Interlocking IF Receiver for a Fully Integrated 4 × 4× 4m m 3 Wireless Sensor Node Li-Xuan Chuo , Zhen Feng, Student Member , IEEE, Y ejoong Kim

提出一种2.4GHz毫米级节点间通信系统，解决载波频率同步难题。

-94dBm灵敏度, 97µW功耗, -12.6dBm EIRP

JSSC 2020第5期RF & WirelessNeural Network Accelerator

Mixer-First MIMO Receiver With Reconﬁgurable Multi-Port Decoupling and

提出一种支持多端口解耦和匹配的混频器优先MIMO接收机架构，实现动态阻抗调谐和宽带耦合响应。

0.1–3 GHz, 16 mW功耗, 3–6 dB噪声系数, 14–40 dB转换增益

JSSC 2020第5期RF & Wireless

Multi-Mode 60-GHz Radar Transmitter SoC in 45-nm SOI CMOS

45nm SOI CMOS工艺的多模式60GHz雷达发射器SoC，支持CW/FMCW、脉冲和PMCW波形。

45nm SOI CMOS, 54-67GHz, 12.8dBm平均输出功率, 14.7dBm峰值功率, 40GHz雷达信号带宽

JSSC 2020第5期Other

TG-SPP A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS

提出基于传输门的短路径填充方法，减少时序误差检测与校正电路的面积开销。

28nm CMOS

JSSC 2020第6期Analog Circuits

32-mW Ultra-Low-Power 173-207-GHz Amplifier With 130-nm SiGe HBTs Operating in S

采用130nm SiGe HBT工艺实现超低功耗200GHz放大器，功耗仅3.2mW。

130nm SiGe HBT, 1.3V/0.7V, 23.5dB@180GHz, 3.2mW/1.73mW

JSSC 2020第6期RF & Wireless

A -7-times7-times2- mm3 86- --mu- W 500-kb-s Transmitter With Robust Injection-L

提出一种超低功耗体内到体表通信的发射/接收对，采用注入锁定技术实现频率到幅度转换解调。

130nm CMOS, 8.6 µW, 500 kb/s, 17.2 pJ/b

JSSC 2020第6期Clocking & PLLsCharge PumpPLL

A 065-V 12-16-GHz Sub-Sampling PLL With 564-fsrms Integrated Jitter and -2564-dB

一种0.65V供电、12-16GHz调谐范围的亚采样锁相环，具有564fs抖动和低功耗特性

40nm CMOS, 0.65V, 12-16GHz, 56.4fs抖动, 7.2mW功耗

JSSC 2020第6期Other

A 100-MHz BW 72.6-dB-SNDR CT Modulator Utilizing Preliminary Sam pling and Quantization Wei Wang , Student Member , IEEE

一款采用预采样量化技术的100MHz带宽CT调制器，实现72.6dB SNDR

100MHz带宽, 72.6dB SNDR, 16.3mW功耗, 0.019mm²面积

JSSC 2020第6期Data ConvertersSAR ADC

A 14-bit 4-MS-s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch C

本文提出了一种基于VCO的14位4-MS/s SAR ADC，利用比较器的亚稳态进行背景校准。

14-bit, 4-MS/s, 78.7 dB SNDR, >93 dB SFDR, 94-157 µW功耗

JSSC 2020第6期Memory

A 187-mm2 569-GOPS Accelerator for

提出一种基于SRAM的低精度并行计算加速器，用于高效求解偏微分方程。

1.87-mm² 180-nm, 200 MHz, 16.6 mW, 1.38-G entries/s

JSSC 2020第6期RF & Wireless

A 21-dm-OP 1d B 20.3%-Efﬁciency − 131.8-dBm/Hz-Noise X -Band Cartesian Error Feedback Transmitter With Fully Integrated Power Ampliﬁer in 65-nm CMOS

提出一种X波段笛卡尔误差反馈环发射机，通过额外参考路径改善线性度与噪声性能。

21.4dBm最大输出功率，21dBm OP1dB，33.3%/30.3% PA效率，22.3%/20.3%系统效率，-133/-131.8dBm/Hz带外噪声

JSSC 2020第6期RF & Wireless

A 22.3-nW, 4.55 cm 2 Temperature-Robust Wake-Up Receiver Achieving a Sensitivity of − 69.5 dBm at 9 GHz Haowei Jiang , Student Member , IEEE, Po-Han

本文介绍了一种温度补偿的微型唤醒接收器，功耗仅为22.3 nW，工作在9 GHz频段，面积小且温度不敏感。

65nm (RF) 和 180nm (BB) CMOS, 22.3 nW功耗, -69.5 dBm灵敏度

JSSC 2020第6期RF & Wireless

A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing

一款低功耗、小尺寸的60GHz CMOS收发器SoC，集成四天线封装，提供宽波束覆盖。

32nm CMOS, 250mW功耗, 17.1dBm EIRP, 6.1dB噪声系数, 4.62Gb/s数据速率

JSSC 2020第6期RF & WirelessPower AmplifierNeural Network Accelerator

A 28 GHz Single-Input Linear Chireix -SILC- Power Amplifier in 130 nm SiGe Technology

本文介绍了一种28 GHz高效线性功率放大器，结合Chireix和Doherty架构，无需预失真即可实现功率回退效率和线性化。

19 dBm饱和功率，34.4%峰值功率附加效率，6 dB回退效率>23%，27.5 GHz

JSSC 2020第6期MemorySRAM

A 373-F2 021--Native-BER EE SRAM Physically Unclonable Function With 2-D Power-G

提出一种基于EE结构的高稳定SRAM PUF，采用2-D电源门控技术降低功耗并提高抗攻击能力。

130nm CMOS, 0.8V, 0.21% BER, 128fJ/bit, 0.44pW/bit

JSSC 2020第6期Data ConvertersSAR ADCNeural Network Accelerator

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog–Digital Corrections in 28-nm CMOS Athanasios T. Ramkaj , Student Member , IEEE,J u a nC .P e ñ aR a m o s

一款5GS/s、1586mW功耗的被动采样时间交错三级流水线ADC，具有高精度和低功耗特性。

5GS/s采样率，158.6mW功耗，1V电源，6GHz带宽，75.2dB SFDR/SNDR

JSSC 2020第6期Data ConvertersVCO

A 5-GS-s 72-ENOB Time-Interleaved VCO-Based ADC Achieving 305 fJ-cs

一款基于VCO的八通道时间交织ADC，在28nm CMOS工艺下实现5GS/s采样率和7.2位ENOB。

28nm CMOS, 5GS/s, 7.2 ENOB, 22.7mW

JSSC 2020第6期RF & Wireless

A Digital RF Transmitter

提出一种无需数字预失真或自适应即可校正静态和动态非线性的新型数字发射机架构。

28-nm CMOS, 50%效率, +24 dBm输出, -35.4 dB相邻信道功率比, -150 dBc/Hz接收带噪声

JSSC 2020第6期Other

A Feedforward Noise Reduction Technique in Capacitive MEMS Accelerometer Analog Front-End for Ultra-Low-Power IoT Applications

提出一种超低功耗电容MEMS加速度计模拟前端芯片，采用前馈噪声消除技术降低噪声。

290 µg/√Hz噪声基底，252 nW功耗，65 dB动态范围，62.8 µg偏置不稳定性

JSSC 2020第6期Other

A Fully Dynamic Multi-Mode CMOS Vision Sensor With Mixed-Signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing Xiaopeng Zhong , Student Member , IEEE,M a n - K a yL a w, Senior Member , IEEE

一种低功耗多模式CMOS视觉传感器，支持运动感知、对象分割和全成像三种操作模式。

256 × 216芯片原型，2.36 µW@15帧/秒（MS模式），1.41 µJ/帧（FIM模式）

JSSC 2020第6期Power ManagementLDO

A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 72-pF

提出一种采用PMOS和NMOS阵列的数字低压差稳压器，实现亚飞秒级速度指标。

28nm CMOS, 0.9V输入电压, 140mA负载电流, 88.4mA负载转换时88mV下冲/42mV过冲

JSSC 2020第6期RF & WirelessCharge PumpPLL

A Sub-mW 2.4-GHz Active-Mixer-Adopted Sub-Sampling PLL Achieving an FoM of −256 dB Dhon-Gue Lee , Student Member , IEEE, and Patrick P . Mercier , Senior Member , IEEE

提出一种采用有源混频器的亚采样锁相环，实现-256 dB的FoM。

161 fs RMS抖动（10kHz-100MHz），-67 dBc杂散，0.93 mW功耗

JSSC 2020第6期Power ManagementLDO

An Analog-Proportional Digital-Integral Multiloop Digital LDO With PSR Improvement and LCO Reduction

本文提出了一种具有模拟比例和数字积分控制的多环数字LDO，优化了负载瞬态响应、电源抑制比和极限环振荡。

65nm CMOS, 0.6V, 5MHz, 29µA静态电流, -22dB PSR@1MHz

JSSC 2020第6期Power ManagementNeural Network Accelerator

An Ultra-Low-Power Polarity-Coincidence Feedback Time-Delay-to-Digital Converter for Sound-Source Localization

一种超低功耗极性重合反馈时间延迟数字转换器，用于声源定位

0.18-um CMOS, 78 nW, 50 kS/s, 20-us分辨率, 6.06 ENOB

JSSC 2020第6期RF & Wireless

Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays M

多频段毫米波阵列的天线预处理与单元模式整形技术研究

带宽37–73 GHz

JSSC 2020第6期Clocking & PLLs

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators

本文提出了一种适用于所有注入锁定振荡器(ILO)拓扑的完整频域模型。

65nm CMOS工艺

JSSC 2020第6期MemorySRAM

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks Shihui Yin , Student Member , IEEE, Zhewei Jiang , Student Member , IEEE

XNOR-SRAM是一种支持二进制/三元深度神经网络的内存计算SRAM宏，能效达403 TOPS/W。

403 TOPS/W能效，CIFAR-10数据集88.8%准确率，0.6V供电

JSSC 2020第7期RF & Wireless

1310-1550 nm Optical Receivers With Schottky Photodiode in Bulk CMOS

本文介绍了一种在体CMOS技术中集成肖特基光电二极管的光学接收器，适用于1310/1550 nm波长。

28 nm CMOS, 40 nm CMOS

JSSC 2020第7期Analog CircuitsDelta-Sigma ADCOp-Amp

50nW Opamp-Less ---Modulated Bioimpedance Spectrum Analyzer for Electrochemical

一款130nm CMOS工艺的无运放调制生物阻抗频谱分析器，用于电化学检测，功耗仅50nW。

0.004mm²每通道, 50nW@0.6V, 1pA灵敏度, 50.3dB SNDR, 5kHz扫描范围

JSSC 2020第7期Digital CircuitsCMOS Image Sensor

A 128 × 128 SPAD Motion-Triggered Time-of- Flight Image Sensor With In-Pixel Histogram and Column-Parallel Vision Processor Francesco Mattioli Della Rocca , Student Member , IEEE

一款128×128 SPAD运动触发ToF图像传感器，集成视觉与测距功能，动态降低功耗。

128×128分辨率，32.5k帧/秒（视觉模式），500帧/秒（ToF模式），3.5米测距精度1.5cm

JSSC 2020第7期Clocking & PLLsVCO

A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1 / f Noise Upconversion Caused by Short-Channel Effects

利用Class-C操作实现K波段CMOS VCO，有效抑制1/f噪声上变频，相位噪声低至-112 dBc/Hz。

28nm CMOS, 19.5 GHz, -112 dBc/Hz at 1-MHz offset, 20.7 mW

JSSC 2020第7期RF & WirelessTDC

A 32 - 128 SPAD-257 TDC Receiver IC for Pulsed TOF Solid-State 3-D Imaging

一款用于脉冲TOF固态3D成像的32×128 SPAD-257 TDC接收器芯片

0.35µm HV CMOS, 78ps分辨率, 250kHz脉冲率, 20fps帧率

JSSC 2020第7期Data ConvertersDACVCO

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid V oltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs

一种高效的两步混合电压-时间ADC，在28nm CMOS工艺下实现4GS/s转换速度和39.9dB SNDR。

28nm CMOS, 4GS/s, 39.9dB SNDR, 47.8dB SFDR, 117mW

JSSC 2020第7期RF & WirelessEqualizerPAM-4

A 50-112-Gb-s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS

65nm CMOS工艺下实现50-112Gb/s PAM-4发射机，采用分数间隔FFE提升眼图性能

112Gb/s最高数据速率，2.17pJ/bit能效

JSSC 2020第7期RF & Wireless

A 64-Channel Transmit Beamformer With ±30-V Bipolar High-V oltage Pulsers for Catheter-Based Ultrasound Probes Mingliang Tan , Student Member , IEEE, Eunchul Kang , Student Member , IEEE

一款用于导管超声探头的64通道高压脉冲发射器芯片，支持±30V双极性脉冲输出。

0.18μm BCD工艺, ±30V输出, 5ns时序分辨率, 9MHz驱动频率, 180Ω导通电阻

JSSC 2020第7期RF & Wireless

A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc-Hz Noise in 14-nm FinFET

提出一种基于数字时间转换器（DTC）的多频带数字极化发射机，支持宽通道相位调制，并通过调整PLL频率消除杂散。

输出频率范围0.7至2.2 GHz，DCO调谐范围7.3–8.7 GHz（±8.7%）

JSSC 2020第7期RF & Wireless

A Fully Integrated Programmable 6.0–8.5-GHz UWB IR Transmitter Front-End for Energy-Harvesting Devices Tuomas Haapala , Student Member , IEEE, Tuomas Rantataro, and Kari A. I. Halonen, Member , IEEE

一款全集成可编程60-85GHz超宽带脉冲无线电发射前端，支持能量收集应用

65nm CMOS, 1.8-pJ脉冲, 7.5GHz载波频率, 63pJ/脉冲, 2.3%效率

JSSC 2020第7期Power ManagementEnergy HarvestingNeural Network Accelerator

A Reconﬁgurable and Exte ndable Single-Inductor Single-Path Three-Switch Converter for Indoor Photovoltaic Energy Harvesting Peng-Chang Huang , Student Member , IEEE

提出一种可重构和可扩展的单电感三开关转换器，用于室内光伏能量收集。

0.5-µm CMOS, 1.24-mm² chip area, 95.0% peak efficiency (1P3S), 210 nA quiescent current (1P3S)

JSSC 2020第7期OtherNeural Interface

A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and A

一款单芯片双向神经接口，支持高压刺激与神经信号记录，实现同步神经调控。

65nm LP工艺, 2.5/1.2V供电, 记录功耗205µW, 刺激功耗142µW, 最大输出功率24mW

JSSC 2020第7期Digital CircuitsNeural Network Accelerator

An 893 TOPS-W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical C

提出一种基于分层粗粒度稀疏的LSTM神经网络加速器，实现高效能语音识别。

65-nm LP CMOS, 8.93 TOPS/W

JSSC 2020第7期Other

An All-Digital, VMAX-Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of V oltage Droop

一种采用分布式电荷注入方案的全数字VMAX兼容稳定可扩展设计，用于快速缓解电压跌落。

0.8 V/1.4 GHz, 1.0 V/2.0 GHz, 跌落减少74% (45%)

JSSC 2020第7期RF & WirelessHigh-Speed LinkEqualizer

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for C

提出一种基于时钟域编码的iPWM线编码方案，实现低电压下的高效均衡。

3–16 Gb/s, 0.5-0.9V, 27dB channel loss, 1.8 pJ/bit

JSSC 2020第7期Wireline I/OEqualizer

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s Michiel V erplaetse , Student Member , IEEE,J o r i sL a m b r e c h t, Michael V anhoecke , Laurens Breyne , Student Member , IEEE

提出一种用于16-QAM光通信的55nm SiGe BiCMOS模拟I-Q FIR滤波器，补偿频率相关变化。

55nm BiCMOS, 185mW核心功耗, 112Gb/s 16-QAM调制信号

JSSC 2020第7期RF & Wireless

Analysis and Design of a 260-MHz RF Bandwidth -22-dBm OOB-IIP3 Mixer-First Receiver With Third-Order Current-Mode Filtering TIA

设计适用于5G应用的260MHz带宽、高线性度混频器优先接收器

IIP3 +22dBm, NF 5.5dB, 功耗21.6mW(信号路径)+7.8mW/GHz(LO)

JSSC 2020第7期Clocking & PLLsPLL

Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication Cheng-Hsueh Tsai , Student Member , IEEE, Zhiwei Zong , Student Member , IEEE, Federico Pepe

28nm CMOS工艺下实现快速锁定、低相位噪声的Bang-Bang数字PLL，适用于毫米波通信。

28nm CMOS, 22.5–27.7-GHz, 220 fs rms jitter, 25 mW, 0.09-mm² core area

JSSC 2020第7期MemorySRAM

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism Zhewei Jiang , Student Member , IEEE, Shihui Yin , Student Member , IEEE

C3SRAM是一种基于电容耦合的内存计算SRAM宏，用于二值化神经网络的高效能硬件加速。

65nm CMOS, 672 TOPS/W, 1638 GOPS, 20.2 TOPS/mm²

JSSC 2020第7期RF & Wireless

High-Rejection RF Code Domain Receivers for Simultaneous Transmit and Receive Applications Ahmed Hamza , Student Member , IEEE, Cameron Hill , Student Member , IEEE, Hussam AlShammary , Student Member , IEEE

采用射频码域处理技术实现同时收发，提升自干扰抑制能力。

52 dB TX SI rejection, 0.25-1.25 GHz tunable, 39 dB gain at 1 GHz, 90 mW power consumption

JSSC 2020第7期Analog CircuitsDAC

Low-Power Highly Selective Channel Filtering Using a Transconductor-Capacitor Analog FIR

提出一种基于时变跨导和积分电容的低功耗高选择性模拟有限脉冲响应滤波器。

22nm FDSOI, 0.7V, 92µW, 0.06-3.4MHz可调带宽, f-60dB/f-3dB=3.8, 31.5dB增益, 12nV/√Hz输入噪声

JSSC 2020第7期Data Converters

Track-and-Zoom Neural Analog-to-Digital Converter With Blind Stimulation Artifact Rejection M. Reza Pazhouhandeh , Student Member , IEEE, Michael Chang, Tauﬁk A. V aliante

一种用于神经调节的双向32通道CMOS神经接口，能够在刺激期间记录神经活动。

130nm CMOS, 0.6V/1.2V 数字/模拟供电, 70dB SNDR, 500Hz带宽

JSSC 2020第8期RF & WirelessEqualizer

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

一款采用联合自适应均衡技术的1.62至10.8 Gb/s视频接口接收器，通过SSLMS算法优化CTLE和DFE，实现高效能和低功耗。

65nm CMOS, 37.2 mW at 10.8 Gb/s, 0.1 pJ/b/dB

JSSC 2020第8期Other

A 05-V Sub-10-μW 1528-mΩHz Bio-Impedance Sensor IC With Sub-1

一种0.5V供电、功耗低于10μW的生物阻抗传感器IC，适用于慢性心衰患者的流体状态监测。

0.5V, 10μW, 15.28-mΩ/√Hz, 4.83 mm²

JSSC 2020第8期RF & WirelessCDREqualizer

A 12-Gbs 10-ns Turn-On Time Rapid ONOFF Baud-Rate DFE Receiver in 65-nm CMOS

一款65nm CMOS工艺的12Gbps快速启停接收器，支持10ns启动时间

12 Gb/s, BER < 10^-12, >30-MHz JTOL corner, 377 fs rms jitter, 3.8-pJ/bit

JSSC 2020第8期Other

A 2-in-1 Temperature and Humidity Sensor With a Single FLL Wheatstone-Bridge Front-End Haowei Jiang , Student Member , IEEE, Chih-Cheng Huang , Matthew R. Chan, Student Member , IEEE, and Drew A. Hall , Senior Member , IEEE

提出了一种基于FLL的温湿度传感器，采用单一模拟前端实现高线性度检测

0.18µm CMOS, 15.6µW, 2mK温度分辨率, 0.0073%RH湿度分辨率

JSSC 2020第8期Digital Circuits

A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices Yu - C h i L e e

一款用于智能助听器的低功耗DSP处理器，集成CNN和FFT加速器，优化语音增强算法。

40nm CMOS, 0.6V, 5MHz, 4.2mm²核心面积, 2.17mW功耗

JSSC 2020第8期Power ManagementLDO

A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator

提出一种数字辅助双环路低压差稳压器，结合数字与模拟环路优势，实现高电源抑制比和快速响应。

245mA负载，-42dB PSR@1MHz，300μA静态电流，7.4ps FOM

JSSC 2020第8期RF & WirelessPAM-4

A 25Gbaud PAM-4 Linear Burst-Mode Receiver With Analog Gain- and Offset Control in 0.25μm SiGeC BiCMOS

一款支持25Gbaud PAM-4调制的线性突发模式接收器，具有模拟增益和偏移控制功能

25Gbaud NRZ: -18.1dBm灵敏度, 3.5dBm过载; PAM-4: -11.4dBm灵敏度, 4.4dBm过载; 280mW功耗

JSSC 2020第8期Power ManagementLDO

A5 . 6 μA Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz

一种采用电流模式前馈纹波消除器的LDO设计，实现高达68dB的电源抑制比和2MHz的宽频带抑制。

180nm BCD技术, 68dB PSR, 2MHz带宽, 250mA负载, 6.1µs恢复时间

JSSC 2020第8期MemoryDRAM

A Capacitor-Coupled Offset-Canceled Sense Ampliﬁer for DRAMs With Reduced V ariation of Decision Threshold V oltage Jung Min Y oon , Student Member , IEEE, Hyungrok Do, Student Member , IEEE, Daehyun Koh, Student Member , IEEE, Seung Han Oak

一种采用耦合电容抵消偏移的DRAM感应放大器，减少阈值电压随机变化的影响。

65nm CMOS

JSSC 2020第8期Other

A Fully Integrated Multilevel Synchronized-Switch-Harvesting-on-Capacitors Interface for Generic PEHs Pavel Angelov , Student Member , IEEE, and Martin Nielsen-Lönn , Student Member , IEEE

提出一种全集成多级同步电容开关能量采集架构，显著提升压电换能器能量提取效率。

0.18-µm CMOS, 22 Hz, 1.51 µW to 4.82 µW

JSSC 2020第8期OtherNeural Network Accelerator

A Hybrid LED

提出一种高效混合LED驱动器，结合开关转换器和无电感驱动方案的优点，实现高功率因数和低闪烁。

95.1%功率效率，0.986功率因数，92%效率（低闪烁配置），15%闪烁

JSSC 2020第8期RF & WirelessNeural Network Accelerator

A Low-Power 70–100-GHz Mixer-First RX Leveraging Frequency-Translational Feedback

提出一种低功耗70100-GHz混频器优先接收机，利用频率转换反馈和被动电压增益。

28-nm CMOS, S11< −10 dB, NF < 10 dB, ∼20-dB conversion gain, 12 mW power consumption

JSSC 2020第8期RF & WirelessLNA

A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push–Pull LNA

一种高效低功耗的2.4GHz射频前端设计，集成DCO-PA和推挽LNA，实现单引脚天线接口。

65nm CMOS, 0.3V/0.5V, 0dBm RF输出, 10.2%功率效率, 11dB增益, 6.8dB噪声系数

JSSC 2020第8期Data ConvertersSAR ADC

A Time-Interleaved SAR ADC With Bypass-Based

一种采用旁路窗口和自适应校准的高效时间交织SAR ADC

28nm FDSOI, 0.9V, 2.4GS/s, 10-bit, 49.02dB SNDR, 9.8mW

JSSC 2020第8期Digital CircuitsProcessor/CPU

A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS

提出一种具有两级时序错误检测与校正的变异弹性微处理器架构，显著提升能效。

0.36V超低供电电压，能效提升60.5%，最小能耗降低37.1%

JSSC 2020第8期Clocking & PLLs

An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture

提出一种利用指令级动态时序松弛的自适应时钟方案，提升GPGPU性能与能效

65nm CMOS工艺下性能提升18%或能耗降低30%

JSSC 2020第8期RF & WirelessPLLClock Generation

An Energy-Efﬁcient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled

一款65nm CMOS工艺的高能效10Gb/s毫米波收发器，集成直接调制数字发射器和I/Q相位耦合频率合成器。

65nm CMOS, 10Gb/s, 340.4mW, 34pJ/bit, -115.6dBc/Hz@10MHz

JSSC 2020第8期Digital Circuits

Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things Joao P . Cerqueira , Member , IEEE, Thomas J. Repetti, Student Member , IEEE,Y uP u , Member , IEEE, Shivam Priyadarshi, Martha A. Kim , Member , IEEE

Catena是一款近阈值电压16核可编程空间阵列加速器，专为超低功耗移动和嵌入式物联网应用设计。

65nm低功耗CMOS, 228 pJ/cycle, 2.7倍能效提升

JSSC 2020第8期RF & WirelessVCO

Clockless, Continuous-Time Analog Correlator Using Time-Encoded Signal Processing Demonstrating Asynchronous CDMA for Wake-Up Receivers Vivek Mangal , Student Member , IEEE, and Peter R. Kinget

提出了一种基于时间编码信号处理的无时钟连续时间模拟相关器电路。

37 nW, 0.54 V

JSSC 2020第8期Other

High-Value Tunable Pseudo-Resistors Design

本文提出了一种优化的伪电阻架构，用于高频低噪声应用中的大值电阻模拟。

0.35 µm CMOS, 100 kHz –10 MHz, 0.017 mm²

JSSC 2020第8期Other

Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor R

提出一种分相翻转电容整流器（SPFCR），优化压电能量收集接口的电容数量与能量提取效率的权衡。

最大输出功率提升率（MOPIR）达9.3倍（VD=0.12V时）

JSSC 2020第8期RF & WirelessPhased ArrayNeural Network Accelerator

Power-Efficient Design Techniques for mm-Wave HybridDigital FDDFull-Duplex MIMO

毫米波MIMO收发器的功率效率优化与全双工设计技术

28-/37-/39-GHz, 65nm CMOS, 16-/11-dB RX增益, 6.2-/7-dB NF

JSSC 2020第8期OtherClock Generation

Table of contents

IEEE JSSC期刊论文合集，涵盖毫米波收发器、低功耗接收机、射频前端设计等多个领域。

10-Gb/s, 70–100GHz, 低功耗

JSSC 2020第8期OtherNeural Network Accelerator

Tianjic A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural C

Tianjic芯片提出统一架构，支持脉冲神经网络与深度学习模型的高效兼容运行。

未明确披露（提及支持动态生物神经网络与深度学习加速）

JSSC 2020第9期RF & Wireless

300-GHz-Band 120-Gbs Wireless Front-End Based on InP-HEMT PAs and Mixers

基于InP-HEMT技术的300GHz频段120Gb/s无线前端设计

输出1dB压缩点大于6dBm（278至302GHz），转换增益-15dB，3dB IF带宽32GHz

JSSC 2020第9期Analog CircuitsNeural Network Accelerator

A 0.032-mm2 43.3-fJ/Step 100–200-MHz IF 2-MHz Bandwidth Bandpass DSM Based on Passive N-Path Filters

基于被动N路径滤波器的带通ΔΣ调制器，实现高能效和宽频调谐范围。

65nm CMOS, 0.032mm², 100-200MHz IF, 2MHz带宽, 55.5dB SNDR, 150µW

JSSC 2020第9期Data ConvertersDAC

A 0.07-mm2 162-mW DAC Achieving >65 dBc SFDR and < −70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing Hung-Yi Huang , Student Member , IEEE

提出一种小面积、低功耗、高线性度的DAC，采用输出阻抗补偿和同心平行四边形布线技术。

28nm CMOS, 1.1V, 10GS/s, 162mW

JSSC 2020第9期Other

A 0.46-THz 25-Element Scalable and Wideband Radiator Array With Optimized Lens Integration in 65-nm CMOS

本文提出了一种438–479GHz全集成25元件辐射器阵列，采用可扩展耦合结构，优化透镜提升辐射性能。

65nm CMOS, 1.2V, 40.7GHz/8.9%调谐范围, 19.3dBm EIRP

JSSC 2020第9期Other

A 1-nA 45-nW 289-ppmC Current

提出一种采用自动校准技术的超低功耗高精度1nA电流基准源。

1nA输出电流，289ppm/°C温度系数，1.4%/V电源灵敏度，4.5nW总功耗

JSSC 2020第9期Power ManagementVCO

A 16.1-bit Resolution 0.064-mm 2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS

一种新型直接电阻传感器数字读出电路，采用单VCO和数字反馈环路，实现16.1位分辨率，面积仅0.064 mm²。

16.1位分辨率，171 µW功耗，0.064 mm²面积，-40°C至125°C工作范围

JSSC 2020第9期Other

A 22-ngHz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass S

开发了一种噪声极低（22 ng/√Hz）且功耗适中（17 mW）的全集成MEMS加速度计，适用于基础设施监测和油气勘探等新兴应用。

22 ng/√Hz噪声, 17 mW功耗, ±0.55 g输入范围, 400 Hz带宽

JSSC 2020第9期RF & Wireless

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

28GHz CMOS相控阵波束成形芯片，采用双向中和技术降低面积，支持5G毫米波双极化MIMO系统。

饱和输出功率15.1 dBm (TX), 噪声系数4.2 dB (RX), 最大EIRP 45.6 dBm, 支持15 Gb/s数据率

JSSC 2020第9期RF & Wireless

A Beyond-1-Tbs Coherent Optical Transmitter Front-End Based on 110-GHz-Bandwidth 21 Analog Multiplexer in 250-nm InP DHBT

基于110GHz带宽的超越1Tbs相干光发射前端

110GHz带宽,1.5Vppd线性差分输出,<3%THD,168GBaud PDM-16QAM

JSSC 2020第9期RF & Wireless

A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength Abdelrahman H. Ahmed , Student Member , IEEE, Abdellatif

本文介绍了一种基于硅光子技术的双偏振相干发射器，支持552 Gb/s的数据传输速率。

6 V峰峰值摆幅，3.6%总谐波失真，40 GHz以上电带宽

JSSC 2020第9期Other

A High-Q Resonant Inductive Link Transmit Driver With Adaptive-Predictive Phase-

提出一种高Q谐振电感链路传输驱动，通过自适应预测相位调制突破Q因子限制。

10 kHz–2 MHz, 0.18-µm 1.8–50-V CMOS/LDMOS

JSSC 2020第9期MemoryProcessor/CPU

A Programmable Heteroge neous Microprocessor Based on Bit-Scalable In-Memory Computing Hongyang Jia , Student Member , IEEE, Hossein Valavi , Student Member , IEEE, Yinqi Tang , Student Member , IEEE, Jintao Zhang , Student Member , IEEE,a n dN a v e e nV e r m a ,Member , IEEE

基于位可扩展内存计算的异构微处理器设计，实现高能效与可编程性。

1b TOPS/W 192-400, 1b-TOPS/mm² 0.60-0.24, VDD 1.2-0.85V

JSSC 2020第9期RF & Wireless

A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration Benjamin J. Fletcher

提出一种低能耗无线3D集成收发器，结合脉冲延时编码和可调电流驱动，显著降低能耗。

7.4 pJ/bit, 28nm CMOS

JSSC 2020第9期Data ConvertersPipeline ADCNeural Network Accelerator

An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Ampliﬁer Y

一种采用高线性度动态放大器的11位100MS/s全动态流水线ADC

28nm CMOS, 0.05mm², 100MS/s, 62dB SNDR, 77dB SFDR, 1.33mW

JSSC 2020第9期Power Management

An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 018-μm CM

一种超低噪声摆幅增强差分弛豫振荡器，具有优异的相位噪声性能和功率效率。

10.5MHz, 219.8µW@1.4V, 9.86psrms抖动, 0.01%相对抖动

JSSC 2020第9期Clocking & PLLsVCO

Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO

提出一种仅使用npn晶体管的17GHz推挽式C类VCO，通过磁变压器实现正反馈，降低功耗。

17GHz, -116dBc/Hz@1MHz, 13.7mA@3.3V, 15%调谐范围

JSSC 2020第9期Other

Analysis and Design of a Robust, Low-Power, Inductively Coupled LSK

设计了一种低功耗半双工电感耦合数据链路，传输距离达5cm，速率4Mb/s。

0.075 pJ/b（发送模式）, 5 pJ/b（接收模式）

JSSC 2020第9期Data ConvertersSAR ADC

Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for L

提出带宽增强型过采样逐次逼近读出技术，降低MEMS电容加速度计噪声并提高能效

0.18-µm BCD工艺，飞法级电容检测

JSSC 2020第9期Analog Circuits

Baseband to 140-GHz SiGe HBT and 100-GHz InP DHBT Broadband Triple-Stacked Distributed Amplifiers

设计并比较了140GHz SiGe和100GHz InP三堆叠HBT分布式放大器，展示了高性能宽带特性。

SiGe: 11.7dB增益, 140GHz带宽; InP: 10.8dB增益, 100GHz带宽

JSSC 2020第9期Power ManagementDACNeural Network Accelerator

Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density Raviteja Theertham, Student Member , IEEE, Prasanth Koottala, Sujith Billa, Student Member , IEEE

提出高分辨率连续时间ΔΣ转换器设计技术，解决寄生电阻、符号间干扰和闪烁噪声问题。

180nm CMOS, 32MS/s, 24mW, 108dB SNR

JSSC 2020第9期Other

Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Ampliﬁers With a Compact 2nd-Harmonic-Shorted Four-Way Transformer and a Thermally

本文设计了一种高线性度高功率SiGe HBT WLAN功率放大器，解决了电热效应带来的挑战。

22.5/23.6/23.2 dBm输出功率, 10.0/12.2/11.2% PAE, DEVM=-35dB

JSSC 2020第9期Power Management

Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS

65nm CMOS工艺下实现宽转换比混合Dickson开关电容转换器，峰值效率达92.6%。

65nm CMOS, 3.4-4.2V输入, 0.3-0.9V输出, 1.5A, 330mW/mm², 92.6%效率

JSSC 2020第9期Other

Introduction to the Special Section on the 2019 IEEE BCICTS Conference

2019年IEEE BCICTS会议特刊介绍，涵盖SiGe和III-V/CMOS集成电路技术的最新研究。

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JSSC 2020第9期Other

Low-Power Organic Light Sensor Array Based on Active-Matrix Common-Gate Transimpedance Ampliﬁer on Foil for Imaging Applications Samar Elsaegh , Clemens V eit, Ute Zschieschang , Mohammad Amayreh , Florian Letzkus, Holger Sailer, Michael Jurisch, Joachim N. Burghartz , Uli Würfel

基于有机薄膜晶体管的低功耗柔性光传感器阵列成像系统

57.6μW功耗，4×5阵列，0-100μA检测范围，1kHz带宽

JSSC 2020第9期Analog Circuits

The Design of a CMOS Nanoelectrode Array With 4096 Current-ClampVoltage-Clamp Amplifiers for Intracellular RecordingStimulation of

设计了一种具有4096个纳米电极的CMOS集成电路，用于高并行性、高灵敏度的神经元电生理记录。

4096个PtB纳米电极，20µm间距，±15 pA至±0.7 µA电流注入，5 pA分辨率

JSSC 2020第10期Other

A 123-μW 072-mm² Fully Integrated Front-End IC for Arterial Pulse Waveform and E

一款低功耗、小面积的前端IC，用于生物医学仪器，支持动脉脉搏波形检测和ExG记录。

0.18-µm CMOS, 123-µW, 0.72-mm², 5.84 µVrms输入噪声, -80 dB总谐波失真

JSSC 2020第10期Other

A 15-Channel Orthogonal Code Chopping Instrumentation Ampliﬁer for Area-Efﬁcient, Low-Mismatch Bio-Signal

提出一种15通道正交码斩波仪表放大器，实现高效面积和低增益失配的多通道生物信号采集。

0.18µm CMOS, 0.019 mm²/Ch., 0.43% gain mismatch, 1.97 µW/Ch., < −51.5 dB crosstalk, 490-Hz bandwidth

JSSC 2020第10期RF & WirelessLNA

A 20-GHz 1.9-mW LNA Using gm-Boost and Current-Reuse Techniques in 65-nm CMOS for

65nm CMOS工艺下20GHz低功耗LNA，采用gₘ提升和电流复用技术

65nm CMOS, 1V, 14.9dB增益, 3.3dB NF, 1.9mW功耗

JSSC 2020第10期Clocking & PLLsPLLCDR

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase

本文提出了一种四电平脉冲幅度调制(PAM4)四分之一速率时钟和数据恢复电路(CDR)，采用线性相位检测器和自偏置PLL多相时钟发生器，实现了低功耗和低抖动。

40nm CMOS, 32-Gb/s, 0.46 pJ/bit, 352.6 fs抖动

JSSC 2020第10期Clocking & PLLsCMOS Image Sensor

A3 2 × 32-Pixel CMOS Imager for Quantum Optics With Per-SPAD TDC, 19.48% Fill-Factor in a 44.64-μm Pitch Reaching 1-MHz

一款用于量子光学的高填充因子32x32像素CMOS图像传感器，具有单光子探测和时间数字转换功能。

44.64µm像素，19.48%填充因子，210.2ps分辨率，50ns（8位）范围TDC，1.28-LSB DNL，1.92-LSB INL

JSSC 2020第10期RF & Wireless

A 390-GHz Outphasing Transmitter in 28-nm CMOS

28nm CMOS工艺下实现的390GHz谐波外差发射机，支持最高6Gb/s数据传输。

28nm CMOS, 峰值输出功率-16dBm, 3dB IF带宽16.5GHz, 最大数据速率6Gb/s

JSSC 2020第10期MemorySRAMNeural Network Accelerator

A 4-Kb 1-to-8-bit Conﬁgurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors Y en-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si , Student Member , IEEE, Ruhui Liu, Y

提出一种1至8位可配置的6T SRAM存内计算单元宏，提升读取精度和能效。

55nm CMOS, 3.5ns每周期, 0.6–40.2 TOPS/W

JSSC 2020第10期Clocking & PLLsCDR

A 65-125-Gbs Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

提出一种基于扩展Bang-Bang相位检测器的无参考时钟数据恢复电路，具有快速锁定和低功耗特点。

28nm CMOS, 12.5 Gb/s, 320 ns频率锁定时间, 21.13 mW功耗, 2.11 pJ/bit能效

JSSC 2020第10期Analog Circuits

A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter Ya n g X u , Member , IEEE,H a n gH u

提出一种基于耦合源跟随器的低功耗高线性度五阶低通滤波器。

0.18µm CMOS, 1.3V, 0.5mA, 20MHz带宽, 76.9dB动态范围

JSSC 2020第10期Data ConvertersSAR ADC

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability Min-Jae Seo , Dong-Hwan Jin, Y e-Dam Kim, Jong-Pal Kim

一种基于CDAC的单电源缓冲嵌入式SAR ADC，采用跳复位方案，具有高能效和轨到轨信号摆幅。

180nm CMOS, 640-kHz BW, 74.8-dB SNDR, 89.1-dB SFDR, 180.1 μW

JSSC 2020第10期MemorySRAMBiosignal

A Smart Hardware Security Engine Combining Entropy Sources of ECG HRV and SRAM P

提出一种结合ECG HRV和SRAM PUF的智能硬件安全引擎，用于实时认证和随机密钥生成。

65nm LP CMOS, 0.6V, 4.04 µW

JSSC 2020第10期Digital CircuitsPower AmplifierNeural Network Accelerator

A VHF Wide-Input Range CMOS Passive Rectifier

提出一种具有主动偏置调谐的VHF宽输入范围CMOS被动整流器，适用于毫米级植入式医疗设备。

64.4%的平均最大功率转换效率（PCE）

JSSC 2020第10期Digital Circuits

An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for I

提出一种支持CNN训练的高效能深度学习加速器，采用三种处理器核心优化不同计算类型。

65nm CMOS, 0.63-1.0V, 50MHz, 40.7mW, 47.4µJ/epoch

JSSC 2020第10期Data ConvertersDelta-Sigma ADCNeural Network Accelerator

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator

结合一阶单比特连续时间调制器和二阶MASH后端，实现高稳定性和低噪声的音频调制器。

180-nm CMOS, 100.9-dB SNDR, 24-kHz带宽, 265μW功耗

JSSC 2020第10期Clocking & PLLsPLL

A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth

提出一种4GHz次谐波注入锁定锁相环，通过自校准技术实现低相位噪声。

4GHz, 11.4mW, 1.0V, 710fs jitter, -112.3dBc/Hz@1MHz

JSSC 2020第10期OtherFlash Memory

Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing Shun Suzuki

提出一种隐私保护的NAND闪存系统，灵活控制数据生命周期。

3-D NAND闪存处理

JSSC 2020第10期MemoryProcessor/CPU

Processor Energy–Performance Range Extension Beyond V oltage Scaling via Drop-In Methodologies

提出一种超越传统电压调节的处理器能效性能扩展方法。

40 nm, 1.1 V, 16-KB SRAM

JSSC 2020第10期Other

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip D

提出一种基于Si背面的BBM结构，用于防止物理安全攻击，保护加密密钥。

0.13-µm CMOS, 0.0025% size-overhead

JSSC 2020第10期Power ManagementNeural Network Accelerator

Stacking Isolated SC Cores for High-V oltage Wide Input Range Monolithic DC–DC Conversion

提出一种堆叠隔离SC核心的全集成DC-DC转换器，支持7.5至42V宽输入范围。

0.35µm CMOS, 3V输出, <5%纹波, 2.1mW峰值功率

JSSC 2020第10期RF & Wireless

Wireless Body-Area-Network Transceiver and Low-Power Receiver With High

提出一种支持IEEE 802.15.6标准和高速数据传输的体域网收发器及低功耗接收器。

31μW低功耗，65nm CMOS

JSSC 2020第11期RF & WirelessPhased ArrayRadar

A 4TX/4RX Pulsed Chirping Phased-Array Radar Transceiver in 65-nm CMOS for X-Band Synthetic Aperture

一款65纳米CMOS工艺的X波段4TX4RX脉冲啁啾相控阵雷达收发器芯片

65nm CMOS, 1.2V, 10GHz中心频率, 1GHz带宽, 228mW每通道

JSSC 2020第11期Data Converters

A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ADCs

本文介绍了一种12英寸晶圆级CMOS X射线探测器，具有高分辨率、低噪声和高动态范围。

16-bit ADC, 45μm pitch, DNL +0.79/-0.65 LSB, INL +6.85/-6.15 LSB, SNR 88.5 dB, 12.6μs转换时间

JSSC 2020第11期OtherDACNeural Network Accelerator

A6 . 5 -μW 10-kHz BW 80.4-dB SNDR G m-C-Based CT Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant

提出一种基于Gm-C的连续时间ΔΣ调制器，用于抗伪影神经记录接口，具有高线性度和低功耗。

65-μW功耗, 10-kHz带宽, 80.4-dB SNDR, 81-dB动态范围, 76-dB CMRR

JSSC 2020第11期Data ConvertersSAR ADCDAC

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background

一种采用背景偏移校准技术的7位900MS/s 2-然后3位/周期SAR ADC

7位, 900MS/s, 2.6mW, 36.6fJ/conversion-step

JSSC 2020第11期OtherBiosignal

A Batteryless Motion-Adaptive Heartbeat Detection System-on-Chip Powered by Human

利用人体热能供电的无电池自适应心跳检测SoC

0.18-µm CMOS, 20 µW最小输入功率, 20 mV输入电压, 0.5°C温度梯度

JSSC 2020第11期OtherPower Amplifier

A Broadband Switched-Transformer Digital Power Ampliﬁer for Deep Back-Off Efﬁciency Enhancement Yu n Yi n , Member , IEEE

本文提出了一种基于开关变压器的宽带数字功率放大器，用于深度回退效率提升。

40nm CMOS, 1.1V, 0.7×1.15mm²芯片面积

JSSC 2020第11期RF & Wireless

A Low-Power Backscatter Modulation System Communicating Across Tens of Meters With Standards-Compliant Wi-Fi Transceivers Po-Han

一种低功耗反向散射调制系统，实现与商用Wi-Fi收发器的远距离通信

65nm CMOS, 2.8 µW唤醒接收功耗, -42.5 dBm灵敏度, 28 µW反向散射功耗, 17 dB镜像抑制

JSSC 2020第11期Other

A Low-Power VGA Vision Sensor With Embedded Event Detection for Outdoor

一款低功耗VGA视觉传感器，嵌入事件检测功能，适用于户外边缘计算。

344 µW（运动检测模式）, 1.35 mW（成像模式）, 8帧/秒

JSSC 2020第11期mm-Wave

A Millimeter-Scale Single Charged Particle Dosimeter for

一种用于癌症放射治疗的毫米级单带电粒子剂量计

无

JSSC 2020第11期RF & WirelessLDO

A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications Kan Li

提出一种多环路设计技术，实现高速瞬态响应的LDO稳压器，适用于5G移动设备。

1 A, 1.2-1.8 V, 10 mV undershoot/overshoot, 60 dB dc loop gain

JSSC 2020第11期Other

A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons Jeroen Petrus Gerardus V an Dijk , Student Member , IEEE, Bishnu Patra , Student Member , IEEE

本文提出了一种用于宽频带多路复用控制的低温CMOS控制器，支持4×32量子比特的控制。

4×32量子比特控制

JSSC 2020第11期Image Sensors

An AMOLED Pixel Circuit With a Compensating Scheme for V ariations in Subthreshold Slope and Threshold V oltage of Driving TFTs

提出一种用于高分辨率AMOLED显示的低灰度阈值电压和亚阈值斜率补偿像素电路。

OLED电流误差在64和128灰度级分别从±3.5/±6.5降至±2.0/±0.8 LSB

JSSC 2020第11期Other

An Auto-Calibrated Resistive Measurement System With Low Noise Instrumentation A

一种用于宽范围电阻传感器的自校准低噪声测量系统

可检测72 ppm的ΔR/Rs变化，相对误差小于±1%

JSSC 2020第11期Power ManagementNeural Network Accelerator

An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 V oltage/Time Dual-Data-Converter-Based AFE

一款采用双数据转换器的40通道高分辨率汽车激光雷达SoC，实现225米测距和240×192像素分辨率。

40通道, 240×192像素, 225米测距, 70-klx阳光, 10 FPS

JSSC 2020第11期Power Management

An Energy-Efﬁcient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

提出一种基于时间域增量式电容数字转换器的高能效设计

76-dB SNDR, 0.083 nJ/conversion, 0.29 fF分辨率

JSSC 2020第11期RF & WirelessNeural Network Accelerator

Breaking the Performance Tradeoffs in N-Path Mixer-First Receivers Using a Second-Order Baseband Noise-Canceling TIA

提出二阶基带噪声消除方案，打破N路径混频器优先接收器的性能折衷。

NF <4 dB, IB-IIP3 +14.5 dBm, OB-IIP3 +25 dBm, 功耗20 mW

JSSC 2020第11期Other

Design and Analysis of a Sample-and-Hold CMOS Electrochemical Sensor for Aptamer-Based Therapeutic

设计并分析了一种基于采样保持电路的CMOS电化学传感器，用于适配体药物浓度检测。

15.2 pArms输入参考噪声电流@2.5kHz带宽

JSSC 2020第11期RF & Wireless

Design of a 0.6-V , 429-MHz FSK Transceiver Using Q-Enhanced and Direct Power Transfer Techniques in 90-nm CMOS Chun-Y

设计了一款0.6V工作电压、429MHz频段的低功耗FSK收发器，接收灵敏度-85dBm，发射效率38.7%。

0.6V, 429MHz, 200kb/s, -85dBm灵敏度, 146μW接收功耗, 390μW发射功耗

JSSC 2020第11期Other

II-B Proton detection using a diode

研究利用二极管探测质子，分析电压降与电子空穴对生成的关系。

0.1µm depletion thickness, 2.5 fF Cpar

JSSC 2020第11期MemorySRAM

III-B Digital

设计了一种采用6T SRAM校准的像素电路，以解决质子撞击导致的误触发问题。

8µm×8µm像素尺寸，10-bit量化，6µs LSB采样时间

JSSC 2020第11期MemorySRAM

III-D Calibration

该论文介绍了一种III-D校准技术，涉及SRAM控制、优先级编码和FIFO数据传输优化。

10-bit计数器，6-bit行地址，6-bit列地址，2-bit状态，24位宽16深FIFO

JSSC 2020第11期MemorySRAM

III System Design

该论文介绍了一种低功耗64×64像素阵列系统设计，包含数字块、SRAM控制块和频率锁定环。

64×64像素阵列, 低功耗, 毫米级尺寸

JSSC 2020第11期Other

II Theory of operation

研究实时体内剂量监测技术以减少质子治疗中的不确定性。

无

JSSC 2020第11期Other

IV Measurement Results

该论文介绍了一种在TSMC 65纳米低功耗CMOS技术中实现的剂量计系统，并对其电气性能和像素间变化进行了测量和分析。

65nm CMOS, 512µm×512µm检测面积, 1/64填充因子, PNR 27.7 dB at 3 ms PW

JSSC 2020第11期Other

I Introduction

毫米级CMOS 64×64单电荷粒子辐射探测器系统，用于外部束癌症放射治疗。

TSMC 65nm LP CMOS, 1.2V, 0.535mW静态功耗

JSSC 2020第11期Image SensorsCMOS Image Sensor

Indirect Time-of-Flight CMOS Image Sensor With On-Chip Background Light Cancelling and Pseudo-Four-Tap/Two-Tap Hybrid Imaging for Motion Artifact Suppression Donguk Kim , Student Member , IEEE

提出一种带背景光消除和运动伪影抑制的间接飞行时间CMOS图像传感器。

320×240分辨率，100MHz调制频率，0.54%深度误差（0.75-4m），120klx背景光下0.55%误差

JSSC 2020第11期RF & WirelessNeural Network Accelerator

Integrated Self-Adaptive and Power-Scalable Wideband Interference Cancellation for Full-Duplex MIMO Wireless Y

提出一种自适应宽带干扰消除技术，支持MIMO阵列功率可调，实现微秒级快速适应。

0.5-to-2.5-GHz, 20-MHz BW, >20-dB干扰消除, 14 mW功耗, 1 µs适应时间

JSSC 2020第11期Clocking & PLLs

Large-Area, Fast-Gated Digital SiPM With Integrated TDC for Portable and Wearable Time-Domain NIRS

设计了一种大面积快速门控数字SiPM，集成TDC，适用于便携式和可穿戴设备

8.6mm²感光面积，37%填充因子，300ps上升沿，78ps TDC LSB，128时间bin，>100dB动态范围

JSSC 2020第11期Other

References

该论文讨论了质子治疗物理学、患者停止功率比估计的质子范围不确定性分析以及植入式MOSFET剂量计在癌症治疗中的应用。

无

JSSC 2020第11期OtherCMOS Image Sensor

Table of contents

2020年ISSCC会议论文摘要，涵盖CMOS图像传感器、LiDAR SoC、X射线探测器及神经记录调制器等多项技术。

240×192像素225米范围成像、5.2M像素88.4dB DR、6.5μW 80.4dB SNDR

JSSC 2020第11期Other

V Conclusion

该论文提出了一种基于二极管传感方法的低功耗实时单粒子检测ASIC。

1.2V, 0.512×0.512 mm2传感面积, 0.535mW传感功耗

JSSC 2020第12期RF & WirelessTransceiver

A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving − 96.4-dBm Sensitivity and − 27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets

一款0.5V低功耗蓝牙收发器，接收灵敏度-96.4dBm，功耗1.9mW。

22nm FD-SOI, 0.5V, -96.4dBm灵敏度, 1.9mW功耗

JSSC 2020第12期RF & WirelessPipeline ADC

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Ampliﬁer and Background Calibration A h m e dM .A .A l i , Senior Member , IEEE

一种采用16nm FinFET工艺的12位18GS/s RF采样ADC，集成宽带跟踪保持放大器

12位分辨率，18GS/s采样率，18GHz输入带宽

JSSC 2020第12期Data ConvertersDACPLL

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/ μs Slope and 1.2-GHz Chirp-Bandwidth

一款基于积分DAC的12mW 10GHz FMCW PLL，用于雷达应用，具有28kHz RMS频率误差。

28kHz rms-frequency-error, 11.7mW功耗(其中QDAC<0.5mW), 1.21GHz啁啾带宽, 23.6MHz/µs啁啾斜率

JSSC 2020第12期Data ConvertersSAR ADCNeural Network Accelerator

A 13-bit 0005-mm2 40-MSs SAR ADC With kTC

提出一种kT/C噪声消除技术的13位SAR ADC，显著减小输入电容尺寸，降低对输入驱动和参考缓冲的要求。

40nm CMOS, 0.005 mm², 40 MS/s, 69 dB SNDR, 591 µW

JSSC 2020第12期Data ConvertersSAR ADC

A 13.5-ENOB, 107- μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Ampliﬁer

提出一种具有PVT鲁棒性的闭环动态放大器二阶噪声整形SAR ADC，实现高精度与高能效。

83.8 dB SNDR, 625 kHz带宽, 107 μW功耗

JSSC 2020第12期Analog Circuits

A 28-W 1022-dB THDN Class-D Amplifier Using a Hybrid ΔΣM-PWM Scheme

一款用于汽车应用的28W高线性度D类放大器，采用混合ΔΣM-PWM方案。

28-W输出功率，91%效率，102.2 dB THD+N，4Ω负载，14.4V电源

JSSC 2020第12期Other

A 4-GS/s 80-dB DR Current-Domain Analog Frontend for Phase-Code d Pulse-Compression Direct Time-of-Flight

130nm CMOS工艺下实现的4GS/s电流域模拟前端，用于相位编码脉冲压缩直接飞行时间汽车激光雷达。

4GS/s采样率, 80dB动态范围, 5pA/√Hz输入参考噪声, 0.225m测距误差(1σ)

JSSC 2020第12期Image Sensors

A 64-Pixel 0.42-THz Source SoC With Spatial Modulation Diversity for Computational Imaging Ritesh Jain

本文介绍了一种专为单像素相机计算成像设计的0.42 THz源SoC，具有空间调制多样性。

0.42 THz, 10.3-dBm最大辐射功率, 10-MHz调制速率, 25帧/s成像速度, 40-dB电压动态范围

JSSC 2020第12期Clocking & PLLsPLL

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional- N Bang–Bang PLL With Digital Frequency-Error Recovery for

提出一种低抖动、低杂散的分数N型BangBang锁相环，采用数字频率误差恢复技术实现快速锁定。

28nm CMOS, 0.17mm²核心面积, 66.20fs rms抖动, 19.8mW功耗

JSSC 2020第12期Data ConvertersSAR ADCOp-Amp

A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique Jia-Ching Wang , Student Member , IEEE

提出一种无需校准的14位100MS/s流水线-SAR ADC，采用加权平均相关电平移位技术。

28nm CMOS, 0.7mW, 100MS/s, 71.7dB SNDR

JSSC 2020第12期Data ConvertersSAR ADC

A Cascaded Noise-Shaping SAR Architecture for Robust

提出级联噪声整形SAR架构，提升系统阶数和信噪比，实现高效稳健的模数转换。

28nm CMOS, 120µW功耗, 0.02mm²面积, 88dB SNDR(100kHz带宽), 177dB Schreier FoM

JSSC 2020第12期RF & Wireless

A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications

本文提出了一种支持Wi-Fi 6的双频段全数字极化发射机，采用28nm CMOS工艺实现。

28nm CMOS, 27 dBm, 53% PE, -30.5 dB EVM, 532 mW

JSSC 2020第12期Power Management

A Monolithic GaN-IC With Integrated Control Loop for 400-V Ofﬂine Buck Operation Achieving 95.6% Peak Efﬁciency

提出一种单片集成控制回路的GaN降压转换器，支持400V离线操作，效率达95.6%。

650V p-GaN栅极增强型GaN-on-Si技术，95.6%效率，29W输出功率

JSSC 2020第12期Power Management

A Monolithic Resonant Switched-Capacitor V oltage Regulator With Dual-Phase Merged- LC Resonator Prescott H. McLaughlin

提出一种集成合并LC谐振器的谐振开关电容电压调节器，提高效率和功率密度。

0.18-µm CMOS, 85.5%效率, 0.47W, <40-mV瞬态波动

JSSC 2020第12期RF & WirelessNeural Network Accelerator

A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver

一款支持5G-NR的多频段FDD SAW-less发射器，采用带宽扩展N路径滤波调制器提升性能。

28nm CMOS, 1.4-2.7GHz, 20MHz带宽, ≤−157.5dBc/Hz带外噪声, 3dBm输出功率, 2.8%-3.6%效率, ACLR1<44dBc, EVM<2%, 0.31mm²面积

JSSC 2020第12期RF & WirelessPower Amplifier

A Multimode Multi-Efficiency-Peak Digital

一款基于SCPA的多模式多效率峰值数字功率放大器，采用Class-G、Doherty和时间交织技术实现六效率峰值。

65nm CMOS, 30-dBm峰值输出功率, 2.4 GHz, 40.2%效率

JSSC 2020第12期RF & WirelessPower Amplifier

A Reconfigurable Hybrid SeriesParallel Doherty Power Amplifier With Antenna VSWR

提出一种可重构混合串并联Doherty功率放大器，有效应对天线阻抗变化带来的性能下降。

39GHz, 33.3% PAE at 20.8dBm Psat, 32.2% PAE1dB at 20.2dBm OP1dB

JSSC 2020第12期RF & WirelessEnergy Harvesting

A Resonant Current-Mode Wireless Power and Data Receiver for Loosely Coupled

提出一种谐振电流模式无线功率与数据接收器，实现高效能量传输与数据传输。

92.6%接收效率@10.89mW, 100kb/s数据速率

JSSC 2020第12期Other

A V ariable-Gain Low-Noise Transimpedance Ampliﬁer for Miniature

用于微型超声探头的可变增益低噪声跨阻放大器设计

±0.9 V供电, 5.2 mW功耗, 1.7 pA/√Hz噪声基底, ±1 dB增益误差

JSSC 2020第12期Data ConvertersNeural Network Accelerator

An 8-Bit 10-GSs 16 Interpolation-Based Time-Domain ADC With 15-ps Uncalibrated Q

一款8位10GS/s时间域ADC，采用16倍时间插值和四通道交织技术，无需校准即可实现15ps量化精度。

65nm CMOS, 1.0V, 10GS/s, 40.1dB SNDR, 50.8mW, 61.5fJ/step

JSSC 2020第12期Power Management

Highly Integrated ZVS Flyback Converter ICs With Pulse Transformer to Optimize U

提出一种高集成度ZVS反激转换器IC，采用脉冲变压器优化USB PD快充方案

20V/3A/60W USB PD转换器，93.5%峰值效率

JSSC 2020第12期RF & WirelessLNA

Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End With On-Antenna Noise-Canceling and Gm-Boosting

本文提出了一种E波段低噪声放大器与多馈天线协同设计的方法，通过天线级噪声消除和gm提升技术，实现了高性能无线前端设计。

4.8-dB NF, 2.2-dBm IIP3

JSSC 2020第12期Other

Multi-Watt, 1-GHz CMOS Circulator Based on Switched-Capacitor

基于开关电容时钟提升技术的多瓦特1GHz CMOS环行器，显著提升功率处理能力和插入损耗。

1-GHz 180-nm SOI CMOS, 2.1-/2.6-dB TX-ANT/ANT-RX IL, +34-dBm TX-ANT P1 dB, 39-mW power consumption

JSSC 2020第12期RF & WirelessTransceiver

NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver 23-dBm CMOS

一款集成NB-IoT和GNSS的全功能SoC芯片，支持多频段通信和23dBm输出功率。

28nm CMOS, 2.5-5V, 15µW always-on power, <10µA sleep current