JSSC 2019 — ISSCC & JSSC 知识库

JSSC 2019第1期Clocking & PLLsPLLTDC

A 0.0043-mm2 0.3–1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC

一种采用推测双参考插值时间数字转换器的合成小数分频数字锁相环，具有宽频率锁定范围和低功耗。

28nm CMOS, 0.3-1.2V, 0.0043mm², FOM < -220dB (VDD > 0.6V)

JSSC 2019第1期Clocking & PLLsDLL

A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

一种采用块共享无偏移频率跟踪环路的超紧凑全数字MDLL，具有低功耗和高性能。

28nm CMOS, 0.8V, 1.55-3.35GHz, 292fs rms jitter, 1.45mW, FoM -249dB

JSSC 2019第1期MemoryEmerging Memory

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination

28纳米1T1MTJ STT-MRAM存储器，采用单电容失调消除感测放大器和原位写入自终止技术

1-Mb容量, 2.8ns/3.6ns读取时间(25°C/120°C), 47%/60%写入功耗降低(25°C/120°C)

JSSC 2019第1期RF & WirelessEqualizerPAM-4

A 112 Gbps PAM-4 56 Gbps NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET

一款采用10nm FinFET工艺的可重构发射器，支持112 Gbps PAM-4和56 Gbps NRZ调制。

112 Gb/s PAM-4调制下功耗232 mW，能效2.07 pJ/b

JSSC 2019第1期Power ManagementHigh-Speed Link

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive V oltage Regulator

16nm FinFET CMOS技术下的25 Gb/s/pin低能耗短距离串行链路

16nm FinFET CMOS, 25 Gb/s/pin, 1.17 pJ/bit

JSSC 2019第1期Wireline I/OPLLEqualizer

A 16-Gb 18-Gbps per pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and P

16Gb GDDR6 DRAM采用每比特可训练单端DFE和ZQ编码发射器，实现18Gbps/pin高速操作

16 Gb/s/pin @1.15V, 18 Gb/s/pin @1.35V

JSSC 2019第1期Other

A 232–1996-kS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological

提出一种232-1996kS/s的鲁棒压缩感知重建引擎，用于实时生理信号监测。

232-1996kS/s, 40nm CMOS

JSSC 2019第1期MemorySRAM

A 23.6-Mb/mm2 SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low- V oltage Applications

10nm FinFET技术中采用脉冲pMOS TVC和阶梯字线技术的高密度SRAM设计

23.6-Mb/mm2和20.4-Mb/mm2 SRAM阵列，0.6-V VMIN

JSSC 2019第1期Digital Circuits

A 55-nm 1004V 125-pJ per MAC Time-Domain Mixed-Signal Neuromorphic Accelerator W

提出了一种55纳米工艺的时域混合信号神经形态加速器，用于强化学习任务，功耗低至690微瓦。

55nm CMOS, 1004V, 125-pJ per MAC, 690 µW peak power

JSSC 2019第1期RF & WirelessEqualizerPAM-4

A 64 Gbps Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS

28nm FDSOI工艺下64Gbps低功耗PAM-4收发器，支持短距电气链路。

28nm CMOS, 1V供电, 64Gbps速率, 2.8mW/Gb/s能效, 10^-12误码率

JSSC 2019第1期Data ConvertersFlash ADC

A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8× Time-Domain Interpolating Flash ADC With Sequential Slope- Matching Offset Calibration Dong-Ryeol Oh, Jong-In Kim, Dong-Shin Jo, Woo-Cheol Kim, Dong-Jin Chang

65nm CMOS工艺下6位2.5GS/s 8倍时域插值闪存ADC，功耗7.5mW。

65nm CMOS, 0.85V, 2.5GS/s, 7.5mW

JSSC 2019第1期RF & WirelessSAR ADCHigh-Speed Link

A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Conﬁgurable ADC in 16-nm FinFET

一款16nm FinFET工艺的双模PAM-4/NRZ收发器，支持19-58Gb/s PAM-4和9.5-29Gb/s NRZ传输。

16nm FinFET, <1e-12 BER, 9.7 pJ/bit

JSSC 2019第1期Power ManagementLDOVCO

A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active V oltage Positioning Using a Beat-Frequency Quantizer

提出一种基于65nm CMOS工艺的全集成数字低压差稳压器，采用拍频量化器和自适应采样技术实现快速响应与低功耗

65nm CMOS, 0.6-1.2V输入, 0.4-1.1V输出, 100mA负载, 99.5%峰值效率

JSSC 2019第1期Power ManagementBoost Converter

A Self-Oscillating Boosting Amplifier With Adaptive Soft Switching Control for P

设计了一种用于水下通信的高压放大器，结合升压和信号生成，提升系统效率。

85%峰值效率，20W输出功率，30kHz信号频率

JSSC 2019第1期Clocking & PLLsVCO

A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation

提出一种基于纹波复制的LC振荡器电源推挤抑制技术，降低电源波动对振荡器性能的影响。

4.9–5.6 GHz, 0.8–1.3 mW, <1 MHz/V supply pushing, <−49 dBc spur (50 mVpp ripple)

JSSC 2019第1期Memory

An Always-On 3.8 μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS

一款超低功耗混合信号二进制CNN处理器，实现CIFAR-10图像分类任务3.8µJ/分类的能效

28nm CMOS, 0.6V/0.8V供电, 237FPS, 0.9mW功耗, 3.8µJ/分类, 86%准确率

JSSC 2019第1期RF & Wireless

An Electronic Dispersion Compensation Transceiver for 10- and 28-Gbps Directly M

提出一种用于10和28 Gbps直接调制激光器的电子色散补偿收发器，通过线性均衡器和双采样决策反馈均衡器改善色散问题。

40nm CMOS, 0.9V, 28 Gb/s

JSSC 2019第1期Power Management

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and VMIN Optimization

14纳米三栅CMOS工艺中集成电压调节器的节能GPU原型，实现动态电压频率调整和能效优化。

14-nm Tri-Gate CMOS, 32% energy reduction at constant performance

JSSC 2019第1期Power ManagementEnergy Harvesting

An ULV PWM CMOS Imager With Adaptive- Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting Albert Yen-Chih Chiou and Chih-Cheng Hsieh

本文介绍了一种超低电压PWM CMOS图像传感器，适用于物联网和人工智能应用。

0.18-µm CMOS, 0.4V, 60.1 dB PSNR, 141 dB DR

JSSC 2019第1期Data ConvertersDelta-Sigma ADCOp-Amp

Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Negative-R

提出一种负阻辅助积分器，显著降低连续时间ΔΣ调制器的功耗。

65nm CMOS, 1.2V, 20/24-kHz带宽, 55/68 µW功耗

JSSC 2019第1期MemorySRAMNeural Network Accelerator

CONV-SRAM- An Energy-Efficient SRAM With In-Memory Dot-Product Computation for L

提出一种能效优化的SRAM，支持内存内点积计算，用于二进制权重卷积神经网络。

>98%准确率（MNIST数据集测试），6位输入/输出

JSSC 2019第1期Power ManagementLDO

Capacitorless Self-Clocked All-Digital Low-Dropout Regulator

一种无电容自时钟数字低压差稳压器，采用自移位双向移位寄存器加速瞬态响应。

65nm CMOS, 0.7-1.2V, 77ns瞬态响应时间, 96mV下冲, 99.86%峰值电流效率, 94.16%峰值功率效率

JSSC 2019第1期Clocking & PLLsCrystal Oscillator

Design of Crystal-Oscilla tor Frequency Quadrupler for Low-Jitter

设计了一种基于晶体振荡器的频率四倍器，用于低抖动时钟乘法器，实现了216MHz参考时钟和77fs rms的集成抖动。

65nm CMOS, 1.0V, 6.5mW, 366fs rms抖动

JSSC 2019第1期Power Management

IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems Christopher Berry , David Wolpert, Christos Vezrytzis, Richard Rizzolo, Sean Carey, Yaniv Maroz, Hunter Shi, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito

IBM z14处理器的高可靠性设计与先进电源管理技术

5.2-GHz高功率设计

JSSC 2019第1期Data Converters

Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC)

2018年ISSCC会议精选论文集，涵盖高速有线收发器、光学技术和时钟生成等领域的进展。

64-Gb/s, 56-Gb/s, 112-Gb/s, 1.17-pJ/bit, 25-Gb/s/pin, 28-Gb/s

JSSC 2019第1期MemorySRAMDRAM

QUEST- Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRA

QUEST是一款采用3D堆叠技术的多用途对数量化DNN推理引擎，具有高带宽和低延迟特性。

7.49 TOPS（二进制精度）, 1.96 TOPS（4位精度）, 300MHz时钟频率

JSSC 2019第1期OtherPAM-4

Table of contents

IEEE JSSC期刊论文摘要，涵盖多篇关于高速低功耗收发器的研究。

64 Gb/s, 19-58 Gb/s, 112 Gb/s

JSSC 2019第1期Digital CircuitsNeural Network Accelerator

UNPU- An Energy-Efficient Deep Neural Network Accelerator With Fully

提出一种能效优化的深度神经网络加速器UNPU，支持可变权重精度和多种网络层类型。

65nm CMOS, 0.63-1.1V, 200MHz, 峰值性能345.6GOPS(16bit)-7372GOPS(1bit)

JSSC 2019第1期Other

Zeppelin- An SoC for

AMD的Zeppelin SoC采用无限架构技术，支持多芯片扩展，适用于多种市场。

14nm FinFET, 4.8B transistors, 213mm² die

JSSC 2019第2期Clocking & PLLs

12-Gbps Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces

提出一种新型高效引脚/能量信号方案——编织时钟信号(BCS)，在12Gbps速率下实现无数据开销的时钟嵌入。

12-Gb/s, 28-nm CMOS, 四线平衡传输

JSSC 2019第2期Other

85110-GHz CMOS Magnetic-Free Nonreciprocal Components for Full-Duplex Transceive

展示两种用于全双工收发器的CMOS非互易组件：隔离器和环行器，在100GHz频段实现超过45dB隔离。

45dB隔离度，1.5GHz带宽，4.5-5.6dB插入损耗

JSSC 2019第2期Data ConvertersDelta-Sigma ADC

A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer

本文提出了一种紧凑且高效的三阶连续时间ΔΣ ADC，采用单OTA和4位二阶全被动噪声整形SAR ADC作为量化器。

40nm CMOS, 1.16mW, 500MHz采样频率, 70.4dB SNDR, 17fJ/转换步

JSSC 2019第2期OtherPhased Array

A 0.53-THz Subharmonic Injection-Locked Phased Array With 63-μW Radiated Power in 40-nm CMOS

0.53-THz次谐波注入锁定相控阵，采用ILO链补偿相位误差，实现60°波束扫描。

529-534GHz输出频率，-12dBm辐射功率，0.24‰ DC-to-THz效率，260mW功耗

JSSC 2019第2期Data ConvertersSAR ADCDAC

A 10-b 20-MSs SAR ADC With DAC-Compensated Discrete-Time

提出一种带DAC补偿的离散时间参考驱动器的10位20MS/s SAR ADC，降低功耗和面积。

10-bit, 20MS/s, 65nm CMOS

JSSC 2019第2期Other

A 141-µW High-V oltage MEMS Gyroscope Drive Interface Circuit Based on

基于飞电容的141微瓦高压MEMS陀螺仪驱动接口电路

141 µW, 0.58 mm²

JSSC 2019第2期RF & WirelessPLL

A 37-mW 24-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation

一种基于BBPLL的低功耗24GHz GFSK接收器，采用1位相位数字转换技术

65nm CMOS, 0.8V, 100kb/s, -89dBm灵敏度, 3.7mW功耗

JSSC 2019第2期Other

A 42 nJ per Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-

提出一种用于微型物联网电池的低功耗电量指示算法与系统，实现按需精确测量。

42 nW功耗，最大电量指示误差1.7%，最小适用电池容量2 µAh

JSSC 2019第2期RF & WirelessEqualizer

A 64-Gbps 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET

16nm FinFET工艺的64Gbps 4-PAM收发器，采用自适应阈值ADC优化功耗与误码率。

16nm FinFET, 1.2V, 64Gbps, 1.39pJ/bit, BER<1e-6

JSSC 2019第2期Data ConvertersSAR ADC

A 78.5-dB SNDR Radiation- and Metastability- Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS

本文提出了一种14位抗辐射和抗亚稳态的两步分裂SAR ADC，峰值SNDR达78.5dB，峰值SFDR达103dB。

14-bit, 78.5-dB SNDR, 103-dB SFDR, 35 MS/s, <25-mW

JSSC 2019第2期MemoryEqualizerSRAM

A 7T-SRAM With Data-Write Technique by

提出一种通过电容耦合写入数据的7T-SRAM，解决电流冲突问题并提升稳定性。

24nm 3.3V CMOS, 1.5V/1.8V Vdd, 20ns/10ns cycle time, 18ns/10ns access time, 400 FIT/Mb SER

JSSC 2019第2期RF & Wireless

A Four-Camera VGA-Resolution Capsule Endoscope System With 80-Mbps Body Channel Communication Transceiver and Sub-Centimeter Range

提出一种采用四摄像头集成和体信道通信技术的无线胶囊内窥镜系统，实现VGA分辨率图像传输和精确定位。

80 Mbps传输速率，<1mW功耗，亚厘米级定位精度，8小时续航（4 fps）

JSSC 2019第2期RF & WirelessBiosignal

A Low-Power Compact IEEE 802.15.6 Compatible Human Body Communication Transceiver With Digital Sigma–Delta IIR

提出一种低功耗紧凑型IEEE 802.15.6兼容人体通信收发器，采用掩模整形技术抑制低频干扰。

65nm CMOS, 3.52mW(发射)/620μW(接收), -72dBm灵敏度@5.25Mc/s

JSSC 2019第2期Power Management

A Low-Power, Differential Relaxation Oscillator With the Self-Threshold-Tracking and Swing-Boosting Techniques in 0.18- μmC M O S

一种采用自阈值跟踪技术的低功耗差分弛豫振荡器

0.18-µm CMOS, 8.2-MHz, 46.3 µW, 7.66 ps rms抖动, -109 dBc/Hz相位噪声

JSSC 2019第2期Other

A ReRAM Macro Using Dynamic Trip-Point- Mismatch Sampling Current-Mode Sense Ampliﬁer and Low-DC V oltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King

提出动态跳变点失配采样电流模式感测放大器和低直流电流电压模式写入终止模块，提升ReRAM读取性能和写入效率。

65nm CMOS, 2-Mb容量, 读取延迟2.6ns

JSSC 2019第2期Data ConvertersPipeline ADC

A Single-Channel 600-MSs 12-b Ringamp-Based Pipelined ADC in 28-nm CMOS

28nm CMOS工艺下基于环形放大器的600MS/s 12位流水线ADC设计

28nm CMOS, 0.9V, 600MS/s, 58.7dB SNDR, 72.4dB SFDR, 14.5mW

JSSC 2019第2期Other

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI

一种用于统计表征CMOS晶体管变异性的多功能阵列芯片。

1.2-V, 65-nm CMOS, 3136 MOS transistors, 1800 × 1800 µm²

JSSC 2019第2期Image Sensors

An 80 x 25 Pixel CMOS Single-Photon Sensor With Flexible On-Chip Time Gating of 40 Subarrays for Solid-State 3-D

一款采用灵活时间门控方案的CMOS单光子传感器，用于3D距离成像。

80 × 25像素阵列，10帧/秒，厘米级精度，4米范围，18°×28°视场，0.1mW平均激活照明功率

JSSC 2019第2期Clocking & PLLsPLLTDC

An 82–107.6-GHz Integer- N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta–Sigma TDC

提出一种W波段整数N全数字锁相环，具有宽频率调谐范围和低相位噪声。

82-107.6 GHz, 27%频率调谐范围, -106至-110 dBc/Hz@10MHz, -84至-87 dBc/Hz@100kHz, 35.5 mW功耗, 0.36 mm²核心面积

JSSC 2019第2期Other

An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI

双模逻辑（DML）通过自适配机制在28nm SOI工艺中实现高性能与低能耗的乘法累加电路。

28nm FDSOI, 0.4V-0.9V, 40MHz-1GHz

JSSC 2019第2期Image Sensors

Compensation Pixel Circuit to Improve Image Quality for Mobile AMOLED Displays

提出一种新型LTPS TFT像素电路，通过延长补偿时间提高AMOLED显示质量

1.3英寸面板，补偿时间33.3µs，255灰度级

JSSC 2019第2期RF & Wireless

High-Linearity Bottom-Plate Mixing Technique With Switch Sharing for N-path Filters-Mixers

提出一种高线性度底极板混频技术，用于SAW-less FDD接收机，实现低噪声和高线性度。

28nm CMOS, +44 dBm OOB IIP3, +90 dBm IIP2, +13 dBm 1-dB压缩点, 38-96 mW功耗

JSSC 2019第2期Other

Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast V oltage Dithering

通过随机快速电压抖动和时钟调制技术提升AES引擎的抗侧信道攻击能力

37倍TVLA峰值降低，692倍CPA最小追踪数增加

JSSC 2019第2期Other

Table of contents

本期IEEE JSSC论文涵盖了多种低功耗、高性能的射频与模拟电路设计。

3.7mW, 2.4GHz, 600MS/s, 12b

JSSC 2019第2期Clocking & PLLs

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

提出一种18晶体管全静态无竞争单相时钟触发器，实现低功耗和面积优化。

65nm CMOS, 0.6V, 25°C

JSSC 2019第3期Other

34-GBd Linear

提出一种34-GBd线性跨阻放大器，用于高速相干光通信接收机。

20-pA/√Hz输入参考噪声密度, 27-GHz 3-dB带宽, 1.5%总谐波失真

JSSC 2019第3期Power Management

AC-Coupled Stacked Dual-Active-Bridge DC–DC Converter for Integrated Lithium-Ion Battery

提出一种AC耦合堆叠双有源桥DC-DC转换器，用于集成锂离子电池供电系统。

0.15-µm CMOS, 3.2–4.2V输入, 0.8–1.5V输出, 87.2%峰值效率

JSSC 2019第3期Data ConvertersPipeline ADC

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Ampliﬁers

采用死区退化和第二级偏置增强技术的12位1GS/s流水线ADC，在28nm CMOS工艺下实现高性能。

28nm CMOS, 0.9V, 1GS/s, 56.6dB SNDR, 73.1dB SFDR, 24.8mW

JSSC 2019第3期Other

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient

130纳米铁电非易失性系统芯片，支持快速外设恢复，提升能效与集成度。

130-nm ferroelectric-CMOS, 22.09-mm² area, 6× higher data throughput

JSSC 2019第3期Clocking & PLLs

A 15-Gbps Sub-Baud-Rate Digital CDR

一种采用亚波特率时钟的15Gbps数字CDR电路，利用四分之一速率时钟实现高效数据恢复。

65nm CMOS, 15.2Gb/s, BER<10^-12, >10MHz JTOL, 548fs rms抖动, 29mW功耗, 1.9pJ/bit能效

JSSC 2019第3期RF & WirelessEqualizerPAM-4

A 52-Gbps ADC-Based PAM-4 Receiver

一款基于ADC的PAM-4接收器，采用32路时间交织SAR ADC和数字均衡技术，实现52Gbps高速数据传输。

52-Gbps数据传输速率，BER<10−6（31dB损耗信道）

JSSC 2019第3期Other

A 53-Gbitps Optical

28纳米CMOS工艺实现的光学接收前端，支持53Gbps传输速率

28nm CMOS, 27GHz带宽, 53Gbit/s传输速率, 0.65pJ/bit能效

JSSC 2019第3期Data ConvertersTime-Interleaved ADC

A 56-GSps 8-bit Time-Interleaved ADC

本文介绍了一种56GS/s时间交织ADC，采用多种技术提升带宽和ENOB。

28nm CMOS, 56GS/s, 5.7-b ENOB, 31.5GHz BW

JSSC 2019第3期RF & WirelessEqualizerPAM-4

A 56-Gbps PAM4 Receiver With Low-Overhead Techniques

本文介绍了一种56-Gbps PAM4接收器，采用低开销技术有效补偿信道损耗。

56-Gb/s, 4.63 mW/Gb/s, BER < 10^-12

JSSC 2019第3期Data ConvertersSAR ADCDAC

A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter

本文提出了一种采用单位长度电容和被动FIR滤波器的紧凑型10位SAR ADC，实现了高线性度和小面积。

65nm CMOS, 10/30 MS/s, 9.18/9.10 ENOB, 4.1/4.4 fJ per conversion-step

JSSC 2019第3期RF & WirelessPower Amplifier

A Compact Transformer-Combined Pola-Quadrature Reconfigurable Digital Power Amplifier in 28-nm Logic LP CMOS

一种支持极坐标和正交发射机的紧凑型变压器结合可重构数字功率放大器。

28.8-dBm峰值功率, 30.8%峰值PAE, 0.56 mm²面积

JSSC 2019第3期Power Management

A Fully Integrated Li-Ion-Compatible Hybrid Four-Level DCDC Converter in 28-nm F

本文提出了一种兼容锂离子的全集成混合四电平DC-DC转换器，适用于穿戴设备和物联网应用。

28nm FDSOI, 0.6-1.2V输出, 2.8-4.2V输入, 78%峰值效率, 200MHz开关频率

JSSC 2019第3期RF & Wireless

A Harmonic-Selective Multi-Band Wireless Receiver With

一款基于谐波选择的多频段无线接收器，采用数字谐波抑制校准技术。

2.4–5-dB噪声系数(NF), -10-dBm带外阻塞容忍, 80 dB谐波抑制

JSSC 2019第3期OtherClock Generation

A Low-Noise Fractional- N Digital

提出一种60GHz分数-N数字频率合成器，降低相位噪声并优化功耗。

213–277fs RMS抖动，57.5–67.2GHz调谐范围，40mW功耗

JSSC 2019第3期Data Converters

A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain

提出一种基于VCO的非均匀采样ADC，通过相位域电平交叉提高带宽并降低成本。

200-MHz带宽, 60-dB动态范围, 19.7 mW功耗, 0.13 mm²面积

JSSC 2019第3期Clocking & PLLsVCO

A Noise Circulating Oscillator

提出一种噪声循环交叉耦合压控振荡器，显著降低相位噪声并提升性能指标。

2.35GHz, 1.2V, 2.15mA, 193.1dBc/Hz FoM@100kHz, 18.6%调谐范围

JSSC 2019第3期Power ManagementBuck Converter

A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output V oltage Range

采用时间域电路实现电流模式降压转换器，具有宽输出电压范围和高效能。

0.15-1.69V输出(1.8V输入), 0.6A最大负载, 94.9%峰值效率(1.5V/250mA), <3.5μs负载瞬态响应

JSSC 2019第3期RF & Wireless

A Wake-Up Receiver With a Multi-Stage Self-Mixer and With Enhanced Sensitivity When Using an Interferer as

一种采用多级自混频器的超低功耗唤醒接收器，具有增强的灵敏度。

0.13-µm CMOS, 0.5V, 220nW, -56.4dBm@400kb/s, -63.6dBm@1.1µW

JSSC 2019第3期Digital Circuits

Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-

提出自适应人工神经网络耦合LDPC纠错码，显著提升3D和2D NAND闪存的容错能力。

数据保持时间提升76倍（3D NAND）和45倍（2D NAND）

JSSC 2019第3期Power Management

An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain V oltage

提出一种利用亚阈值电流的11nW超低功耗CMOS温度数字转换器。

11nW, -20°C to 80°C, 145mK resolution

JSSC 2019第3期Other

An Energy-Efficient 37-nVpHz Bridge Readout IC

本文介绍了一种高效能的桥式读出集成电路，具有低噪声和高线性度。

输入噪声密度3.7 nV/√Hz，噪声效率因子5，功率效率因子44

JSSC 2019第3期OtherNeural Network Accelerator

An Inductive Voltage-Current-Mode Integrated

一种具有无缝电压-电流模式操作和能量回收功能的集成电源管理芯片。

3V稳压输出，142kHz LC-tank开关频率，输入电压范围宽（无死区）

JSSC 2019第3期MemorySRAM

Bitline Charge-Recycling SRAM Write Assist Circuitry for VMIN Improvement and Energy Saving Hanwool Jeong, Se Hyeok Oh, Tae Woo Oh , Hoonki Kim, Chang Nam Park

提出基于位线电荷回收的SRAM写入辅助电路，降低最小工作电压并提升能效。

14nm FinFET, VMIN降低150mV, 能效提升11%-66%

JSSC 2019第3期RF & Wireless

Design and Analysis o f a DCO-Based Phase- Tracking RF Receiver for IoT Applications

设计并分析了一种基于DCO的相位跟踪射频接收器，适用于物联网应用，具有高能效和小面积特点。

40nm CMOS, 0.85V, 2 Mb/s, 1.55 mW, -87dBm灵敏度

JSSC 2019第3期Other

Integrated Synthetic Fourth-Order Q-Enhanced

本文展示了一种可调谐的微波四阶Q增强带通滤波器，采用130nm SiGe BiCMOS工艺实现。

4-8GHz中心频率可调, 2%-25%带宽可调, 151-166dB·Hz动态范围, 112-125mW功耗

JSSC 2019第3期Other

Introduction to the Special Section on the 2018

2018年定制集成电路会议精选论文扩展版合集，涵盖多种集成电路设计领域。

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JSSC 2019第3期Data Converters

Table of contents

本文介绍了几种低功耗、高性能的CMOS温度数字转换器和ADC设计。

11-nW, 1-GS/s, 12-b, 52-Gb/s, 56-Gb/s, 15-Gb/s

JSSC 2019第4期Data ConvertersSAR ADCVCO

A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator

提出一种利用VCO比较器振荡周期信息实现自适应旁路的SAR ADC，提高能效。

40nm CMOS, 0.511V, 10MS/s, 9.71b ENOB, 2.4–6.85 fJ/conv.-step FoM

JSSC 2019第4期RF & WirelessBiosignal

A 0.8-V 82.9- μW In-Ear BCI Controller IC With 8.8 PEF EEG Instrumentation Ampliﬁer and Wireless BAN Transceiver

一款用于耳内脑机接口的低功耗控制器芯片，具有高能效EEG放大器。

65nm CMOS, 8.8 PEF, 829μW

JSSC 2019第4期Other

A 1-mW Class-AB Ampliﬁer With −101 dB THD+N for High-Fidelity 16 Headphones in 65-nm CMOS

一款用于高保真耳机的低功耗AB类放大器，实现-101.4dB THD+N和0.97mW静态功耗。

65nm CMOS, 0.97mW静态功耗, -101.4dB THD+N, 12.3MHz UGB, 108dB SNR, 51.2mW峰值功率

JSSC 2019第4期Data ConvertersSAR ADCNeural Network Accelerator

A 12-Bit 311-μW 1-MSs SAR ADC With On-ChipInput-Signal-Independent Calibration A

一款12位1MS/s低功耗SAR ADC，采用片上输入信号无关校准技术，实现100.4dB无杂散动态范围。

12-bit, 311μW, 1MS/s, 100.4dB SFDR, 256fF采样电容

JSSC 2019第4期Wireline I/O

A 128-Gbps Daisy Chain-Based Downlink IF Employing Spectrally Compressed Multi-B

提出一种基于频谱压缩多带复用的新型菊花链下行接口，实现高带宽、低功耗的NAND闪存存储系统。

12.8-Gb/s吞吐量，BER 10^-12，发射机功耗252.1mW，接收机总功耗375.7mW

JSSC 2019第4期Digital Circuits

A 1920 × 1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Uniﬁed Optical Flow and Stereo Depth With Semi-Global Matching

一款支持全高清实时3D深度与运动感知的低功耗6D视觉处理器

28nm CMOS, 1920×1080@25fps/30fps, 760mW

JSSC 2019第4期MemorySRAM

A 290-mV , 7-nm Ultra-Low-V oltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell

7nm FinFET工艺下290mV超低电压单端口SRAM编译器设计

7nm FinFET, 290mV Vmin

JSSC 2019第4期Clocking & PLLsTDC

A 30-frames/s, 252 × 144 SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming Chao Zhang , Scott Lindner , Ivan Michel Antolovi´c , Juan Mata Pavia

一款252×144 SPAD像素传感器，采用180nm CMOS工艺，支持30帧/秒的闪光LiDAR成像。

180nm CMOS, 48.8ps TDC分辨率, 28.5μm像素间距, 30帧/秒, 50m测距精度8.8cm

JSSC 2019第4期Digital Circuits

A 4096-Neuron 1M-Synapse 38-pJ per SOP SpikingNeural Network With On-Chip STDP L

10nm FinFET CMOS工艺的4096神经元、100万突触SNN芯片，支持片上STDP学习，能效达3.8pJ/SOP。

25.2 GSOP/s@0.9V, 3.8pJ/SOP@525mV, 2.3μW/neuron@450mV

JSSC 2019第4期RF & WirelessPLL

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS

一种55GHz背景校准的亚采样极化发射器，具有413dB EVM性能

5.5 GHz, 2.5 MHz BW (1024 QAM), 1.1-dBm输出功率, 50 mW总功耗

JSSC 2019第4期Other

A 550-μ W 20-kHz BW 1008-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ AD

提出一种两阶段线性-指数累积环路的增量型模数转换器，结合线性阶段的噪声抑制和指数阶段的SQNR提升。

65nm CMOS, 1.2V, 20kHz BW, 100.8dB SNDR, 550μW

JSSC 2019第4期OtherCMOS Image Sensor

A 5500-frames per s 85-GOPS per W 3-D Stacked BSIVision Chip Based on Parallel I

本文介绍了一种基于3D堆叠技术的视觉芯片，具有高帧率和高能效比。

5500帧/s, 85 GOPS/W

JSSC 2019第4期Power ManagementBuck Converter

A Hybrid Structure Dual-Path Step-Down Converter With 96.2% Peak Efﬁciency Using 250-m Large-DCR Inductor

采用混合结构的双路径降压转换器，峰值效率达96.2%，解决传统降压转换器功率损耗问题。

250mΩ电感，峰值效率96.2%，功率损耗降低至传统方案的30%

JSSC 2019第4期RF & WirelessPower Amplifier

A Subharmonic Switching Digital Power Amplifierfor Power Back-Off

提出一种次谐波开关数字功放架构，提升功率回退区效率

26.8-dBm峰值输出功率，49.3%峰值漏极效率(DE)，-13dB PBO时27% DE

JSSC 2019第4期Image SensorsCMOS Image Sensor

A Time-Resolved NIR Lock-In Pixel CMOS Image Sensor With Background Cancelling Capability for

一种具有背景光消除功能的近红外锁相像素CMOS图像传感器，用于远程心率检测。

1024×1280分辨率，30fps帧率，134.8ke-/lux·s灵敏度，1.13e-rms噪声

JSSC 2019第4期Clocking & PLLs

A Uniﬁed Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-V oltage SoC Domains

提出一种结合时钟和电容开关技术的电源架构，显著降低电压保护带需求

16% Vdd降低/94% Vdd裕度恢复/3.2倍频率提升

JSSC 2019第4期Other

An All-Digital Unified Physically UnclonableFunction and True Random Number GeneratorFeaturing Self-Calibrating HierarchicalVon Neumann Extraction in14-nm Tri-gate CMOS

一种基于14nm三栅CMOS的全数字统一物理不可克隆函数和真随机数生成器

14nm CMOS, 650mV, 70°C, 1.48Gb/s PUF, 0.56Gb/s TRNG

JSSC 2019第4期Digital Circuits

An Energy-Efﬁcient Reconﬁgurable Processor for Binary- and Ternary-Weight Neural Networks With Flexible Data Bit Width Shouyi Yin , Peng Ouyang, Jianxun Yang, Tianyi Lu , Xiudong Li

提出一种能效优化的可重构处理器，用于加速二值和三值权重神经网络的推理。

28nm CMOS

JSSC 2019第4期Clocking & PLLsVCO

An Ultra-Low-Jitter 22.8-GHz Ring- LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114

提出一种超低抖动的228GHz环形-LC混合注入锁定时钟倍频器，采用双用途频率校准器优化性能。

65nm CMOS, 153fs RMS抖动, 7.4mW总功耗

JSSC 2019第4期Clocking & PLLs

Chip-Scale Molecular Clock

基于65nm CMOS工艺的分子钟芯片，通过锁定OCS气体分子旋转模式实现高稳定时钟输出。

65nm CMOS, 231.061GHz PLL, 66mW功耗, 3.8×10⁻¹⁰艾伦偏差(τ=1000s)

JSSC 2019第4期Power Management

Design of Single-Topology Continuously Scalable-Conversion-Ratio Switched- Capacitor DC–DC Converters

提出一种新型高效单拓扑可调转换比开关电容DC-DC转换器。

28nm CMOS, 峰值效率93%, 输出电压范围0.9-2.03V, 输入电压2V时效率>90%

JSSC 2019第4期Other

Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits

2018年VLSI电路研讨会精选论文，涵盖集成电路与系统设计的前沿技术与成果。

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JSSC 2019第4期MemoryEmerging Memory

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5-nS Read

40纳米逻辑工艺兼容16Mb嵌入式垂直MRAM，采用混合电阻参考和单元位置补偿技术提升读取性能。

40nm CMOS, <±1 µA分辨率, 17.5 nS读取时间, -40°C至125°C工作温度

JSSC 2019第4期Digital Circuits

Navion: A 2-mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of

Navion是一款2mW全集成实时视觉-惯性里程计加速器，用于微型机器人和VR/AR设备导航。

65nm CMOS, 752×480立体图像@20fps/2mW, 峰值171fps/52kHz@24mW

JSSC 2019第4期RF & Wireless

Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s R e v e r s eD a t aO v e raS i n g l eP a i ro fC o i l s

通过单对感应线圈实现94mW无线功率传输和反向数据通信的自调节系统。

94mW功率传输，4.2cm传输距离，3cm直径线圈，40倍负载电流变化容限

JSSC 2019第4期Data Converters

Table of contents

IEEE JSSC期刊论文涵盖芯片级分子钟、低抖动时钟乘法器、低功耗SAR ADC等前沿技术。

22.8GHz, 12-bit, 31.1μW, 1MS/s, 65nm CMOS

JSSC 2019第5期RF & Wireless

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efﬁciency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS

本文介绍了一种超低电压能量收集BLE发射器，系统效率达25%。

28nm CMOS, 0.2V, 25%系统效率, 0.53mm²面积

JSSC 2019第5期OtherPhased Array

A 1-GHz 16-Element Four-Beam True-Time-Delay

首个采用基带真实时延技术的16元素四波束数字波束成形器，解决了高频宽应用中的波束偏斜问题。

16元素波束成形器，SFDR提升13.7 dB，EVM优于37 dB，总面积0.29 mm²，总功耗453 mW

JSSC 2019第5期Data ConvertersSAR ADC

A 12-Bit 300-MSs Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC

提出一种新型12位300MS/s单通道流水线-SAR ADC，采用开环MDAC设计，提升速度与能效。

12位, 300MS/s, 63.6dB SNDR, 12.5mW, 1.2V

JSSC 2019第5期Clocking & PLLsPLL

A 24-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-N

一种新型24GHz参考采样锁相环，同时实现低噪声和低杂散性能。

65nm CMOS, 2.05-2.55GHz, 抖动功率优值<-251dB, 参考杂散<-66dBc@50MHz

JSSC 2019第5期RF & Wireless

A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture W

一款基于LO移相架构的28GHz CMOS相控阵收发芯片，支持5G NR，实现高精度波束控制与低旁瓣水平。

28-GHz, 15.7 dBm P1dB, 4.1 dB NF, 39.8 dBm EIRP, 15 Gb/s 64-QAM

JSSC 2019第5期RF & Wireless

A 28-GHz Flip-Chip Packaged Chireix Transmitter With On-Antenna

一款28GHz Chireix发射器，利用双馈环天线实现高效功率放大和负载调制。

53%/43% PA drain/power-added efficiency at 17.1-dBm saturated output power

JSSC 2019第5期RF & WirelessPLL

A 28-nm 75-fs rms Analog Fractional- N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference

28纳米工艺下实现75飞秒抖动的高线性DTC模拟分数N采样PLL

28nm CMOS, 75-fs rms抖动, -249.7-dB FoM, 18.9 mW功耗

JSSC 2019第5期RF & Wireless

A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide

一款采用65nm CMOS工艺的32单元240GHz外差接收器阵列，具有阵列级相位锁定功能。

65nm CMOS, 240GHz, 32单元, 980mW功耗, -84dBc/Hz相位噪声(1MHz偏移), 58fW单单元灵敏度

JSSC 2019第5期Analog CircuitsNeural Network Accelerator

A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

65nm CMOS工艺下实现的40GHz带宽镜像共源共栅差分跨阻放大器

54dBΩ跨阻增益/40GHz带宽/19.8pA/√Hz噪声密度/55.2mW功耗/32Gb/s PRBS眼图

JSSC 2019第5期RF & Wireless

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

一款支持IEEE 802.11ay标准的60GHz CMOS收发器，具有LOFT和I/Q不平衡校准功能，实现高数据速率和低功耗。

128 QAM下24.64 Gb/s，64 QAM下42.24 Gb/s，最高50.1 Gb/s，发射模式功耗169 mW，接收模式功耗139 mW

JSSC 2019第5期RF & WirelessTransceiverNeural Network Accelerator

A 60-GHz 30-Gbs Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range W

一种60GHz低功耗短距离无线收发器，采用BPOOK调制方案，实现高谱效和低功耗。

3.0 Gb/s, 100 mW, 1-V supply, -46 dBm sensitivity

JSSC 2019第5期Data ConvertersPipeline ADCOp-Amp

A 75.3-dB SNDR 24-MS/s Ring Ampliﬁer-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite

提出ACLS和RS技术，降低流水线ADC中运放增益和电容失配误差，实现16位高性能ADC。

90nm CMOS, 24 MS/s, 74.3-dB SNDR, 85.5-dB SFDR, 5.1 mW

JSSC 2019第5期Data ConvertersNeural Network Accelerator

A Dynamic Power Reduction Technique for

提出一种动态功耗降低技术，应用于增量Delta Sigma调制器，通过增加非理想性节省功耗。

180nm CMOS, 3V, 200kS/s, 91.5/86.6 dB SNDR, 1.1mW

JSSC 2019第5期Other

A Flexible Phased-Array Architecture for Reception and Rapid Direction-of-Arrival Finding Utilizing Pseudo-Random Antenna

一种可重构的相控阵接收架构，结合传统波束成形和压缩采样快速方向估计。

1-3 GHz, 32-dB转换增益, 3.3-dBm IIP3, 6.4-dB NF, 19.8 mW功耗

JSSC 2019第5期Other

A Noise-Immunity-Enhanced Analog Front-End for Touch-Screen Controllers With 20-

设计了一种具有高抗噪能力的触摸屏控制器模拟前端，采用多通道驱动和噪声过滤接收结构。

54-dB SNR, 120-Hz帧率, 20-V PP噪声抗扰度

JSSC 2019第5期OtherPhased Array

A Nonuniform Sparse 2-D Large-FOV Optical Phased Array With a Low-Power PWM Drive

提出一种低功耗非均匀稀疏二维大视场光学相控阵，实现高分辨率和低功耗。

128单元孔径，16°/0.8°无栅瓣视场-波束宽度比，484单元等效均匀阵列，400可分辨点

JSSC 2019第5期RF & WirelessPhased ArrayNeural Network Accelerator

A Reconfigurable 28-37-GHz MMSE-Adaptive Hybrid-Beamforming Receiver for Carrier Aggregation and Multi-Standard MIMO Communication

提出一种可重构28-37GHz混合波束成形接收器，支持多标准MIMO模式和载波聚合模式。

28-/37-GHz, 65-nm CMOS, 四天线输入双基带输出

JSSC 2019第5期RF & Wireless

A Watt-Level Quadrature Class-G Switched-Capacitor Power

基于Class-G IQ-cell-shared SCPA和电压失配补偿技术的30.1dBm正交发射机，实现瓦级输出功率。

30.1dBm峰值输出功率，37.0%系统效率，802.11g 64-QAM OFDM信号下EVM为-40.7dB

JSSC 2019第5期Clocking & PLLs

A pW-Power Hz-Range Oscillator Operating With a 03-18-V

一种可在0.3-1.8V宽电压范围内工作的pW级Hz振荡器，适用于传感器节点。

180nm CMOS, 0.3-1.8V, 4Hz, 8-18pA, 1600µm²

JSSC 2019第5期RF & WirelessPower Amplifier

An E-Band Power Amplifier With 263 PAE and 24-GHz Bandwidth in 22-nm FinFET CMOS

本文介绍了一种在22nm FinFET CMOS工艺中实现的E波段功率放大器，具有高效率和宽带宽。

22nm FinFET CMOS, 18.6 dB峰值增益, 62–86 GHz带宽, 26.3%峰值PAE

JSSC 2019第5期RF & WirelessVCO

Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 × Frequency

设计了一种基于全数字环形振荡器的超低功耗蓝牙低能耗发射器，适用于短距离物联网应用。

40nm CMOS, 486µW功耗, 0.0166mm²面积

JSSC 2019第5期Other

IEEE JOURNAL OF SOLID-STATE CIRCUITS

IEEE固态电路期刊的会员信息及编辑团队介绍

无

JSSC 2019第5期Other

Information

IEEE JSSC期刊专注于集成电路分析与设计，鼓励实验验证。

无

JSSC 2019第5期Other

Introducing IEEE Collabratec

介绍IEEE Collabratec平台

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JSSC 2019第5期Other

Introduction to the Special Section on the 2018 RFIC Symposium

2018年RFIC研讨会精选论文，涵盖射频与毫米波集成电路的前沿技术与应用。

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JSSC 2019第5期Analog Circuits

Inverter-Based Subthreshold Amplifier Techniques and Their Application in 03-V D

本文提出基于反相器的亚阈值放大器技术，显著提升0.3V工作下的性能与效率。

0.3V, 74.1-dB SNDR, 83.4-dB SFDR, 20-kHz带宽, 79.3μW

JSSC 2019第5期Other

Non-Magnetic CMOS Switche d-Transmission-Line Circulators With High Power Handling and Antenna Balancing: Theory and Implementation

提出一种无磁CMOS循环器，实现高功率处理和高线性度。

1-GHz, 180-nm SOI CMOS, >1-W TX–ANT P1dB, >+50-dBm TX–ANT IIP3, 2.1/2.9 dB插入损耗, 3.1 dB ANT–RX噪声系数

JSSC 2019第5期RF & Wireless

Secure Satellite Communication Digital IF CMOS Q-Band Transmitter and K -Band Receiver

首款CMOS RF集成芯片组，用于安全卫星通信，支持低SWaP终端。

200-/300-MHz DDR接口，>30-dB spur抑制，24-dBm Q-band PA

JSSC 2019第5期RF & WirelessPhased Array

Table of contents

IEEE JSSC期刊论文涵盖了多个前沿技术领域，包括光学相控阵、毫米波接收器、5G通信和锁相环设计等。

28GHz, 240GHz, 28nm CMOS, 65nm CMOS

JSSC 2019第5期Other

Together we are advancing technology

无摘要无法提供概要

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JSSC 2019第5期Other

Ultrasonic Wake-Up With

提出一种毫米级超声波唤醒接收器，利用预充电换能器实现高灵敏度超低功耗唤醒

灵敏度-59.7dBm@BER 10^-3，功耗8nW，面积14.5mm²

JSSC 2019第6期OtherFlash Memory

3-D NAND Flash Value-Aware SSD Error-Tolerant SSD Without ECCs for

提出一种无需ECC的Value-Aware SSD，通过DNN图像识别的容错性提升可靠性。

允许15%的NAND闪存位错误率（BER）

JSSC 2019第6期Data ConvertersSAR ADCDelta-Sigma ADC

A 04-V 13-bit 270-kSs SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

提出一种13位高分辨率两步ADC，采用SAR-ADC和ISDM结合，降低功耗和积分器误差。

0.4V, 270kS/s, 90.38dB SFDR, 73.57dB SNDR, 0.45LSB DNL, 0.75LSB INL, 638nW

JSSC 2019第6期Other

A 13.56 MHz, 94.1% Peak Efﬁciency CMOS Active Rectiﬁer With Adaptive Delay Time Control for

提出一种基于自适应延迟时间控制的CMOS有源整流器，显著降低功耗并提升效率。

峰值效率94.1%（输出功率10.63mW时），静态功耗<230µW，最大输出功率34.1mW（输入AC幅值2.5V）

JSSC 2019第6期Power ManagementEnergy Harvesting

A 14-nA Highly Efficient Triple-Output Thermoelectric Energy Harvesting System B

本文提出了一种基于可重构热电发电机阵列的无电感三输出热电能量收集系统，具有高效能量回收和低静态电流特点。

14-nA quiescent current, 86% efficiency over 0.15–10.8 V input, 38 µW–200 mW output power, 99% peak efficiency

JSSC 2019第6期RF & Wireless

A 1.5–1.9-GHz All-Digital Tri-Phasing Transmitter With an Integrated Multilevel Class-D Power Ampliﬁer Achieving 100-MHz RF Bandwidth

一种采用28nm CMOS工艺的全数字三相位发射机，集成多电平D类功放，无需数字预失真即可实现高线性。

28nm CMOS, 1.5-1.9GHz, 100MHz OFDM, 22.6dBm输出功率, 14.6% PA效率

JSSC 2019第6期Analog CircuitsNeural Network Accelerator

A 230260-GHz Wideband and High-Gain Amplifier in 65-nm CMOS Based on Dual-Peak G

基于双峰最大增益核心的65nm CMOS宽带高增益放大器设计

3-dB带宽30 GHz (227.5–257.2 GHz), 增益12.4 ± 1.5 dB, 峰值PAE 1.6%, 功耗23.8 mW

JSSC 2019第6期RF & Wireless

A 25-Gbs Avalanche Photodetector-Based Burst-Mode Optical Receiver With 224-ns R

28nm CMOS工艺下25Gbps雪崩光电探测器突发模式光接收器，具有高灵敏度和快速重配置能力。

28nm CMOS, 25Gb/s, -16dBm@BER<10^-12, 2.24ns重配置, 1.37pJ/b

JSSC 2019第6期Power Management

A 25-MHz Four-Phase SAW Hysteretic Control DC–DC Converter With 1-Cycle Active

提出一种25MHz四相DC-DC转换器，采用自适应窗口迟滞控制，实现快速瞬态响应和高效率。

0.35µm CMOS, 3.3V输入, 0.3-2.5V可编程输出, 88.1%峰值效率

JSSC 2019第6期RF & WirelessPower Amplifier

A 28-/37-/39-GHz Linear Doherty Power Ampliﬁer in Silicon for 5G Applications

本文提出了一种用于5G应用的28-37-39 GHz硅基线性Doherty功率放大器。

28/37/39 GHz, +16.8/+17.1/+17 dBm Psat, 52% -3-dB S21带宽, 40% -1-dB Psat带宽

JSSC 2019第6期Memory

A 3-D IC for Mitigating Energy of Memory Accessing and Data Movement in Accelerator- Based

提出一种用于异构域特定流架构的三维集成电路，通过分层设计优化内存访问和数据移动能耗。

未明确提及

JSSC 2019第6期MemoryNeural Network Accelerator

A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute

一款采用电荷域混合信号操作的64片24Mb内存计算CNN加速器，提升计算信噪比和可扩展性。

65nm CMOS, HLs/FL能效866/1.25 TOPS/W, 吞吐量18876/43.2 GOPS

JSSC 2019第6期RF & Wireless

A CMOS MedRadio Transceiver With Supply-Modulated Power Saving Technique for an Implantable Brain–Machine

介绍了一种用于植入式脑机接口的CMOS MedRadio收发器，采用事件驱动电源调制技术降低功耗。

180nm CMOS, 1.8V, 1/10kbps, -79/-74dBm灵敏度

JSSC 2019第6期Clocking & PLLs

A CMOS SPAD Line Sensor With Per-Pixel Histogramming TDC for Time-Resolved

一款基于SPAD的线阵传感器，具有像素级直方图TDC，用于时间分辨多光谱成像。

512×16阵列, 51.20ps时间分辨率, 102.1G事件/s(SPC模式)

JSSC 2019第6期Data ConvertersSAR ADCDAC

A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors

提出一种无需校准的12位50MS/s全模拟SAR ADC，采用反馈过零检测技术。

12-bit, 50-MS/s, 0.01 mm²

JSSC 2019第6期RF & WirelessPower Amplifier

A Compact Dual-Band Digital Polar Doherty Power Amplifier Using Parallel-Combining Transformer

一种采用并行组合变压器的紧凑型双频数字极化多尔蒂功率放大器。

55nm CMOS, 1.11 mm² die area, 28.9-dBm peak Pout (LB), 27.0-dBm peak Pout (HB), -21.6-dB EVM

JSSC 2019第6期OtherEnergy Harvesting

A Fully Integrated Split-Electrode SSHC Rectifier for Piezoelectric

提出一种全集成分裂电极SSHC整流器，用于压电能量收集，无需外接电感。

0.18-µm CMOS, 186 µW峰值输出功率

JSSC 2019第6期Clocking & PLLs

A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration

一种低抖动、注入锁定的多频率发生器，可在65nm CMOS工艺中独立生成0.9-1.2GHz的多频信号。

960MHz输出信号的1MHz相位噪声-133.5dBc/Hz，rms抖动375fs，面积0.05mm²，功耗7.7mW

JSSC 2019第6期Data Converters

A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR

提出了一种面向移动I/O应用的低功耗双向链路，采用CMOS缩放技术提升能效。

22nm CMOS, 0.55-0.7V, 1.2-5 Gb/s, 0.6 pJ/b

JSSC 2019第6期RF & WirelessPAM-4

A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for

一款支持数字预失真PAM-4调制的127 GHz毫米波CMOS收发器，用于非接触通信。

20 Gb/s, 1.2V, 79.5 mW, 3.98-pJ/bit

JSSC 2019第6期Other

A Multi-Loop-Controlled AC-Coupling Supply Modulator With a Mode-Switching CMOS

提出一种多环路控制的AC耦合电源调制器，用于低成本LTE应用。

0.5–2.5-V输出, 2.4-V输入, 88.7%效率

JSSC 2019第6期Other

A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over

提出一种采用绝热驱动技术的低功耗互电容触摸读取IC，显著降低功耗并提升抗干扰能力。

180nm CMOS, 17.8mW, 57.0dB SNR@120fps

JSSC 2019第6期Data Converters

A Reference-Free Temperature-Dependency- Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Conﬁgured Sense Ampliﬁers Dong-Hwan Jin, Ji-Wook Kwon, Min-Jae Seo , Mi-Young Kim, Min-Chul Shin, Seok-Joon Kang

提出一种无参考温度补偿相变存储器读取方案，通过重构感放阵列为闪存ADC优化决策阈值。

137×27µm², 305µW@3.3V, <100ns延迟

JSSC 2019第6期Data ConvertersSAR ADC

A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level V oting

本文提出一种低功耗、易扩展的二阶噪声整形SAR ADC，采用无源积分器和三电平表决技术。

40nm CMOS, 1.1V, 8.4MS/s, 143µW, 78.4dB SNDR, 262kHz带宽

JSSC 2019第6期Other

Call for Papers IEEE Asian Solid-State Circuits Conference A-SSCC 2019

IEEE亚洲固态电路会议A-SSCC 2019征稿通知

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JSSC 2019第6期Digital Circuits

Design of an Always-On Deep Neural Network-Based 1- μ W Voice Activity Detector Aided With a Customized Software Model for Analog

设计了一种超低功耗语音活动检测器，采用模拟信号处理和数字深度神经网络分类，功耗仅1μW。

0.18μm CMOS, 1.66×1.52 mm², 1μW, 84.4%/85.4% 语音/非语音命中率

JSSC 2019第6期Other

IEEE JOURNAL OF SOLID-STATE CIRCUITS

IEEE JSSC期刊的会员信息及管理团队介绍

无

JSSC 2019第6期Other

Information

IEEE JSSC期刊投稿指南，涵盖集成电路设计、建模、技术、系统设计、布局和测试等内容。

无

JSSC 2019第6期RF & Wireless

New Associate Editors

IEEE JSSC期刊介绍新编辑团队及其专业背景

无

JSSC 2019第6期RF & Wireless

Reference-Less Time-Division Duplex Transceiver IC for a Renal

首款用于肾去神经术的时分双工收发器IC，实现微创手术并减少并发症。

0.18-μm HV BCDMOS, 2.1 mm², ±0.5°C温度测量精度, 120-V pp RF信号

JSSC 2019第6期Other

Table of contents

多篇JSSC论文摘要，涵盖射频前端、收发器设计、功率放大器等主题。

1.5–1.9GHz, 100MHz RF带宽, 多频段数字极坐标Doherty功放

JSSC 2019第6期RF & WirelessNeural Network Accelerator

Wide-Band RF Front End for SAW-Less Receivers Employing Active Feedback and Far Out-of-Band Blocker

提出一种采用主动反馈和远带阻塞抑制技术的宽频带射频前端，适用于无SAW滤波器接收器。

0.18-µm CMOS, 1.26 mm², 700 MHz–6 GHz, IIP3: -6 to 0.5 dBm, OOB IIP3: -5.3 to 35 dBm

JSSC 2019第7期Power ManagementSAR ADC

A 0.1-nW–1-μW Energy-Efﬁcient All-Dynamic Versatile Capacitance-to-Digital Converter

一种基于全动态架构的低功耗、高能效电容数字转换器，适用于物联网应用。

65nm CMOS, 1 S/s至100 kS/s采样率, 1.23至24.59 pF电容范围, 0.1nW至1µW功耗, 18-59 fJ/conv-step FoM

JSSC 2019第7期Other

A 0410 GHz 47 MHop s Frequency-Hopped TXR Front End With 20 dB In-Band Blocker R

本文提出了一种超快速跳频扩频收发器前端，在RF链路上实现了20 dB的处理增益。

65 nm RF CMOS, 1 V, 47 MHop/s

JSSC 2019第7期RF & Wireless

A 085mm2 51-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz I

16nm FinFET工艺下，集成DCO与DPA的亚千兆赫兹发射机，面积节省50%，效率达51%。

16nm FinFET, 0.3V, 1.8GHz, 51%效率, 11dBm输出, -116dBc/Hz相位噪声

JSSC 2019第7期Analog CircuitsBandgap Reference

A 1-V Bandgap Reference in 7-nm FinFET With a

提出了一种在7nm FinFET工艺中实现的可编程温度系数的1V精密电压参考源。

1V, 最大误差±0.2%, 最小温度系数6ppm/°C, 线调节率0.1%/V, 面积0.078mm²

JSSC 2019第7期Wireline I/O

A 1-pJ/bit 80-Gb/s 2 15 − 1 PRBS Generator With a Modiﬁed Cherry–Hooper

一款低功耗80Gb/s伪随机二进制序列生成器，采用改进Cherry-Hooper输出驱动，性能优异。

130nm SiGe, 1 pJ/bit, 80 Gb/s, 300-mV眼图开度, 0.6-ps rms抖动

JSSC 2019第7期Other

A 135-mW 170TOPS Sparse Video Sequence Inference SoC for

设计了一款用于视频动作分类的稀疏推理SoC，具有高效能

40nm CMOS, 0.9V, 250MHz, 1.70TOPS, 135mW

JSSC 2019第7期Other

A 15-nW per Sensor Inte rference-Immune Readout IC for Capacitive

一款用于电容式触摸传感器的15nW/传感器抗干扰读出IC，采用异步CDC和高效跟踪算法。

38Hz扫描速率下每传感器15nW功耗

JSSC 2019第7期Clocking & PLLsProcessor/CPU

A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SR

一款16纳米工艺的常开DNN处理器，采用自适应时钟和多周期存储体SRAM技术，适用于移动和物联网设备。

16nm, 0.4-1V, 1.36 GHz, 750 µW, 750 GOPS/W dense, 1.81 TOPS/W sparse

JSSC 2019第7期Image SensorsCMOS Image Sensor

A 192128 Time Correlated SPAD Image Sensor in 40-nm CMOS Technology

40nm CMOS工艺下实现的192×128像素SPAD时间分辨单光子计数图像传感器

40nm CMOS, 13%填充因子(微透镜后42%), 18.6k帧/秒, 219ps FWHM IRF, 25Hz中值DCR

JSSC 2019第7期Data ConvertersNeural Network Accelerator

A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC

提出一种新型全时间两步ADC，采用高线性度动态延迟器，实现低功耗高性能。

65nm CMOS, 1 GS/s, 2.3 mW, 44.4 dB SNDR

JSSC 2019第7期OtherNeural Network Accelerator

A 24-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4 4 256-QAM

本文介绍了一种用于4×4 256-QAM的MMSE-NBLDPC迭代检测解码器，采用65nm CMOS工艺，实现了高能效的检测和解码。

65nm CMOS, 1.38Gb/s MMSE检测器, 1.02Gb/s NBLDPC解码器, 19.2pJ/b检测, 20.1pJ/b/iteration解码

JSSC 2019第7期Clocking & PLLsVCODLL

A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference

提出一种低抖动、低功耗的环形振荡器注入锁定时钟倍频器，采用背景校准和数字环路技术。

65nm CMOS, 0.09mm², 2.5-5.75GHz, 335fs rms, 5.3mW

JSSC 2019第7期Clocking & PLLs

A 2.5 ppm/ ◦C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time

一款105MHz弛豫振荡器，采用动态频率误差补偿技术，温度系数低至2.5 ppm/°C。

1.05MHz, 2.5ppm/°C TC, 160ps RMS抖动, 69µW@1V

JSSC 2019第7期RF & Wireless

A CMOS Polar Class-G Switched-Capacitor PA With a Single High-Current Supply, for LTE NB-IoT and eMTC

提出一种仅需单一高电流电源的CMOS极性G类开关电容功率放大器，简化电源管理单元设计。

807 MHz, 27.1 dBm峰值输出功率, 33.3% PAE, 13位分辨率

JSSC 2019第7期Data ConvertersNeural Network AcceleratorBiosignal

A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications

提出一种双环路八通道心电图记录系统，用于无线实时12导联心电图应用，具有快速稳定模式。

112.5-dB CMRR, 113.0-dB PSRR, 1.44-μV rms噪声, 0.3mm²面积, 60μW功耗

JSSC 2019第7期Other

A Fast T&H Overcurrent Detector for a Spinning Hall Current Sensor With Ping-Pong

一种快速TH过流检测器，用于具有乒乓结构的旋转霍尔电流传感器

568 ns总体延迟，250 kHz旋转频率，85 μT残余偏移，136 μT rms输入参考噪声，1.7 MHz带宽

JSSC 2019第7期Power Management

A Fully Integrated Switched-Capacitor-Based AC–DC Converter for a 120 V RMS

一种基于开关电容的全集成ACDC转换器，适用于120 VRMS电源，通过电荷重分配和记忆效应提高效率和操作范围。

15.16 µW输出功率，80.7%峰值效率，9.8mm²活动面积

JSSC 2019第7期RF & WirelessNeural Network Accelerator

A Quantized Analog RF

一种采用量化模拟射频前端、无表面声波的接收器，动态范围可调，性能优越。

65nm CMOS, 0.8V, 1-dB压缩点达10.5dBm, 噪声系数低至1.5dB, 功耗14mW

JSSC 2019第7期Data Converters

A Real-Time 189-GHz Bandwidth 175-kHz Resolution Sparse Spectral Analysis RISC-V

一款采用16nm CMOS工艺的1.89GHz带宽、175kHz分辨率稀疏频谱分析SoC，集成子采样ADC与数字重构后端。

16nm CMOS, 0.7V VDD, 3.78GHz参考时钟, 49.8mW ADC功耗, 133.5mW DSP总功耗

JSSC 2019第7期Clocking & PLLsDAC

A Robust BBPLL-Based 0.18- μm CMOS Resistive Sensor Interface With High Drift Resilience Over a −40 ◦C–175 ◦C

一种基于BBPLL的0.18微米CMOS抗漂移电阻传感器接口，具有高精度和低漂移特性。

0.18-µm CMOS, 15-bit ENOB, 100-ms转换时间, 3.41 mW功耗, 0.23 mm²面积

JSSC 2019第7期MemorySRAM

An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI

提出一种带片上动态可靠性管理的8T SRAM，通过两阶段写操作解决BTI退化问题。

28nm FDSOI, 16-kb SRAM, 3.42%功耗开销, 10%面积开销

JSSC 2019第7期Other

Analysis and Design of Coupled Inductive Bridges for Magnetic

本文提出了一种新型磁传感器，采用交叉耦合电感对改进的交流惠斯通电桥设计，实现了尺寸减半和增益加倍。

770-1450 MHz, 200 μm × 200 μm 有效感应区域

JSSC 2019第7期Other

Analysis and Design of a Foam-Cladded PMF Link With Phase Tuning in 28-nm CMOS

本文设计了一种140GHz泡沫包覆介质波导通信链路，采用新型FSK解调器拓扑，实现了12Gb/s的数据传输。

28nm CMOS, 0.9V, 230mW, 12Gb/s/10Gb/s/7Gb/s

JSSC 2019第7期RF & Wireless

Enhanced Interference Rejection Bluetooth Low-Energy Back-Channel Receiver With LO

提出两种低功耗BLE唤醒接收器，通过跳频增强干扰抑制能力。

灵敏度-57.5dBm/-82.2dBm，功耗150µW/1.2mW

JSSC 2019第7期OtherProcessor/CPU

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing Antonio Pullini , Davide Rossi , Igor Loi

MrWolf是一款面向物联网边缘的并行超低功耗SoC，具有能效比高的特点。

40nm CMOS, 108μW内存保持功耗, 1.6Gbit/s数据传输速率, 850MMAC/s峰值性能

JSSC 2019第8期Clocking & PLLsPLL

A 0.016 mm 2 0.26-μW/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

本文提出了一种新型数字PLL设计，结合RC振荡器和环形振荡器的优势，适用于超低功耗MCU和IoT应用。

65nm CMOS, 50–300 MHz输出频率, 超低功耗

JSSC 2019第8期Digital CircuitsBiosignal

A 1.06-μW Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal

一款用于实时生物特征认证的65nm CMOS智能ECG处理器

65nm CMOS, 1.06 µW @ 0.55V, 1.70%/2.18%/2.48% 等错误率

JSSC 2019第8期Data ConvertersSAR ADC

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC

一款12位1GS/s时间交织SAR ADC，采用模拟HPF辅助校准技术

65.3dB SNDR, >70dB SFDR, 315mW功耗, 0.27mm²面积

JSSC 2019第8期RF & WirelessCDR

A 25-Gbs 21-pJbit Fully Integrated Optical Receiver With a Baud-Rate Clock and D

一款25-Gb/s全集成光接收器，采用波特率时钟恢复技术，实现高灵敏度和高能效。

25-Gb/s, 21-pJ/bit, BER < 10^-12, 1.7-ps rms抖动

JSSC 2019第8期Data ConvertersDAC

A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error Derui Kong , Kevin Rivas-Rivera

本文介绍了一种600MS/s DAC，采用自适应校准技术，实现了87dB SFDR和77dB SNDR。

600MS/s, 87dB SFDR, 77dB SNDR, 265MHz信号带宽

JSSC 2019第8期Power Management

A 763 pW 230 pJ/Conversion Fully Integrated CMOS Temperature-to-Digital Converter With +0.81 ◦C/−0.75 ◦C Inaccuracy

提出一种亚纳瓦级全集成CMOS温度传感器，采用电容充电时间反馈环路实现温度数字化。

65nm CMOS, 0.5V, 763pW, 230pJ/conversion

JSSC 2019第8期RF & Wireless

A Broadband CMOS RF Front End for

比较两种新型RF可编程增益放大器架构在宽带CMOS RF前端中的应用。

28nm CMOS, 50mW功耗, 0.32mm²面积, 增益范围42dB, 0.25dB步进

JSSC 2019第8期RF & Wireless

A Differential Optical Receiver With Monolithic Split-Microring Photodetector

提出一种采用新型谐振分裂微环光电探测器的高灵敏度全差分光接收器，用于高密度片上系统应用。

45nm SOI CMOS, 0.52-A/W responsivity, 5.0 GHz bandwidth, BER < 10−12 at 12 Gb/s, −18.2 dBm OMA sensitivity, 7 mW power consumption

JSSC 2019第8期Clocking & PLLs

A General Theory of Injection Locking and Pulling in Electrical Oscillators—Part I: Time-Synchronous Modeling and Injection

提出一种通用模型，用于分析周期性注入下电气振荡器的锁定和牵引现象。

无具体性能指标

JSSC 2019第8期OtherNeural Network Accelerator

A Low-Noise Chopper Ampliﬁer Designed for Multi-Channel Neural

设计了一种用于多通道神经信号采集的低噪声、低谐波失真斩波放大器。

TSMC 0.18µm CMOS, 1.8V, 3.24µW/通道, THD < -61dB, 输入参考噪声0.65µVrms (0.3–200Hz)

JSSC 2019第8期Image SensorsCMOS Image Sensor

A Sub-100 μm-Range-Resolution Time-of-Flight Range Image Sensor With Three-Tap L

提出一种亚100微米分辨率的时间飞行测距图像传感器，采用三抽头锁定像素和列并行数字延迟锁定环技术。

64 µm rms范围分辨率，430-fs时间分辨率，25-mm范围

JSSC 2019第8期RF & Wireless

A Wireless Multi-Channel Peripheral Nerve Signal Acquisition System-on-Chip

一款高度集成的十通道无线神经信号采集SoC，适用于慢性植入式神经假体设备。

0.18μm CMOS, 1.9μV rms输入噪声, 4.0 NEF, 10-bit分辨率, 17.5 ksps, 4.4 mW总功耗

JSSC 2019第8期Other

An Energy-Efﬁcient Reconﬁgurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications

首款DTLS协议硬件实现，专为物联网设计，能效比软件提升438倍。

65nm CMOS, 0.8V, 16MHz, 44.08 µJ/handshake, 0.89 nJ/byte

JSSC 2019第8期RF & Wireless

An IR-UWB CMOS Transceiver for High-Data-Rate, Low-Power, and Short-Range Communication Geunhaeng Lee , Jungwoon Park , Junyoung Jang

提出一种采用数字化多脉冲位置调制的IR-UWB收发器，实现高数据率、低功耗和短距离通信。

500 Mb/s, 27.7-mW Rx, 7 mW Tx, 1–5 m range

JSSC 2019第8期Clocking & PLLsPLLProcessor/CPU

An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low

提出一种基于指令驱动的自适应时钟管理方案，通过动态相位缩放和编译器辅助设计实现低功耗微处理器。

55-nm CMOS, 20%性能提升, 32%能耗节省

JSSC 2019第8期mm-Wave

High-Efﬁciency SiGe-BiCMOS E-Band Power Ampliﬁers Exploiting Current Clamping in the Common-Base Stage

提出基于SiGe-BiCMOS的高效E波段功率放大器，采用共基极输出级设计，显著提升输出功率和效率。

80 GHz下输出功率18-21.5 dBm，PAE在1dB压缩点达22%

JSSC 2019第8期RF & Wireless

Interference Robust Detector-First Near-Zero Power Wake-Up Receiver

提出一种纳瓦级功耗、高灵敏度且抗干扰的唤醒接收器，适用于事件驱动应用。

151.8MHz频段-76dBm灵敏度，433MHz频段-71dBm灵敏度，7.6nW总功耗（1.0V/0.6V供电）

JSSC 2019第8期Clocking & PLLs

REFERENCES [1] B. Hong and A. Hajimiri, “A genera l theory of injection locking and pulling in electrical oscillators—Part I: Time-synchronous modeling and injection waveform design,” IEEE J. Solid-State Circuits, vol. 54, no. 8, pp. 2109–2121, Aug. 2019. [2] R. Adler, “A study of locking phenomena in oscillators,” Proc. IRE , vol. 34, no. 6, pp. 351–357, Jun. 1946. [3] R. D. Huntoon and A. Weiss, “Synchronization of oscillators,” Proc. IRE, vol. 35, no. 12, pp. 1415–1423, Dec. 1947. [4] H. L. Stover, “Theoretical explan ation for the output spectra of unlocked

该论文研究了振荡器的注入锁定现象及其波形设计。

无具体性能指标

JSSC 2019第8期OtherNeural Network Accelerator

Self-Timed Pulsed Latch for Low-V oltage Operation

提出了一种自定时脉冲锁存器，用于低电压操作，显著减少保持时间。

65nm CMOS, 300mV降低, 77%保持时间减少

JSSC 2019第8期Other

Therefore, a part of the Drain2 current directly ﬂows from the bulk toward the Drain2 due to the wide aperture setting. The internal quantum efﬁciency estimated from the simulation results in Fig. 4 is 60% at 473 nm, in which the signal loss due to the leakage is taken into account. The internal QEs for the other wavelength of 550 and 650 nm are simulated to be 58% and 52%, respectively. C. Distance Calculation and Its Resolution Assuming a Gaussian function for the photocurrent response, the distance calculated by the TOF, (D

该论文研究了基于TOF技术的距离测量方法，分析了光电流响应和距离计算的关系。

内部量子效率在473nm、550nm和650nm波长下分别为60%、58%和52%

JSSC 2019第9期OtherPhased Array

A 034-THz Wideband Wide-Angle 2-D Steering Phased Array in 013- μm SiGe BiCMOS

本文提出了一种0.34-THz宽带广角二维转向相控阵，采用新型毫米波/太赫兹频谱相控阵实现方法。

0.13-μm SiGe BiCMOS, 1.5V, 318-370GHz, 52GHz调谐范围, 128°/53°二维转向角度

JSSC 2019第9期Data ConvertersDelta-Sigma ADCOp-Amp

A 1-V 175- μW 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator

采用65nm CMOS工艺的1V 175μW ΔΣ调制器，实现94.6dB SNDR和25kHz带宽。

65nm CMOS, 1V, 5MS/s, 175μW, 94.6dB SNDR, 25kHz带宽

JSSC 2019第9期RF & Wireless

A 115–135-GHz 8PSK Receiver Using Multi-Phase RF-Correlation-Based Direct-Demodulation Method

一款基于多相射频相关技术的115-135GHz 8PSK直接解调接收器，实现36Gb/s无线传输。

55nm SiGe BiCMOS, 32dB增益, 10.3dB噪声系数, 36Gb/s@30cm, -41.28dBm灵敏度, 200.25mW功耗

JSSC 2019第9期Image SensorsCMOS Image Sensor

A 117-Megapixel CMOS Image Sensor With 15 AD Conversions per Digital CDS Pixel R

提出一种低功耗117兆像素CMOS图像传感器，采用数字相关双采样技术降低能耗。

1232×952像素阵列，2.8µm像素间距，27.3 pJ/pixel，0.064 nJ·e⁻ FoM

JSSC 2019第9期Clocking & PLLsPLL

A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

提出计算锁定技术，实现快速频率和相位锁定的全数字锁相环。

1–2 GHz, 12 TREFCLK (re-lock), 16 TREFCLK (cold-start)

JSSC 2019第9期Clocking & PLLsPLL

A 320-fs RMS Jitter and −75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

基于环形DCO的数字PLL实现低抖动和低参考杂散

65nm CMOS, 2.4GHz, 320fs RMS jitter, -75dBc reference spur, 6.0mW

JSSC 2019第9期RF & Wireless

A 4-GHz Low-Power Multi-User Approximate Zero-IF FM-UWB Transceiver for IoT

一款用于物联网的低功耗4GHz FM-UWB收发器

65nm CMOS, 575µW发射功耗, -11.4dBm输出功率, 100kb/s速率

JSSC 2019第9期Data ConvertersSAR ADC

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS Kyoung-Jun Moon, Dong-Shin Jo , Wan Kim, Michael Choi, Hyung-Jong Ko

本文介绍了一种采用电流模式残差处理技术的流水线-SAR ADC，实现了10位分辨率、500MS/s的转换速率和低功耗。

10位分辨率，500MS/s转换速率，1.0V供电，56.6dB SNDR，21.7fJ/转换步

JSSC 2019第9期OtherPLLPhased Array

A Fully Integrated 384-Element, 16-Tile, W -Band Phased Array With Self-Alignment and Self-Test

介绍了一种基于TowerJazz 0.18µm SiGe BiCMOS工艺的可扩展W波段相控阵系统，具有自对准和自测试功能。

384-element (256TX/128RX), 60 dBm EIRP, 10 Gb/s data rate at 90.7 GHz

JSSC 2019第9期RF & WirelessDLL

A Reconﬁgurable Cross-Connected Wireless- Power Transceiver for Bidirectional Device-to-Device

提出一种可重构交叉连接无线功率收发器，用于高效双向设备间充电。

峰值效率77.2%(0.7W), 最大功率2.74W(62.7%), 最远距离24mm

JSSC 2019第9期RF & Wireless

A Three-Stage 18524-GHz GaN-on-SiC 4 W 40 Efﬁcient MMIC PA

本文介绍了一种三阶段K波段GaN-on-SiC MMIC功率放大器的设计与性能。

150-nm GaN-on-SiC, 4 W, 40% PAE, 18-24 GHz

JSSC 2019第9期Clocking & PLLs

A commonly used approach to lower TS is shown in Fig. 1(b), which aims at increasing the active circuitry’s negative resistance RN by modifying the inverting ampliﬁer’s gm or the capacitors C1 and C2. Reference [7] describes a method in which a minimum load capacitor CL [deﬁned as CL = C0 +C1C2/(C1+C2)] is applied to the oscillator during start-up, and once a stable oscillation is detected, a second capacitor bank is switched in to adjust the frequency and reach the desired steady state . Reference [8] implemented a similar concept to reduce T

本文探讨了降低TS的常用方法，通过修改反相放大器的gm或电容C1、C2来增加RN。

无

JSSC 2019第9期Clocking & PLLsVCO

Analysis and Correction of Noise Injection Due to Parallel-Output-Misalignment P

本文提出了一种并联输出失准校正电路，有效消除了环形时间数字转换器中的相位噪声。

40nm CMOS, 3或0.8 ps时间分辨率, 12 ns时间长度检测范围

JSSC 2019第9期Other

Analysis and Design o f a Multi-Step Bias-Flip Rectiﬁer for Piezoelectric

多级偏置翻转整流器提升压电能量提取效率

130nm CMOS, 2µW功耗, 89.5%电压翻转效率, 47µH电感

JSSC 2019第9期Wireline I/O

Analysis and Design of Wideband I/Q CMOS 100–200 Gb/s Modulators Hasan Al-Rubaye and Gabriel M. Rebeiz

本文介绍了一种宽带I/Q CMOS调制器的分析与设计，适用于下一代无线回程链路。

60 dB动态范围，1-GHz带宽，OP1dB ∼−10 dBm，200 Gb/s 16-QAM

JSSC 2019第9期Other

Broadband 240-GHz Radar f or Non-Destructive Testing of Composite Materials Thomas Merkle , Dominik Meier, Sandrine Wagner, Axel Tessmann , Michael Kuri

介绍了一种240 GHz宽带频率调制连续波雷达，用于复合材料的无损检测。

输出功率8 dBm（芯片级），6 dBm（模块级），接收路径转换增益10 dB，噪声系数7 dB

JSSC 2019第9期RF & WirelessEnergy HarvestingNeural Network Accelerator

Design of Sub-Gigahertz Reconﬁgurable RF Energy Harvester From −22 to 4 dBm With 99.8% Peak MPPT Power Efﬁciency

设计了一种可重构的亚千兆赫兹射频能量收集器，工作范围从-22到4 dBm，具有高效率和自我启动功能。

-18.1-dBm sensitivity for 1-MΩ loading, 36% peak efficiency at 1 dBm, MPPT accuracy over 87%

JSSC 2019第9期Data ConvertersFlash ADC

Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM

设计了一款55nm SiGe BiCMOS工艺的5位时间交错闪存ADC，支持64-Gbd 16-QAM信号处理。

128 GS/s, 5-bit, 1.25 W, 1.1 mm × 1.9 mm

JSSC 2019第9期RF & WirelessPhased Array

Gabriel M Rebeiz S86M88SM93F97

Gabriel M Rebeiz教授团队在毫米波和太赫兹频段的射频集成电路、相控阵和RF MEMS技术方面取得多项突破。

6-110GHz多频段覆盖，8/16单元相控阵，85-105GHz无源成像

JSSC 2019第9期Other

Introduction to the Special Section on the 2018 IEEE BCICTS Conference

2018 IEEE BCICTS会议精选论文扩展版，涵盖SiGe和III-V/CMOS IC技术的最新研究。

45-nm silicon on insulator

JSSC 2019第9期RF & Wireless

RF Filter Synthesis Based on Passively Coupled N-Path Resonators

提出基于被动耦合N路径谐振器的射频带通滤波器合成方法。

0.8–1.1-GHz tunable bandpass frequency

JSSC 2019第9期Clocking & PLLs

Reconﬁgurable Clock Networks for Wide V oltage Scaling

提出可重构时钟网络，通过动态调整中继器层级数，在宽电压范围内降低时钟偏差。

40nm CMOS, 3.3×时钟偏差降低, 110mV Vmin降低, 31%最小能耗降低, 1.8%面积开销

JSSC 2019第9期MemorySRAMEmerging Memory

Self-Convergent Trimming SRAM True Random Number Generation With In-Cell Storage Po-Shao Yeh, Chih-An Yang , Yi-Hong Chang, Yue-Der Chih, Chrong-Jung Lin, and Ya-Chin King

首次实现基于4T-2R自对准氮化物SRAM单元的真随机数生成器，通过自收敛修调机制减少工艺变异影响。

未明确提及（需补充具体参数如CMOS工艺/电压/速度）

JSSC 2019第9期RF & Wireless

Single-Chip 3072-Element-Channel Transceiver 128-Subarray-Channel 2-D Array IC W

单芯片3072通道收发器与128子阵列通道2D阵列IC，用于超声心动图成像。

3072-ECh transceivers, 128-SCh, 0.18-µm HV-SOI

JSSC 2019第9期Clocking & PLLsCrystal Oscillator

Study and Design of a Fast Start-Up Crystal Oscillator Using Precise

本文提出两种技术减少皮尔斯晶体振荡器的启动时间和能量，通过精确注入和负电阻提升实现快速启动。

18 µs启动时间, 114.5 nJ启动能量, 180 µW稳态功耗, -135 dBc/Hz相位噪声

JSSC 2019第9期Clocking & PLLs

Table I illustrates the comparison of the published TDC works. VI. C ONCLUSION The proposed CRV TDC has been implemented to eliminate (not minimize) the intrinsic computing error due to the POM effect in the ring-type TDC. The POM error correction imple- mentation maintains the practi cal, effective time resolution as good as the quantitative time resolution (3 ps for 32-stage version and 0.8 ps for 128-stage version). The detectable range depends on the bit number of the loop counter, which

提出一种消除环形TDC中POM误差的方法，保持高时间分辨率并简化电路结构。

3 ps（32级版本），0.8 ps（128级版本）

JSSC 2019第10期RF & WirelessEqualizer

A2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Inﬁnite-Range Timing Recovery Seuk Son , Student Member , IEEE,S i g a n gR y u , Student Member , IEEE, Hwanseok Y eo, Member , IEEE

提出一种结合自适应均衡和时序恢复的盲过采样FSE接收器，支持准同步时钟。

28nm CMOS, 3.5 pJ/bit, 0.10 mm², 9 Gb/s, 22-dB信道损耗补偿, 100ppm频率偏移

JSSC 2019第10期RF & WirelessPAM-4Neural Network Accelerator

A 0.25–27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and

提出一种支持PAM4/NRZ的多模收发器，具有自适应功耗CDR和抖动分析功能

28nm CMOS, 0.25-27Gb/s, 3.8pJ/bit (TX), 6.2pJ/bit (RX)

JSSC 2019第10期Data ConvertersSAR ADCNeural Network Accelerator

A 06 V 163 fJc-s Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-C

提出一种低功耗侦探开环动态系统缓冲器，与SAR ADC协同设计，适用于零电容触摸显示驱动集成系统。

0.6V, 400-kS/s, 10-b, 334 nW, 55.96 dB SNDR, 163 fJ/c-s FoM

JSSC 2019第10期Clocking & PLLsCDR

A 10-Gb/s, 0.03-mm 2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

提出一种带路径失配跟踪环路的10Gb/s半速率全数字注入锁定时钟数据恢复电路

28nm CMOS, 0.9V, 10Gb/s, 12.8mW, 0.03mm²

JSSC 2019第10期Data ConvertersDAC

A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion

一款10位1026通道列驱动IC，采用部分分段线性DAC，提升超高清液晶显示色彩深度。

10-bit分辨率, 1026通道, 最大输出偏差16mV, 18.14mm×1.2mm芯片尺寸, 5.6μs建立时间

JSSC 2019第10期Digital CircuitsBiosignal

A 12.6 mW, 573-2901 kS/s Reconﬁgurable Processor for Reconstruction of Compressively Sensed Physiological Signals Y u-Zhe Wang, Y ao-Pin Wang, Yi-Chung Wu , Student Member , IEEE, and Chia-Hsiang Y ang , Senior Member , IEEE

基于ADMM算法的可重构处理器，用于压缩感知生理信号重建，功耗低至12.6mW。

40nm CMOS, 0.60V, 573-2901 kSamples/s, 12.6mW

JSSC 2019第10期Other

A 28-nm 320-Kb TCAM Macro Using Split- Controlled Single-Load 14T Cell and Triple-Margin V oltage Sense Ampliﬁer Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Y ang, Yi-Ju Chen

28纳米工艺下采用新型14T单元和三重容差电压感测放大器的低功耗高速TCAM设计

28nm CMOS, 710ps搜索延迟, 0.422fJ/bit/搜索能耗

JSSC 2019第10期Power ManagementNeural Network Accelerator

A 2.92-μW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18- μmC M O S Sujin Park, Student Member , IEEE, Geon-Hwi Lee

一种低功耗电容数字转换器，支持气压、湿度和加速度传感器。

0.18μm CMOS, 1.1V, 292μW, 864aF分辨率

JSSC 2019第10期Clocking & PLLsVCO

A 37545 GHz Superharmonic-Coupled QVCO With Tunable Phase Accuracy in 28 nm CMOS

提出一种新型毫米波超谐耦合QVCO，具有高相位精度和零电压余量。

40 GHz, -94.32 dBc/Hz @1MHz, 0.18°相位误差, 8.4 mW功耗, 18.4%调谐范围

JSSC 2019第10期Clocking & PLLsVCO

A 6800-μm2 Resistor-Based Temperature Sensor With ±0.35 ◦C( 3σ) Inaccuracy in 180-nm CMOS

一种基于电阻的紧凑型温度传感器，在180nm CMOS工艺中实现，面积仅6800μm²，精度±0.35°C。

±0.35°C (3σ)精度，0.12°C (1σ)分辨率，2.8kSa/s采样率

JSSC 2019第10期Data ConvertersSAR ADCOp-Amp

A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps

一种无需校准的13位10MS/s全模拟SAR ADC，采用连续时间前馈级联运放和自触发放大再生操作。

40nm CMOS, 13-bit, 10-MS/s

JSSC 2019第10期Data ConvertersDelta-Sigma ADCDAC

A Continuous-Time Delta-Sigma Modulator Using a Modiﬁed Instrumentation Ampliﬁer and Current Reuse DAC for

提出一种改进型仪表放大器作为积分器的连续时间ΔΣ调制器，用于神经记录前端。

180nm CMOS, 90dB动态范围, 0.005% THD, 90dB CMRR, 23μW/通道

JSSC 2019第10期Data Converters

A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface Hyuntak Jeon , Student Member , IEEE, Jun-Suk Bang, Y oontae Jung, Student Member , IEEE, Injun Choi, Student Member , IEEE

一种采用退化R-DAC的高动态范围DC耦合时域神经记录IC，用于同时处理神经信号和刺激伪影。

81.3-dB SNDR, 200-Hz带宽, 200-mVpp输入范围, 3.9µW/通道

JSSC 2019第10期Other

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

本文展示了一种基于RISC-V的信号分析SoC，采用16nm FinFET工艺，集成矢量扩展处理器和信号处理加速器。

16nm FinFET, 410 MHz, 750 mV, 600 mW

JSSC 2019第10期Other

A Physically Unclonable Function Using Soft Oxide Breakdown Featuring 0 Native B

基于MOSFET软栅氧化击穿随机性的物理不可克隆函数，具有自限机制和差分读出方案。

40nm CMOS, 0.9V, 40Mb/s, 51.8fJ/bit, 0%原生误码率(1V)

JSSC 2019第10期OtherNeural Network Accelerator

A Single-Inductor Triple-Source Quad-Mode Energy-Harvesting Interface With Automatic Source Selection and Reversely Polarized

提出一种单电感三源四模式能量收集接口，提升低输入电压下的转换效率和输出功率范围。

0.18-µm CMOS, 1.2V, 82.1% peak conversion efficiency

JSSC 2019第10期Digital CircuitsEnergy HarvestingNeural Network Accelerator

An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators Yo s u k e To y a m a, Member , IEEE, Kentaro Y oshioka , Member , IEEE

提出一种低功耗8位相位域MAC电路，用于物联网边缘设备的深度学习加速器。

12.4 TOPS/W

JSSC 2019第10期MemoryNeural Network Accelerator

An Energy-Efﬁcient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm Luke R. Everson , Student Member , IEEE, Muqing Liu , Student Member , IEEE

提出一种基于时间域的神经网络加速器，采用动态阈值误差校正技术，实现高效能计算。

104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC

JSSC 2019第10期Clocking & PLLsVCOCDR

An Inductorless 20-Gbs CDR

一种无电感20Gbps时钟数据恢复电路，具有高抖动容限

45nm CMOS, 抖动容限2 UI@5MHz, 恢复时钟抖动459fs

JSSC 2019第10期Power Management

An Integrated DC–DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast

提出一种基于VCO的15相SC DC-DC转换器，采用分段频率调制和多相协同技术提升瞬态响应。

1V输出/2.4V输入, 138mA负载电流, 峰值效率82.8%, 瞬态恢复25/29ns

JSSC 2019第10期RF & WirelessEnergy Harvesting

Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors Pengcheng Xu , Student Member , IEEE

设计了一种用于SWIPT物联网智能传感器的2.45GHz射频能量收集系统

灵敏度-17.1dBm, 峰值能量收集效率48.3%

JSSC 2019第10期Other

Assuming that the transitions of the up/down signal are random with respect to the CCO phase, which is the case if the CCO frequency FCCO is asynchronous with respect to the demodulating frequency FWB, and/or if FCCO is dithered by thermal noise, the counter’s rounding error will have a uniform distribution. With this assumption, the total in-band phase noise (in radians) is given by [20] σP =

本文分析了异步频率下的相位噪声，并提出了优化离散化噪声的方法。

FCCO,pp=600MHz, FWB=3MHz, 分辨率=0.12°C (rms)

JSSC 2019第10期RF & Wireless

BodyWire: A 6.3-pJ/b 30-Mb/s −30-dB SIR-Tolerant Broadband Interference-Robust Human Body Communication Transceiver Using Time Domain Interference Rejection Shovan Maity , Student Member , IEEE, Baibhab Chatterjee , Student Member , IEEE

BodyWire提出了一种宽带干扰鲁棒的人体通信技术，通过电容终端和电压模式通信实现高效能数据传输。

6.3-pJ/bit, 30 Mb/s, -30-dB SIR tolerance

JSSC 2019第10期Digital CircuitsNeural Network Accelerator

Combining(22) and (23), the RFEH MN power extraction efﬁciency PEE MN can be expressed as PEEMN = Pin/Pincident = 4Rant × real(Zin) (Zin + Rant)2 . (24) From (12) and (13), we can also get directly the relationship between |S11| and PEEMN,w h i c hi sP E EMN = 1−| S11|2 (here, |S11| is in linear units) as illustrated in Fig. 21. As expressed in (11)–(14), once the MN impedance ZMN and rectiﬁer equivalent input impedance Zrec are speciﬁed

该论文提出了一种灵活的RFEH建模方法，用于分析功率提取效率与阻抗匹配网络的关系。

功率提取效率（PEE）和阻抗匹配网络（MN）的性能

JSSC 2019第10期Clocking & PLLsEqualizer

DDJ-Adaptive SAR TDC-Based Timing Recovery for

一种低延迟低功耗的双模NRZ和PAM-4时序恢复电路，直接自适应均衡DDJ。

65nm CMOS, 10-Gb/s NRZ, 20-Gb/s PAM-4, 23 mW, >20 MHz跟踪带宽

JSSC 2019第10期Data Converters

EDAC_RST is approximately twice as large as EConv, because the CDAC skipping algorithm only decreases the conversion energy. In addition, EDAC_RST is still limited by the split- monotonic switching method. In this work, the energy curve of E DAC_RST can be approximated by a ﬁrst-order polynomial equation EDAC_RST = (−16X+276.36)·Cu V 2 ref. (5) The difference /Delta1EDAC_RST of EDAC_RST from the side code

本文提出了一种用于补偿电荷损失的简单电源复位电路。

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JSSC 2019第10期Data Converters

Fourier transform. Pipeline registers favor the direct-form FFT slightly, though the critical path through this circuit is still through log 2(n) butterﬂies, so one pipeline register per stage (a pipeline depth of log 2(n)) is recommended. Bitwidths grow immediately to the estimated output bitwidth assuming one bit growth per stage. This growth is split between the biplex and direct FFT stages, so bitwidth growth happens twice. If the output has more or fewer bits than normal growth would imply, the result is automatically truncated or sign- extended as needed. This archit ecture reuses signiﬁcantly from

该论文探讨了傅里叶变换流水线寄存器的优化设计及其在混合信号模块集成中的应用。

1.2-GHz clock, 8-bit words, deserialized by a factor of 4

JSSC 2019第10期Other

If the voltage drop across Req is considerably smaller than the inductor voltage ( VL) because of the low inductor current, IL,TON can be simpliﬁed as follows: IL,TON (t) ≈ VIN − VSTO L t. (4) The peak inductor current IL,PEAK is computed as IL,PEAK = VIN − VSTO L TON . (5) IL,TOFF can be expressed as follows based on (5): IL,TOFF (t) = VIN − VSTO

分析电感电流和功率转换效率的简化模型及损耗优化方法。

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JSSC 2019第10期Power ManagementBoost ConverterCharge Pump

Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-V oltage Ring Oscillator Soumya Bose , Student Member , IEEE

提出一种片上冷启动技术，实现57mV输入电压下快速启动升压转换器。

57 mV, 135 ms, 90 nJ

JSSC 2019第10期Other

Introduction to the Special Section on the 2018 Asian Solid-State Circuits Conference (A-SSCC)

2018年亚洲固态电路会议（A-SSCC）精选论文集，涵盖模拟电路、数据转换器、新兴技术等领域。

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JSSC 2019第10期Other

Moreover, TMV also has the disadvantage of introducing more latency to the system. The dark-bit masking scheme detects and marks the position of the unstable PUF bits and then discards these bits further in the application. As reported in [3], by masking out the unstable bits, the readout of remaining PUF bits has an ideal BER of 0%. Although such an outcome is desired, it necessitates more testing time and/or additional circuitry to detect the unstable bits. This can introduce a higher cost and may add more vulnerability to side-channel attacks. For example

该论文讨论了PUF技术中不稳定位的处理及其对系统延迟和成本的影响。

理想BER 0%

JSSC 2019第10期Data ConvertersSAR ADC

REFERENCES 1 G-H Chen The application and market of TDDI Sitronix Technol Corp T

该论文讨论了TDDI技术的应用和市场，以及相关的电路设计和优化技术。

0.8V 10b 80kS/s SAR ADC, 16-bit 16MS/s SAR ADC, 0.6V 1.63fJ/c.-s

JSSC 2019第10期Other

Rui P Martins M88SM99F08 was born

本文介绍了Rui P Martins教授的学术生涯及其在电子工程和计算机领域的贡献。

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JSSC 2019第10期Other

Steven Stevo Bailey M11 was born in

论文介绍了三位作者的教育背景、研究经历及兴趣领域。

无关键性能指标

JSSC 2019第10期Power ManagementNeural Network Accelerator

VI. C ONCLUSION This paper proposed two load transient enhancement control techniques: segmented frequency modulator (SFM) and MCW to reduce the recovery time during heavy-to-light and light-to- heavy load transients. We veriﬁed these two methods through a proof-of-concept converter prototype implemented in 65-nm CMOS. The 15-phase interleaved converter implementation supports output voltages of 1 V from a 2.4-V input supply attaining 82.8% peak efﬁciency at an output power density of 240 mW/mm

提出两种负载瞬态增强控制技术以减少负载变化时的恢复时间。

1V输出，2.4V输入，82.8%峰值效率，240mW/mm²功率密度，5.1mA/ns和4.38mA/ns恢复速度

JSSC 2019第11期Power ManagementPLLDLL

A 1.6-to-3.0-GHz Fractional- N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power Alessio Santiccioli , Student Member , IEEE, Mario Mercandelli , Student Member , IEEE

提出一种采用DTC范围缩减技术的16至30GHz分数N MDLL，优化了抖动与功耗的平衡。

65nm CMOS, 1.6-to-3.0GHz, 397fs rms jitter, 2.5mW, -244dB FoM

JSSC 2019第11期Data ConvertersDelta-Sigma ADC

A 22-bit Read-Out IC With 7-ppm INL and Sub-100-μHz 1/ f Corner for DC Measurement Systems Jaehoon Jun , Student Member , IEEE, Soungchul Park, Student Member , IEEE, Junho Kang, Student Member , IEEE

一款22位读出IC，采用电容耦合仪表放大器和增量Δ-Σ ADC，实现7ppm INL和40μHz 1/f噪声拐角。

21.9位有效分辨率，7ppm INL，40μHz 1/f拐角，142μA@3V，18μA@1.5V

JSSC 2019第11期Data ConvertersDAC

A 31-μW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS Peng Chen , Student Member , IEEE, Feifei Zhang, Student Member , IEEE, Zhirui Zong , Student Member , IEEE, Suoping Hu, Student Member , IEEE

提出一种高效低功耗的电容阵列数字时间转换器，采用恒斜率放电技术。

1V电源, 40MHz时钟, 31μW功耗, 148fs分辨率, 9位范围

JSSC 2019第11期MemoryProcessor/CPU

A 4714- µW 200-MHz MOSMTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-

一种低功耗高性能的非易失性微控制器单元，采用STT-MRAM技术。

4714-µW, 200-MHz

JSSC 2019第11期Analog Circuits

A 512-Pixel, 51-kHz-Frame-Rate, Dual-Shank, Lens-Less, Filter-Less Si ngle-Photon Avalanche Diode CMOS Neural Imaging Probe Jaebin Choi , Student Member , IEEE, Adriaan J. Taal, Student Member , IEEE, Eric H. Pollmann, Student Member , IEEE

提出一种植入式单光子成像器，集成于单芯片CMOS，具有512像素和51kHz帧率。

512像素, 51kHz帧率, 3.4mm×600µm×400µm成像范围

JSSC 2019第11期OtherNeural Network Accelerator

A Bio-Impedance Readout IC With Digital- Assisted Baseline Cancellation for Two-

提出一种支持双电极生物阻抗测量的读取IC，采用数字辅助基线抵消技术提升动态范围和噪声性能。

55nm CMOS, 1 kHz-1 MHz, 24 kΩ最大输入范围, 2 mΩRMS最佳分辨率

JSSC 2019第11期Image Sensors

A CMOS Electrochemical Biochip With 32 × 32 Three-Electrode V oltammetry Pixels

一款集成32×32三电极伏安法像素的CMOS电化学生物芯片，用于高性能分子检测。

280 fA rms输入参考噪声（0.1-20 Hz带宽），93 dB动态范围

JSSC 2019第11期Image SensorsCMOS Image Sensor

A Data-Compressive 1.5/2.75-bit Log-Gradient QVGA Image Sensor With Multi-Scale Readout for Always-On Object Detection Christopher Young , Student Member , IEEE

一种面向低功耗物体检测的QVGA图像传感器，采用对数梯度压缩技术，显著降低数据量和能耗。

0.13µm CIS工艺, 4-T 5µm像素, 99pJ/像素

JSSC 2019第11期Other

A Modular, Direct Time-of-Flight Depth Sensor in 45/65-nm 3-D-Stacked CMOS Technology

介绍了一种模块化直接飞行时间深度传感器，采用3D堆叠CMOS技术，具有高精度和远距离测量能力。

低分辨率模式：300米最大范围，80厘米精度；高分辨率模式：150米最大范围，7厘米精度；28dB干扰抑制

JSSC 2019第11期Wireline I/OPAM-4Neural Network Accelerator

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/ λ PAM-4

一款16nm FinFET CMOS工艺的线性TIA，支持100Gbs PAM-4光链路，具有高带宽、低噪声和低功耗特性。

16nm FinFET CMOS, 60.8mW功耗, 27GHz带宽, 16.7pA/√Hz输入噪声密度

JSSC 2019第11期Image Sensors

A Reconﬁgurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LI

一款用于闪光激光雷达的256×256 SPAD传感器，采用3D堆叠工艺，具有像素内直方图功能。

256×256分辨率，36.72µm像素间距，51%填充因子，31.4 Mb/s数据率，100 mW功耗

JSSC 2019第11期OtherPhased ArrayOptical I/O

A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics CMOS 3D-I

通过硅光子与CMOS的3D集成实现单芯片光学相控阵，用于固态光束控制。

125个元件，0.5mm×0.5mm孔径，20mW/元件平均功耗

JSSC 2019第11期RF & Wireless

A Sub-10-pJ/bit 5-Mb/s Magnetic Human Body Communication Transceiver Jiwoong Park , Student Member , IEEE, and Patrick P . Mercier , Senior Member , IEEE

提出一种超低功耗磁人体通信收发器，实现5Mb/s数据传输，能耗低于10pJ/bit。

40MHz载波频率，Q值~50，发射器18.56µW，接收器6.3µW，7.15pJ/bit，4.7pJ/bit

JSSC 2019第11期Medical & BioNeural Interface

A Sub-mm 3 Ultrasonic Free-Floating Implant for Multi-Mote Neural Recording Mohammad Meraj Ghanbari , Student Member , IEEE,D a v i dK .P i e c h, Student Member , IEEE, Konlin Shen, Student Member , IEEE, Sina Faraji Alamouti, Student Member , IEEE, Cem Y alcin, Student Member , IEEE, Benjamin C. Johnson, Member , IEEE

一种0.8mm³的无线超声供能自由浮动神经记录植入物，实现多节点同步记录

5.3µVrms噪声(5kHz带宽), 37.7µW功耗, 7kS/s@50mm深度

JSSC 2019第11期Clocking & PLLs

A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power

提出一种采用比例参考和子时钟门控技术的亚纳瓦级弛豫振荡器，实现超低功耗物联网传感器节点时钟源。

0.68 nW/kHz能效比，1.2MHz频率，0.005mm²面积，0.7%/V电源稳定性，100ppm/°C温度稳定性

JSSC 2019第11期Digital Circuits

A Time-Domain Computing Accelerated Image Recognition Processor With Efﬁcient Time Encoding and Non-Linear Logic Operation Zhengyu Chen , Student Member , IEEE,a n dJ i eG u , Member , IEEE

提出新型时域计算技术加速图像识别处理器，实现高效能低功耗

55nm, 72-fps/core (1.33 GHz), 42%面积与功耗节省

JSSC 2019第11期Power ManagementBoost ConverterNeural Network Accelerator

Algebraic Series-Parallel-Based Switched-Capacitor DC–DC Boost Converter With Wide Input V oltage Range and Enhanced

提出一种基于代数串并联的开关电容升压转换器，具有灵活的电压转换比和高效率。

峰值效率80%，最大负载功率20.4mW，功率密度22.7mW/mm²

JSSC 2019第11期Other

An Acoustic Signal Processing Chip With 142-nW V oice Activity Detection Using M

本文提出了一种基于混频器架构和超低功耗神经网络的语音活动检测芯片，显著降低了功耗。

142-nW 功耗，91.5%/90% 语音/非语音检测率，10-dB SNR

JSSC 2019第11期Power ManagementPLL

An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor Xun Sun , Student Member , IEEE, Fahim ur Rahman , Student Member , IEEE, V enkata

提出UniCaP架构，通过统一时钟和电源控制减少82%的Vdd冗余，支持动态电压频率调整。

82%平均Vdd冗余减少，0.6–1.0-V电压范围

JSSC 2019第11期RF & WirelessDAC

Analysis and Design of High-Order QAM Direct-Modulation Transmitter for High-Speed Point-to-Point mm-Wave Wireless Links Huan Wang , Student Member , IEEE, Hossein Mohammadnezhad , Student Member , IEEE

提出一种新型高速无线发射机架构，通过叠加多路QPSK信号实现高阶QAM调制，避免使用高速DAC。

115GHz载频, 20Gb/s, EVM -15.8dB, +1dBm输出功率, 520mW功耗

JSSC 2019第11期Other

Carlo Samori M98SM08F17 was born

Carlo Samori 和 Salvatore Levantino 的学术背景与研究贡献概述

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JSSC 2019第11期Other

Design and Characterization of a 28-nm Bulk-CMOS Cryogenic Quantum Cont roller D

28纳米体硅CMOS低温量子控制器设计，用于超导量子比特控制。

28nm CMOS, 总功耗<2mW, 数字数据流<500Mb/s

JSSC 2019第11期MemoryCMOS Image Sensor

Dual-Tap Computational Photography Image Sensor With Per-Pixel Pipelined Digital Memory for Intra-Frame Coded Multi-Exposure

提出一种用于计算成像的双抽头编码曝光像素图像传感器，支持每像素流水线数字处理。

280H×176V阵列，11.2µm像素尺寸

JSSC 2019第11期Data ConvertersSAR ADCCMOS Image Sensor

Energy-Efﬁcient Motion-Triggered IoT CMOS Image Sensor With Capacitor Array-Assisted Charge-Injection SAR ADC Kyojin

提出一种低功耗运动触发CMOS图像传感器，适用于物联网应用。

10b ADC, 226 µVrms噪声, 63.6 pJ/frame/pixel, 14.4 µVrms·nJ FoM

JSSC 2019第11期Clocking & PLLsCrystal Oscillator

Fast & Energy Efﬁcient Start-Up of Crystal Oscillators by Self-Timed Energy Injection Joeri B. Lechevallier , Student Member , IEEE, Ronan A. R. van

提出一种自定时能量注入技术，快速启动晶体振荡器，显著降低能耗。

6 µs启动时间，3.7 nJ能耗

JSSC 2019第11期RF & WirelessClock Generation

Hans Herdian S18 was born in Bekasi

本文介绍了三位研究者的学术背景及研究方向，涉及高性能频率合成器、混合信号电路、时钟生成与恢复等领域。

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JSSC 2019第11期Image SensorsCMOS Image Sensor

Hui Feng Ke is currently pursuing the ﬁve-year B.Sc. degree in electrical and computer engineer- ing with the University of Toronto, Toronto, ON, Canada. From 2018 to 2019, he was a Design and Veri- ﬁcation Intern with AMD, Markham, ON, Canada. His research interests include CMOS image sensors, image processing, and digital system design.

本文介绍了 Hui Feng Ke、Harel Haim 和 Manuel Moreno-García 的研究背景与兴趣。

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JSSC 2019第11期Other

Introduction to the Special Section on the 2019 IEEE International Solid-State C

IEEE JSSC期刊2019年特刊介绍，涵盖图像传感器、医疗电子等领域的最新研究进展。

1.7 nJ/frame

JSSC 2019第11期MemoryDRAM

PEDRAM MOHSENI , Guest Editor Department of Electrical, Computer, and Systems Engineering Case Western Reserve University Cleveland, OH 44106 USA pedram.mohseni@case.edu

Pedram Mohseni教授在神经工程和无线传感系统领域的研究贡献。

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JSSC 2019第11期Other

Prior work has addressed some challenges in ﬁne-grained IVR design for digital S

本文提出了一种适用于多种稳压器的UniCaP框架，解决了相位锁定和自适应时钟问题。

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JSSC 2019第11期RF & WirelessOptical I/O

RADAR and wireless communications, and it is also possible to realize the same concept in the optical domain. This technique has gained a lot of attention alongside advancements in silicon photonics technology, w hich enables inexpensive fabrication of a large number of optical components [10], [11]. OPA technology has progressed tremendously within a rela- tively short period of time, and multiple large-scale implemen- tations with ∼1000 elements recently reported [12]–[16]. However, it is still challenging to realize a low-cost OPA that can bring the proliferatio n of chip-scale optical beam

硅光子技术进步推动低成本光学相控阵（OPA）发展，但仍面临芯片集成挑战。

500–1000元件数量

JSSC 2019第11期Data ConvertersSAR ADCDAC

SAR ADCs over single-slope ADCs. But with a coarse/ﬁne structure, the required number o f ci-cell activations to create 2N DAC levels scales down relative to M. This scaling enables the low-energy operation of a c-ciDAC. For our implemen- tation, M of 8 was selected, and ci -cell activations were effectively reduced by 4.3 ×, including dual correlated double sampling (dual-CDS), which slightly hampers the reduction. 3) Calibration Mechanisms: Including multiple ci-paths levies calibration overhead on the c-ciDAC. Although leverag- ing reuse in the ci-cells redu ces the impact of mismatch among

论文提出了一种采用粗-细结构的SAR ADC，通过校准机制优化DAC增益误差和DNL问题。

8位M值，ci-cell激活减少4.3倍

JSSC 2019第11期Other

ULPAC A Miniaturized Ultralow-Power

本文介绍了一种芯片级超低功耗原子钟（ULPAC），采用新型悬浮量子封装架构和全集成频率探测锁定环路，实现紧凑封装和超低功耗。

频率稳定性2.2×10^-12（平均时间10^5秒），功耗59.9mW

JSSC 2019第12期Data ConvertersSAR ADCTDC

A 06-V 13-bit 20-MSs Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-E

一种0.6V供电、13位20MS/s的TDC辅助SAR ADC，具有PVT鲁棒性和速度增强技术。

65nm CMOS, 0.6V, 20MS/s, 71.0dB SNDR, 89.5dB SFDR

JSSC 2019第12期Data ConvertersSAR ADCNeural Network Accelerator

A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Ampliﬁer Ahmed ElShater , Student Member , IEEE, Praveen Kumar V enkatachala, Student Member , IEEE, Calvin Y oji Lee, Student Member , IEEE

本文展示了一种采用双死区环形放大器的16位15-MS/s两步SAR ADC，实现91-dB SNDR和179.8 dB Schreier品质因数。

16位分辨率，15 MS/s采样率，91-dB SNDR，179.8 dB Schreier品质因数

JSSC 2019第12期OtherBandgap Reference

A 192-pW V oltage Reference Generating BandgapVth With Process and Temperature D

提出一种利用工艺偏差维度效应补偿阈值电压变化的192皮瓦超低功耗电压基准电路

0.18µm CMOS, 192pW, 0.0045mm², 0.53%工艺偏差, 33ppm/°C温度系数

JSSC 2019第12期Clocking & PLLsPLL

A 265-μW Fractional- N Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

提出一种265μW超低功耗分数N数字锁相环，实现无缝切换子采样操作。

265μW功耗，2.8ps积分抖动，-52dBc分数杂散

JSSC 2019第12期Clocking & PLLsPLLClock Generation

A 30-GHz Digital Sub-Sampling Fractional- N PLL With − 238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS Luca Bertulessi , Student Member , IEEE, Saleh Karman, Dmytro Cherniak, Student Member , IEEE

30GHz数字子采样分数N锁相环，实现低抖动功耗比

30.4-34.2GHz, 191Hz分辨率, 180/197.6fs抖动, 35mW功耗, -238.6dB FoM

JSSC 2019第12期RF & Wireless

A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO

一款支持422Gbps、43pJ/b能效的60GHz数字发射器，采用12b/符号极化MIMO技术。

28nm CMOS, 0.9V, 42Gb/s, 4.3pJ/b

JSSC 2019第12期Other

A 52% Peak Efﬁciency >1-W Isolated Power Transfer System Using Fully Integrated Transformer With Magnetic Core Y ue Zhuo ,S h a o y uM a , Tianting Zhao, Wenhui Qin, Y uanyuan Zhao, Yingjie Guo, Haiyang Y an

提出一种全集成隔离电源传输系统，采用片上变压器和磁芯，实现52%峰值效率和1.1W输出功率。

52%峰值效率, 1.1W输出功率, 5kV隔离电压

JSSC 2019第12期Power ManagementVCONeural Network Accelerator

A Bipolar-Input Thermoelectric Energy-Harvesting Interface With Boost/Flyback Hybrid Converter and On-Chip Cold Starter Peng Cao , Student Member , IEEE, Y ao Qian ,P a nX u e

提出一种基于升压/反激混合转换器的双极性输入热电能量收集接口，实现高效能量转换与自启动。

180nm CMOS, 峰值效率84%（260mV）和79%（-300mV）, 自启动电压±129mV/±140mV

JSSC 2019第12期Data ConvertersSAR ADC

A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC

提出一种无需校准的时间交织四阶噪声整形SAR ADC，扩展带宽并保持高能效。

40nm CMOS, 50MHz带宽, 70.4dB SNDR, 13mW功耗, 0.06mm²面积

JSSC 2019第12期RF & Wireless

A. Circulator-Receiver as a Shared MIMO FD Antenna Interface This article employs the N-path-ﬁlter-based circ.-RX described in [36] in differential conﬁguration as the shared antenna interface that merges a commutation-based linear- periodically time-varying (LPTV) nonmagnetic circulator with a downconverting mixer, directly providing BB signals at its output. Each circ.-RX requires two sets of eight-phase nonoverlapping clocks with 90 ◦ phase shift to drive the

本文提出了一种基于N路径滤波器的循环器-接收器，用于MIMO全双工天线接口。

2.2 GHz, 3.5 Ω, 0.5 V

JSSC 2019第12期OtherNeural Network Accelerator

A DC-to-108-GHz CMOS SOI Distributed Power Ampliﬁer and Modulator Driver Leveraging Multi-Drive Complementary

提出一种采用堆叠增益单元和多输入驱动信号的互补分布式功率放大器，实现从直流到108 GHz的宽带平坦增益。

45nm RFSOI, 23dB增益, 108GHz带宽, 16.9dBm P1dB, 100Gb/s 64-QAM/PAM-4

JSSC 2019第12期Clocking & PLLsCrystal Oscillator

A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection Karim M. Megawer , Student Member , IEEE, Nilanjan Pal, Student Member , IEEE

提出一种采用两步注入技术的快速启动CMOS晶体振荡器，显著缩短启动时间。

54-MHz, 20 µs startup time, 34.9 nJ startup energy, 1.0-V supply

JSSC 2019第12期Power ManagementNeural Network Accelerator

A Flying-Inductor Hybrid DC–DC Converter for 1-Cell and 2-Cell Smart-Cable

提出一种新型混合DC-DC转换器，适用于1S和2S电池充电，利用飞跨电感和开关电容网络实现高效降压转换。

峰值功率12.2W和31.9W，峰值效率94.3%和97.4%

JSSC 2019第12期Power Management

A Light-Load Efﬁcient Fully Integrated V oltage Regulator in 14-nm CMOS With 25-

14nm CMOS工艺下实现轻载高效全集成电压调节器，峰值效率达88%。

14nm CMOS, 1.6–1.2V, 70MHz

JSSC 2019第12期RF & WirelessPhased ArrayNeural Network Accelerator

A Mm-Wave Wideband MIMO RX With Instinctual Array-Based Blocker/Signal Management for Ultralow-Latency Communication

毫米波宽带MIMO接收机采用基于阵列的本能空间滤波器实现快速干扰抑制

27–41-GHz, 45-nm SOI CMOS

JSSC 2019第12期Clocking & PLLsPLL

A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth

一种基于自校准16GHz子采样PLL的快速啁啾FMCW调制器，用于雷达应用。

28nm CMOS, 1.5GHz带宽, 10µs啁啾时间, 230kHz RMS频率误差

JSSC 2019第12期Other

A. Sense Phase As previously discussed in Section II-A, a PEH’s open- circuit voltage VP-OC is far less than VMPP. The difference comes from the current that ﬂows through CP , and, hence, we can recover VMPP by taking this current into account. Assuming the PEH is left in the open-circuit state, then IP = IR + IC (11) where IR and IC are the current ﬂowing through RP and CP , respectively. IR can be derived by VP /RP ,i nw h i c hRP is an unknown but ﬁxed value for a given PEH. To measure IC ,w e

该论文提出了一种通过测量电流来恢复PEH最大功率点电压的方法。

未明确提及

JSSC 2019第12期RF & WirelessTransceiver

A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS

全球首款支持5G sub-6GHz NR和LTE EN-DC的单片射频收发器，采用14nm FinFET CMOS工艺。

噪声系数6.5-9.3 dB, OOB IIP3 +3dBm, OOB IIP2 >+70dBm, EVM -39.5dB@+4dBm

JSSC 2019第12期Clocking & PLLsCrystal Oscillator

A Sub-nW 32-kHz Crystal Oscillator Architecture Based on a DC-Only Sustaining Ampliﬁer

提出一种基于直流放大的32kHz晶体振荡器架构，实现亚纳瓦级功耗。

0.55 nW, 0.5 V, 14 ppb

JSSC 2019第12期OtherPower AmplifierNeural Network Accelerator

A Super-Resolution Mixed-Signal Doherty Power Ampliﬁer for Simultaneous Linearity and Efﬁciency Enhancement Fei Wang , Student Member , IEEE,T s o - W e iL i, Member , IEEE

提出一种混合信号Doherty功率放大器，同时提升线性度和效率。

45nm SOI CMOS, 27 GHz, 40.1% PAE, 23.3-dBm Psat

JSSC 2019第12期Data ConvertersNeural Network Accelerator

A Two-Step ADC With a Continuous-Time SAR-Based First Stage Linxiao Shen , Student Member , IEEE,Y iS h e n ,Z h e l uL i ,Student Member , IEEE, Wei Shi, Student Member , IEEE, Xiyuan Tang , Student Member , IEEE

一种采用连续时间SAR作为第一级的两步ADC，显著减小输入电容尺寸并降低采样噪声。

40nm CMOS, 2 MS/s, 72-dB SNDR, 25 µW, 0.01 mm²

JSSC 2019第12期Other

A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Ampliﬁer Aoyang Zhang , Student Member , IEEE, and Mike

提出一种相位交错多子谐波开关数字功率放大器架构，提升功率回退效率并实现瓦级输出功率。

1.9GHz 30dBm峰值功率，45.9%/41.3%/35.3%/32.2%/24.2%效率（0/-3.5/-7.0/-9.5/-12dB PBO）

JSSC 2019第12期RF & Wireless

An 80-Gbs 300-GHz-Band Single-Chip CMOS Transceiver

一款80 Gb/s、300 GHz频段的单芯片CMOS收发器，采用40nm工艺，支持16QAM调制。

40nm CMOS, 80 Gb/s, 252–279 GHz, -1.6 dBm输出功率, 22.9 dB SSB NF

JSSC 2019第12期Power ManagementEnergy Harvesting

An Efﬁcient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-

提出一种高效压电能量收集接口电路，采用感知与设置整流器实现最大功率点跟踪。

0.18-µm CMOS, 0.47-mm² core area, 230-nW active power, 7-nW leakage power

JSSC 2019第12期Other

An Energy Measurement Frontend With Integrated Adaptive Background Accuracy Monitoring of the Full System Including the Current and V oltage Sensors Seyed Danesh , William Holland, George R. Spalding, Member , IEEE, Michael Guidry, a n dJ .E .D .H u r w i t z ,Member , IEEE

提出一种集成自适应背景精度监测的交流能量测量前端，用于不间断监测系统精度。

0.18 µ CMOS, 0.1% RMS电流精度, 0.25%有功能量精度

JSSC 2019第12期Clocking & PLLsPLLClock Generation

An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced V oltage Comparators Juyeop Kim , Student Member , IEEE, Y ounghyun Lim , Student Member , IEEE, Heein Y oon , Member , IEEE, Y ongsun Lee , Student Member , IEEE, Hangi Park , Student Member , IEEE, Y oonseo Cho, Student Member , IEEE, Taeho Seong , Student Member , IEEE

采用数字子采样技术的毫米波频段超低抖动频率合成器设计

28-31GHz, <80fs rms抖动, <-40dBc IPN, 41.8mW功耗

JSSC 2019第12期RF & WirelessNeural Network Accelerator

Analysis and Design of a Full-Duplex Two-Element MIMO Circulator-Receiver With H

本文提出了一种全双工双元素MIMO循环器-接收器设计，通过射频和基带自干扰消除技术实现高效能通信。

65nm CMOS, +14dBm TX功率处理, 35-45dB平均自干扰消除

JSSC 2019第12期Digital CircuitsNeural Network AcceleratorOp-Amp

C. Offset V oltage of TIAs Mismatches in the TIA circuits introduce input-referred offsets in the I and Q paths, namely, VOS ,I and VOS ,Q .T a k i n g into account the effect of offsets in Fig. 4, the following has to be satisﬁed by design to minimize the impact of the offset voltage:

该论文分析了TIA电路中的偏移电压及其对设计的影响，并提出了减少偏移电压的方法。

偏移电压小于1mV，时间常数5μS

JSSC 2019第12期Power Management

Due to the RSSM technique, the switching period varies from T [n]t o T [n + 1] randomly on a cycle-by-cycle basis. Here, n and n + 1r e p r e s e n tt h enth and the ( n + 1)th switching cycle, respectively. For stability and noise concerns, the loop gain bandwidth of the converter is usually designed lower than the switching frequency. Hence, the random T change cannot be immediately detected by the feedback controller. As a result, when the switching cycle alters from T [n]t o T [n+1] randomly, T ON [n+1] remains unchanged from TON [n].

论文分析了RSSM技术导致的开关周期随机变化对电压调节性能的影响。

无

JSSC 2019第12期Power Management

EMI-Regulated GaN-Based Switching Power Converter With Markov Continuous Random Spread-Spectrum Modulation and One-Cycle ON-Time Rebalancing

采用马尔可夫连续随机扩频调制技术的8.3MHz GaN开关电源转换器，有效降低EMI并抑制输出电压抖动。

8.3MHz, ±10%调制范围, 峰值效率86.8% @6.25W, EMI降低至35dBµV@基频

JSSC 2019第12期Other

Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)

2019年IEEE国际固态电路会议精选论文特刊，涵盖模拟、电源管理、数据转换器、射频和无线技术。

32kHz XO功耗<1nW, 启动时间<20µs(-40°C~85°C), RMS电流测量精度0.1%(1000:1动态范围)

JSSC 2019第12期Power ManagementNeural Network Accelerator

REFERENCES 1 USB Charger USB Power DeliveryUSB-IF Accessed Oct 11 2019 Online A

本文引用了多篇关于USB充电器和高效DC-DC转换器的研究论文。

94.2%峰值效率, 1.53A, 91.5%效率, 36W

JSSC 2019第12期RF & Wireless

REFERENCES [1] User Equipment (UE) Radio Transmission and Reception; Part 1: Range1 Standalone (Release 15) , document TS38101-1, 3GPP , Dec. 2018. [2] Y . Kim, P . Jang, J. Han, H. Shin, S. Ahn, D. Kwon, J. Choi, S. Kang, S. Heo, and T. B. Cho, “An RF receiver for multi-band inter- and intra- band carrier aggregation,” in Proc. IEEE Radio Freq. Integr . Circuits Symp. (RIFC) , May 2016, pp. 79–82. [3] V . Bhagavatula, D. Kwon, J. Lee, Q.-D. Bui, J.-H. Choi, S.-I. Lu, and S. Son, “A SAW-less reconﬁgurable multimode transmitter with a

多篇关于射频集成电路的论文参考文献集合

14nm FinFET CMOS, 0.4 psrms jitter, -78 dBc fractional spur

JSSC 2019第12期RF & Wireless

Sub-nW Wake-Up Receivers With Gate-Biased Self-Mixers and Time-Encoded

65nm CMOS工艺下实现亚纳瓦级唤醒接收器，采用栅极偏置自混频器和时间编码信号处理技术

434MHz时-79.1dBm灵敏度/420pW功耗，1.016GHz时-74dBm灵敏度/470pW功耗

JSSC 2019第12期Other

Substituting (39) and (40) in (38), then substituting (37) and (38) in (25) results in iM(t) = e−αt[ A cosωM t + B sin ωM t] + C cosωinjt + D sin ωinjt. (41) Using initial conditions of iM(0) = 0a n d (di M/dt)(0) = 0, results in A =− C (42) B = αA − Dωinj

论文推导了晶体振荡器在注入锁定条件下的电流响应表达式。

无具体性能指标

JSSC 2019第12期Other

Thus, the effect of process skew for given technology can be compensated by optimizing the design parameters over the process corners. A regulation scheme with a native device is also proposed to achieve a double regulation of supply variation. The whole circuit is formed in a single branch that is operated using only leakage current. The reference generator fabricated in three (SS, TT, and FF) wafers of a 0.18- μm CMOS. With an active area of 0.0045 mm

该论文提出了一种通过优化角落补偿工艺偏差的方法，并设计了一种原生器件调节方案以实现双调节供电变化。

0.18-μm CMOS, 0.0045 mm², 192 pW, 0.53% PVT variations, 0.020%/V, 33 ppm/°C

JSSC 2019第12期Power Management

Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Ampliﬁer Parisa Mahmoudidaryan , Student Member , IEEE

提出了一种宽带混合包络跟踪调制器，结合了滞环控制三电平开关转换器和增强型线性放大器。

93%峰值效率，1W输出功率，80MHz LTE包络跟踪